JPH10312357A - Data processing system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To process data in order from data having top priority by the data processing system which processes data having priority levels. SOLUTION: Priority level output means 2a of data processing circuits 2A to 2N output priority level data Pr of divided data to be outputted to a bus 1 to a bus arbitration circuit 3. The bus arbitration circuit 3 having received them selects and sends the data with top priority among the outputted priority level data Pr back to the respective data processing circuits by a priority level selecting means 3a. Then the data processing circuits 2A to 2N outputs permission request signals Re to the bus arbitration circuit 3 by request output means 2b only when the sent-back priority level data Ps matches the priority level data Pr sent by themselves. The bus arbitration circuit 3 having received the permission request signal Re outputs an acknowledgement signal Gr to the data processing circuit 2A having outputted the permission request signal Re by an acknowledgement signal output means 3b.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing system for processing a plurality of divided data, and more particularly to a data processing system for processing divided data having a priority.

[0002]

2. Description of the Related Art Conventionally, ATM (Asynchronous Transfer)
Mode), a plurality of data processing circuits that share a data bus and a bus arbitration circuit that manages the use state of the data bus are provided.

FIG. 8 is a block diagram showing a configuration of a conventional data processing system having a bus arbitration circuit. Bus 80
Denotes a data bus to which a data processing circuit 81, a data processing circuit 82, and the like are connected. When it is desired to output data on the bus 80, the data processing circuits 81 and 82 send a request signal RE requesting a bus right to the bus arbitration circuit 83.
The bus arbitration circuit 83 outputs the permission signal GR to the data processing circuit that has transmitted the request signal earliest. For example, if a permission signal is sent to the data processing circuit 82, the data processing circuit 82 acquires the right to use the bus, and can use the bus in the current cycle.

[0004]

However, in such a data processing system, regardless of the priority of data,
Since the right to use the bus is given only to the data processing circuit that has sent the request signal first, data with low priority may be processed first, and the efficiency of data processing may be reduced.

The present invention has been made in view of such a point, and an object of the present invention is to provide a data processing system capable of processing data in order of priority.

[0006]

According to the present invention, in order to solve the above-mentioned problems, as shown in FIG. 1, in a data processing system for processing data having a priority order, divided data divided into a small number of bits is used. A plurality of data processing circuits 2A to 2N for processing the data and outputting them on the bus 1, a bus arbitration circuit 3 for arbitrating the buses of the respective data processing circuits, and A priority output means 2a for outputting the priority data Pr to the bus arbitration circuit 3; and a data processing circuit which is provided in the bus arbitration circuit 3 and selects the highest priority data among the output priority data Pr and Priority selection means 3 for returning to
request output means provided in each of the data processing circuits 2A to 2N for outputting the permission request signal Re to the bus arbitration circuit 3 only when the priority data Pr output from itself and the returned priority data Ps match. 2b, bus arbitration circuit 3
And a permission signal output means 3b for outputting a permission signal Gr to the data processing circuit 2A which has output the permission request signal Re.
And a data processing system comprising:

In such a data processing system, the priority output means 2 a of the data processing circuits 2 A to 2 N outputs the priority data Pr of the divided data to be output to the bus 1 to the bus arbitration circuit 3. Bus arbitration circuit 3 receiving this
Then, the priority selection means 3a selects the highest priority data among the output priority data Pr and returns it to each data processing circuit.

In the data processing circuits 2A to 2N,
The request output means 2b outputs the priority data P output by itself.
The permission request signal Re is output to the bus arbitration circuit 3 only when r and the returned priority data Ps match. Here, it is assumed that only the data processing circuit 2A can output the permission request signal Re. In the bus arbitration circuit 3 that has received the permission request signal Re, the permission signal output means 3b outputs the permission signal Gr to the data processing circuit 2A that has output the permission request signal Re.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a conceptual diagram of the function of the present invention.
The bus 1 is a data bus to which a plurality of data processing circuits 2A to 2N are connected. The data processing circuits 2 </ b> A to 2 </ b> N process the divided data divided into a small number of bits and output the processed data to the bus 1. Each data processing circuit 2
The bus arbitration circuit 3 performs the bus arbitration of A to 2N.

The priority output means 2a of the data processing circuits 2A to 2N (only the data processing circuit 2A is shown here) outputs the priority data Pr of the divided data to be output to the bus 1 to the bus arbitration circuit 3. In the bus arbitration circuit 3 receiving this, the priority selection means 3a selects the highest priority data among the output priority data Pr and returns it to each data processing circuit.

Then, in the data processing circuits 2A to 2N,
The request output means 2b outputs the priority data P output by itself.
The permission request signal Re is output to the bus arbitration circuit 3 only when r and the returned priority data Ps match. Here, it is assumed that only the data processing circuit 2A can output the permission request signal Re. In the bus arbitration circuit 3 that has received the permission request signal Re, the permission signal output means 3b outputs the permission signal Gr to the data processing circuit 2A that has output the permission request signal Re.

When there are a plurality of data processing circuits which output the highest priority data, the permission request signal Re is sent to the bus arbitration circuit 3 by the number of the data processing circuits. In this case, the bus arbitration circuit 3 compares the priorities of the processing circuits set in advance and outputs the permission signal Gr to the data processing circuit having the highest priority.

Next, a specific configuration of the data processing system of the present embodiment will be described. FIG. 2 is a block diagram showing a schematic configuration of a network having the data processing system of the present embodiment. SDH (Syncronous Digital Hieraky) 1
0 is connected to another network,
On the other hand, an ATM is connected to the terminating device 12 via the optical line 13.
(Asynchronous Transfer Mode) Switching Device 14
Is connected.

The ATM switching device 14 is a device provided with the data processing system of the present invention. The ATM switching device 14 performs switching of the SDH data transmitted from the optical line 13 and conversion into the ATM data, and converts the SDH data into the optical line 15 and the terminal device. 16,
17 and connected to a terminal device such as a telephone or a personal computer connected thereto. The ATM switching device 14 performs switching and conversion of the ATM data of the terminal device sent from the optical line 15 into SDH data, and
Send to the side.

FIG. 3 is a block diagram showing the configuration of the data processing system in the ATM switching device 14. A data processing circuit 31 for processing cell data is provided on a data bus 21 for transmitting and receiving cell data as divided data.
To 38 are connected. These data processing circuits 31 to
38 is connected to the bus arbitration circuit 40 via the priority bus 22, the request bus 23, and the permission bus 24.
The data processing circuits 31 to 38 are assigned priorities in advance for each processing circuit. Here, the data processing circuit 31
It is assumed that the priority order for each processing circuit is higher in order from.

The data processing circuits 31 to 38 respond to the pulse from the SOC (Start Of Cell) generation circuit 50 in the bus arbitration circuit 40 and output the priority data Pr added to the cell data to be output to the data bus 21. On the priority bus 22. Here, the priority data Pr is
Four levels from the first to fourth priorities are indicated by 4-bit data. That is, in the case of the first priority, data “0001” is used, and in the case of the second priority, data “0010” is used.
In the third place, data "0100" is set, and in the fourth place, data "1000" is set by setting a bit at a position corresponding to each rank.

Upon receiving the priority data Pr, the bus arbitration circuit 40 selects the highest priority data among the output priority data and returns it to the priority bus 22. Each of the data processing circuits 31 to 38 that has received the returned priority data Ps outputs a permission request signal Re on the request bus 23 only in the case of the same priority as compared with the priority data Pr output by itself. I do. The permission request signal Re is 8-bit data, and the bits at the positions corresponding to the data processing circuits 31 to 38 are set. For example, the permission request signal Re of the data processing circuit 31
Is the first bit of the data "00000000"
1 ". Similarly, the permission request signals Re of the data processing circuits 32 to 38 are “00000010” and “0”, respectively.
0000100 ",..." 10000000 ".

When only one data processing circuit has output the permission request signal Re, the bus arbitration circuit 40 having received the permission request signal Re transmits the permission signal Gr to the data processing circuit via the permission bus 24. Output. On the other hand, when the permission request signal Re is output from a plurality of data processing circuits, the bus arbitration circuit 40 selects the data processing circuit having the highest priority among the data processing circuits and outputs the permission signal Gr. However, when the selected data processing circuit is selected in the previous SOC, the data processing circuit having the next highest priority is selected. When only the data processing circuit selected last time outputs the permission request signal Re this time,
The data processing circuit is selected.

Next, a specific logic configuration in the bus arbitration circuit 40 for outputting the permission signal Gr will be described. FIG. 4 is a block diagram showing a specific logic configuration in the bus arbitration circuit 40 for outputting the permission signal Gr. The latch unit 41 latches the priority data output from each of the data processing circuits 31 to 38. Here, for example, the data processing circuits 31 and 32 output data “0001” indicating the first priority, the data processing circuit 33 output data “0010” indicating the second priority, and the data processing circuits 34 to 3.
8 output data “0100” indicating the third priority. At this time, the latch unit 41 latches these, and stores the priority order latch data “0111”.
And Then, a determining function (not shown) selects the highest priority based on the priority latch data and returns it to each of the data processing circuits 31-38.

The decoding section 42 creates an enable for writing mask data, which will be described later, to the bank section 43. The bank unit 43 creates mask data for each priority and stores the mask data. Here, the mask data refers to the last permission signal G in the priority order of each cell data.
r indicates a data processing circuit having a processing circuit priority lower by one than the output data processing times. For example, for the first priority of the cell data, the permission signal Gr
Is the data processing circuit 33, the bank unit 43 determines that the mask data “00” indicating the data processing circuit 34 having the next lower priority by the processing circuit.
001000 ”is stored. Other data priority 2nd ~
Similar processing is performed for the fourth place.

The latch section 44 includes data processing circuits 31-31.
The 8-bit permission request signal Re output from the latch 38 is latched. Here, the highest priority data "000
The permission request signals Re “00000001” and “00000010” of the data processing circuit 31 and the data processing circuit 32 that output “1” are latched to obtain permission request latch data “00000011”.

The mask section 45 reads, from the bank section 43, mask data corresponding to the priority of the permission request latch data "00000011" latched by the latch section 44, and uses the read mask data to execute the permission request latch data. “00000011” is masked. Specifically, the mask unit 45 reads the mask data of the first priority, for example, “00001000” from the bank unit 43. Then, the mask data “0000100”
0, the lower digit, ie, 1 to
The permission request latch data is masked by a bit corresponding to the 3 bit. As a result, the permission request latch data “0”
0000011 "becomes" 0000000000 ". The masked data “0000000000” is sent to the encoding unit 46.

The encoder 46 sets only the least significant bit of the masked data and selects the
Send to For example, if the data after masking is “0000011”
If “1”, it is set to “00000001”. However,
In the above example, the data after masking is "00000000
Since it is “0”, “00000000” is sent to the selection unit 48 as it is.

On the other hand, the encoding section 47 includes a latch section 44.
Out of the permission request latch data, only the bit of the smallest digit is set and sent to the selector 48. Here, since the permission request latch data is “00000011”, the permission request latch data is sent to the selector 48 as data “00000001”.

When the data from the encoding unit 46 is other than "00000000", the selecting unit 48 always selects the data from the encoding unit 46 and outputs the permission signal G
Output to the permission bus 24 as r. On the other hand, when the data from the encoding unit 46 is “00000000”,
The selecting section 48 selects the data from the encoding section 47 and outputs it to the permission bus 24 as a permission signal Gr.
Here, the data from the encoding unit 46 is “0000”.
0000 ”, the data“ 0 ”
0000001 "is selected and output as the permission signal Gr. That is, the permission signal Gr is sent to the data processing circuit 31 this time.

The adder 49 converts the data output as the permission signal Gr into a binary number and adds "1". That is, the adding unit 49 sets the 8-bit data “0000” in advance.
Binary data "0001" to "1000" are stored in correspondence with "0000" to "10000000", respectively. When an 8-bit permission signal Gr is input, it is converted into a corresponding binary number. Add 1. For example, here, data “00000001” is converted to binary “000”.
"1" and add "1" to this to obtain "0010".
The bank unit 43 rewrites and stores the added data “0010” as new mask data of the priority. However, in the next cycle, the binary data “0010” is replaced with the 8-bit data “00000010”.
It is restored and used.

Next, the timing of the output processing of the permission signal Gr in the bus arbitration circuit 40 will be specifically described with reference to FIG. 4 and FIGS. FIG. 5 is a time chart of cycles T1 and T2 showing the timing of the output processing of the permission signal Gr in the bus arbitration circuit 40. Similarly, FIG. 6 is a time chart of cycles T3 and T4 showing the timing of the output processing of the permission signal Gr in the bus arbitration circuit 40. FIG. 7 is a diagram showing an example of mask data in the bank section 43 in each of the cycles T1 to T4.

First, as shown in FIG. 5, it is assumed that, for example, "0111" is latched by the latch unit 41 as the priority data Pr in the cycle T1. Then, the bus arbitration circuit 40 returns the data “0001” in which the highest priority bit is set as the priority data Ps. Each of the data processing circuits 31 to 3 receiving this
8, the one that sent the priority data of the first priority sends the permission request signal Re, and the latch unit 44 latches it as permission request latch data “000000011”. That is, in the cycle T1, the data processing device 3
The permission request data Re is sent from the devices 1 and 32.

Next, the permission request latch data "00000"
“011” is masked in the mask unit 45 by the mask data stored corresponding to the first priority in the bank unit 43. Priority 1 in cycle T1
As shown in FIG. 7, for example, data "00001000" having the fourth bit indicating the data processing circuit 34 is stored as the mask data of the order. Using this mask data, the permission request latch data "000000"
11 ", the masked data becomes" 0000 ".
0000 ”, and the output of the encoding unit 46 is the same“ 0 ”.
00000000 ". On the other hand, in the encoding unit 47, as described above, the permission request latch data “0000”
Only the bit corresponding to the high-priority circuit of “0011” is set and output as data “00000001”.

In this way, in the selecting section 48, the output data "00000" of the encoding section 47 in which the bit is set is output.
001 "is output as the permission signal Gr. At the same time, the adder 49 converts the data “00000001” into binary data “0001” and adds 1 to the data to obtain data “0010”. The bank unit 43 stores the added data “0010” as mask data in the cycle T2 having the highest priority. However, when used as mask data, data “0010” is restored to data “00000010” as shown in FIG.

Incidentally, as for the mask data of other priorities, the data of the previous cycle is held. In the cycle T2, as shown in FIG. 5, it is assumed that “0111” is again latched by the latch unit 41 as the priority data Pr. Then, the bus arbitration circuit 40 returns the data “0001” as the priority data Ps as in the cycle T1. Then, the permission request latch data "01
It is assumed that “000111” is latched by the latch unit 44. That is, in the cycle T2, the data processing device 3
The permission request data Re is sent from 1, 32, 33, 37.

The mask data of the first priority in the cycle T2 is “00000010” as shown in FIG. 7, and therefore, when the mask processing of the permission request latch data “01000111” is performed by the mask unit 45, the masked data becomes “0”.
1000110 ". In addition, this is
And the output data is "00000010"
Becomes The selecting section 48 outputs the output data “00000010” of the encoding section 46 as the permission signal Gr.

The adder 49 outputs the data "00000010"
1 is added to the binary data “0010” of “001”
1 ". That is, in terms of 8-bit data, “0”
0000100 ”is the first priority of the next cycle T3.
The data is stored in the bank 43 as mask data of the order (see FIG. 7).

In the cycle T3, as shown in FIG. 6, it is assumed that "0110" is latched by the latch unit 41 as the priority data Pr. The bus arbitration circuit 40 returns data "0010" in which a bit corresponding to the second highest priority in the data is set, as priority data Ps. Then, it is assumed that the permission unit latch data “11111111” is latched by the latch unit 44. That is, in the cycle T3, the permission request data Re is transmitted from all the data processing devices 31 to 38.
Has been sent.

Since the mask data of the second highest priority in cycle T3 is "00000010" as shown in FIG. 7, mask processing of the permission request latch data "11111111" by the mask unit 45 results in "1" after masking.
1111110 ". In addition, this is
And the output data is "00000010"
Becomes The selecting section 48 outputs the output data “00000010” of the encoding section 46 as the permission signal Gr.

The adder 49 outputs the data "00000010"
1 is added to the binary data “0010” of “001”
1 ". That is, in terms of 8-bit data, “0”
0000100 ”is the priority 2 of the next cycle T4
The data is stored in the bank 43 as mask data of the order (see FIG. 7).

In the cycle T4, it is assumed that "0110" is latched by the latch unit 41 as the priority data Pr. The bus arbitration circuit 40 returns, as the priority data Ps, data “0010” in which a bit corresponding to the second highest priority in the data is set, as in the cycle T3. Then, it is assumed that the permission unit latch data “11110000” is latched by the latch unit 44. That is, in cycle T3,
Permission request data Re is sent from all the data processing devices 31 to 38.

Since the mask data of the second priority in cycle T4 is "0000100100" as shown in FIG. 7, mask processing of the permission request latch data "11110000" by the mask unit 45 results in data "1" after masking.
110000 ". In addition, this is
, The output data is "00010000"
Becomes The selecting section 48 outputs the output data “00010000” of the encoding section 46 as the permission signal Gr.

Thereafter, the same procedure is repeated. As described above, in the present embodiment, the permission signal Gr is output to the data processing circuit that has output the highest priority data among the priority data Pr output from the data processing circuits 31 to 38. Processing can be performed in order from the highest data.

Further, in this embodiment, when there are a plurality of data processing circuits which output the highest priority data, the one having a higher priority set for each processing circuit is selected. Can be further enhanced.

Further, in the present embodiment, the mask data is generated such that the previously permitted data processing circuit and the data processing circuit having a higher priority than the previously permitted data processing circuit are masked at the same priority. In the case where priority data having the same content is continuously transmitted as in the cycle T1, T2 of the fifth cycle, the same data processing circuit is not continuously selected, and the data processing circuit different from the previous cycle is not selected. Can be selected. As a result, the processing is not biased toward the data processing circuit having the higher priority for each circuit.

[0042]

As described above, according to the present invention, the enable signal is output to the data processing circuit which has output the highest priority data among the priority data output from each data processing circuit. Processing can be performed in order from the data having the highest rank.

[Brief description of the drawings]

FIG. 1 is a conceptual diagram of the function of the present invention.

FIG. 2 is a block diagram illustrating a schematic configuration of a network having a data processing system according to the present embodiment.

FIG. 3 is a block diagram showing a configuration of a data processing system in the ATM switching device.

FIG. 4 is a block diagram showing a specific logic configuration in a bus arbitration circuit for outputting a permission signal.

FIG. 5 is a time chart of cycles T1 and T2 showing the timing of output processing of a permission signal in the bus arbitration circuit.

FIG. 6 is a time chart of cycles T3 and T4 showing the timing of output processing of a permission signal in the bus arbitration circuit.

FIG. 7 is a diagram illustrating an example of mask data in a bank unit in each of cycles T1 to T4.

FIG. 8 is a block diagram showing a configuration of a conventional data processing system having a bus arbitration circuit.

[Explanation of symbols]

 Reference Signs List 1 bus 2A to 2N data processing circuit 2a priority output means 2b request output means 3 bus arbitration circuit 3a priority selection means 3b permission signal output means 10 SDH network 14 ATM switching device 21 data bus 22 priority bus 23 request bus 24 permission Bus 31-38 data processing circuit 40 bus arbitration circuit

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Koichi Sugama 2-3-9 Shin-Yokohama, Kohoku-ku, Yokohama-shi, Kanagawa Prefecture Fujitsu Digital Technology Co., Ltd. In-house (72) Inventor Hiroyuki Asano 4 Kamikadanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Chome 1-1 Fujitsu Limited

Claims (5)

[Claims] 1. A data processing system for processing data having a priority order, comprising: a plurality of data processing circuits for processing divided data divided into a small number of bits and outputting the processed data to a bus; A bus arbitration circuit that performs bus arbitration; a priority output unit that is provided in each of the data processing circuits and outputs priority data of the divided data to the bus arbitration circuit; Priority selecting means for selecting the highest priority data among the priority data and returning the selected priority data to the data processing circuits; and the priority data provided in the data processing circuit and output by itself and the return. Request output means for outputting a permission request signal to the bus arbitration circuit only when the priority data matches the received priority data; A permission signal output unit that outputs a permission signal to the data processing circuit that has output the permission request signal. 2. When the plurality of permission request signals are received, the permission signal output means outputs the permission request signal to a predetermined data processing circuit having a higher priority for each processing circuit among the data processing circuits that output the permission request signal. The data processing system according to claim 1, wherein the data processing system is configured to output a permission signal. 3. The data processing circuit having a lower priority order for each processing circuit than the data processing circuit receiving the permission signal in a previous cycle. 3. The data processing system according to claim 2, wherein the data processing circuit is configured to select the data processing circuit and output the permission request signal. 4. The apparatus according to claim 3, wherein said permission signal output means is configured to store the data processing circuit to be selected in the next cycle for each priority of the divided data. Data processing system. 5. The method according to claim 1, wherein the divided data is an ATM (Asynchrono).
2. The data processing system according to claim 1, wherein the data processing system is a cell of a us transfer mode.