JP3112208B2 - Matrix network circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is applied to an information processing apparatus, a communication exchange, in particular, an ATM exchange, and other systems having a plurality of resources commonly connected by a bus.
Here, the resource refers to a memory device, an output device, a display device, an input device, a printing device, a functional unit, and other facilities including hardware for operating the system.

[0002] The present invention relates to arbitration of a plurality of access requests generated within a system with respect to a plurality of shared resources arranged in one system.

[0003]

2. Description of the Related Art Arbitration of access requests according to the prior art will be described with reference to a model shown in FIG. 6. This is based on a control method of a ring arbiter. In this model, there are eight access request sources R (1) to R (8) and eight resources S (1) to S (8) for receiving the access requests. These are connected to the input terminal group and the output terminal group of the matrix switch means, respectively. The matrix switch means may be provided with hardware having a matrix configuration as shown in the figure, or may be a virtual one constituted by a logic circuit having a matrix function as shown and capable of transmitting an access request. The number of access request sources and the number of resources need not necessarily be equal.

The access request sources R (1) to R (8) generate access requests one after another. Since an access request is generated according to the circumstances of the source, a plurality of access requests may simultaneously compete for one resource. The contention is arbitrated by the matrix switch means, and one access request source is transmitted to one request destination resource. At this time, ring arbiter RA
(1) to RA (8) sweep the access requests as indicated by arrows in FIG. 6, and when they hit the corresponding access request, the access request is unified via the intersection C (n, m). Only one is transmitted to the resource side, and the resource accepts the access request.

When one access request is accepted,
Information indicating that the request has been accepted is sent to the request source that sent the access request. By receiving one access request, another access request sent to the ring arbiter is waited, and the other access request is detected at the next timing or at the next timing. After the access request is accepted, processing such as transfer of necessary data via the matrix switch means or another bus signal line is executed.

In such arbitration control of access requests,
Ring arbiter RA for arbitration in case of conflict
Each of (1) to RA (8) can accept only one access request issued from each request source in one time slot.

[0007]

The device described in the prior art apparatus shown in FIG. 6 has eight request sources R (1) to R (8), but this number is actually several tens. Alternatively, the number is several hundred, and the time required for the ring arbiter to make a circuit at this time is not negligible.

The present invention improves on this by dividing a large-scale matrix switch into a number of small-scale matrix switches and processing contention arbitration in parallel.
It is an object of the present invention to provide a matrix network circuit capable of shortening the overall contention arbitration time and various data transfer paths.

[0009]

According to the present invention, there are provided N (N is an integer of 3 or more) request sources (R
(n), n is an integer from 1 to N) and M (M is an integer of 3 or more) resources (S (m), m is 1 to M) shared by the N access request sources And an arbitration connection for an access request generated from the request generation source, and a data transfer connection from the request generation source to the resource in accordance with the arbitration connection.

Here, a feature of the present invention is that the N request sources are divided into I (I is an integer of 2 or more) groups, and the M resources are J (J Is an integer of 2 or more), and the divided groups of the request source and the groups of the resources are mutually one small matrix switch (G
(I, j), i is an integer from 1 to I, j is an integer from 1 to J, and a total of I × J), and generates an access request and / or data from the request source. An input connection line (LI (i), i is an integer from 1 to I) for directly transferring to a small matrix switch to which a source is connected, and an access request and / or data from the small matrix switch to the resource. An output connection line (LO (j), where j is an integer from 1 to J) that directly transfers to the resources connected to the small-scale matrix switch
And at least one of them.

It is preferable that the output side of the small-scale matrix switch includes a contention arbitration means for permitting at most one access request within one unit time slot.

It is desirable that a connection circuit between each of the M resources and the output side of the small-scale matrix switch includes an OR circuit.

A connection circuit between each of the M resources and the output side of the small-scale matrix switch includes a speed conversion circuit (M (j)), and this speed conversion circuit includes a plurality of speed conversion circuits in one unit time slot. When an access request is issued to the small-scale matrix switch, the means for temporarily storing the plurality of access requests and data, and the access requests and data stored in the means for storing are stored in the next unit time slot. It is desirable to include means for transferring all of the resources.

The small-scale matrix switch (total I
× J), it is desirable to have means for executing contention arbitration so as to select one small matrix switch for one resource connected to the output side for each unit time slot.

[0015]

The large-scale matrix switch is divided into a set of small-scale matrix switches. Since the request sources and resources involved in each of the divided small matrix switches are predetermined, the intersection irrelevant to the access is skipped, and data is directly input to the small matrix switches involved in contention arbitration.

As a result, the number of passing intersections is reduced, and competition arbitration by the ring arbiter is performed in parallel for each small-scale matrix switch, so that the overall operation time can be shortened.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The configuration of a first embodiment of the present invention will be described with reference to FIG. FIG. 1 is a configuration diagram of the first embodiment of the present invention.

In the first embodiment of the present invention, eight request sources R (1) to R (8) for generating access requests, and eight request source sources R (1) to R (8) for the eight accesses are provided. ) Are provided between the eight resources S (1) to S (8) shared by the request sources R (1) to R (8). Therefore, the request sources R (1) to R
This is a matrix network circuit for performing data transfer connection from (8) to resources S (1) to S (8).

The feature of the present invention is as follows.
Request sources R (1) -R (8) are divided into four groups, and the eight resources are divided into four groups, and the divided request sources R (1) -R ( 8) and one group of resources S (1) to S (8) are mutually small one matrix switch G (1,1) to G (4,4).
And transmits access requests and / or data from the request sources R (1) to R (8) to the request sources R (1) to R (8).
R (8) connected small matrix switch G (1,1)
To the input-side connection lines LI (1) to LI for direct transfer to G (4,4).
(8) and small matrix switches G (1,1) to G (4,4)
To the resources S (1) to S (8) from the small matrix switch G (1,1) to
At least one of output side connection lines LO (1) to LO (8) for directly transferring the resources to the resources S (1) to S (8) connected to G (4,4).

Next, the operation of the first embodiment of the present invention will be described with reference to FIG. The presence or absence of an access right between the request sources R (1) to R (8) and the resources S (1) to S (8) is indicated by a grid-like horizontal line and a vertical line diagram for convenience. (1,1) 〜
Let C (8,8).

Small-scale matrix switches G (1,1) to G
When (4,4) is represented by a set of intersections C (1,1) to C (8,8), ｛C (1,1), C (1,2), C (2,1), C (2,1) 2,2)｝ ⊂G (1,
1) ｛C (1,3), C (1,4), C (2,3), C (2,4)｝ ⊂G (1,
2) ｛C (1,5), C (1,6), C (2,5), C (2,6)｝ ⊂G (1,
3) ｛C (1,7), C (1,8), C (2,7), C (2,8)｝ ⊂G (1,
4) ｛C (3,1), C (3,2), C (4,1), C (4,2)｝ ⊂G (2,
1) ｛C (3,3), C (3,4), C (4,3), C (4,4)｝ ⊂G (2,
2) ｛C (3,5), C (3,6), C (4,5), C (4,6)｝ ⊂G (2,
3) ｛C (3,7), C (3,8), C (4,7), C (4,8)｝ ⊂G (2,
4) ｛C (5,1), C (5,2), C (6,1), C (6,2)｝ ⊂G (3,
1) ｛C (5,3), C (5,4), C (6,3), C (6,4)｝ ⊂G (3,
2) ｛C (5,5), C (5,6), C (6,5), C (6,6)｝ ⊂G (3,
3) ｛C (5,7), C (5,8), C (6,7), C (6,8)｝ ⊂G (3,
4) ｛C (7,1), C (7,2), C (8,1), C (8,2)｝ ⊂G (4,
1) ｛C (7,3), C (7,4), C (8,3), C (8,4)｝ ⊂G (4,
2) ｛C (7,5), C (7,6), C (8,5), C (8,6)｝ ⊂G (4,
3) ｛C (7,7), C (7,8), C (8,7), C (8,8)｝ ⊂G (4,
4) Each of the request generation sources R (1) to R (8) and the small-scale matrix switches G (1,1) to G (4,4) are connected to the input side connection line LI.
R (1) ⇔ [LI (1)] ⇔G (1,1), G (1,2), G (1,3)
, G (1,4) R (2) ⇔ [LI (2)] G (1,1), G (1,2), G (1,3)
, G (1,4) R (3) ⇔ [LI (3)] ⇔G (2,1), G (2,2), G (2,3)
, G (2,4) R (4) ⇔ [LI (4)] ⇔G (2,1), G (2,2), G (2,3)
, G (2,4) R (5) ⇔ [LI (5)] ⇔G (3,1), G (3,2), G (3,3)
, G (3,4) R (6) {[LI (6)]} G (3,1), G (3,2), G (3,3)
, G (3,4) R (7) {[LI (7)]} G (4,1), G (4,2), G (4,3)
, G (4,4) R (8) {[LI (8)]} G (4,1), G (4,2), G (4,3)
, G (4,4). In addition, the small matrix switch G (1,
1) to G (4,4) and the resources S (1) to S (8) are independently G (1,1) and G (2) by output side connection lines LO (1) to LO (8), respectively. , 1), G (3,1), G (4,1) ⇔ [LO (1)
] ⇔S (1) G (1,1), G (2,1), G (3,1), G (4,1) ⇔ [LO (2)
] ⇔S (2) G (1,2), G (2,2), G (3,2), G (4,2) ⇔ [LO (3)
] ⇔S (3) G (1,2), G (2,2), G (3,2), G (4,2) ⇔ [LO (4)
] ⇔S (4) G (1,3), G (2,3), G (3,3), G (4,3) ⇔ [LO (5)
] ⇔S (5) G (1,3), G (2,3), G (3,3), G (4,3) ⇔ [LO (6)
] ⇔S (6) G (1,4), G (2,4), G (3,4), G (4,4) ⇔ [LO (7)
] {S (7) G (1,4), G (2,4), G (3,4), G (4,4)} [LO (8)
] ⇔ (8) is connected. To transfer data from the request source R (1) to the resource S (8), R (1) ⇒ [LI (1)] ⇒ G (1,4) ⇒ [LO (8)] ⇒ S
(8) If the data transfer path in the small-scale matrix switch G (1,4) is represented by an intersection, it is expressed as C (1,7) ⇒ C (1,8) ⇒ C (2,8). That is, three intersections C (1,7), C (1,8), C
(2,8) indicates that the transfer path is configured. This corresponds to the 15 intersections C (1,1) and C (1,1) in the conventional device.
2), C (1,3), C (1,4), C (1,5), C (1,6), C (1,
7), C (1,8), C (2,8), C (3,8), C (4,8), C (5,
8), a transfer path much smaller than the transfer path composed of C (6,8), C (7,8) and C (8,8) can be realized.

The contention arbitration on the outgoing side is not specifically described in the first embodiment of the present invention, but will be described in detail in the second and subsequent embodiments of the present invention.

Next, a second embodiment of the present invention will be described with reference to FIG. FIG. 2 is a configuration diagram of the second embodiment of the present invention. In the second embodiment of the present invention, the output side connection lines L (1) to L (8)
Is performed using the ring arbiters RA (1) to RA (8). Each ring arbiter RA (1)-RA (2)
Is C (1,1) ⇔C (2,1) ⇔C (3,1) ⇔C (4,1) ⇔C (5,1) は
C (6,1) ⇔C (7,1) ⇔C (8,1) ... RA (1) C (1,2) ⇔C (2,2) ⇔C (3,2) ⇔C (4,1) 2) ⇔C (5,2) ⇔
C (6,2) ⇔C (7,2) ⇔C (8,2) ... RA (2) C (1,3) ⇔C (2,3) ⇔C (3,3) ⇔C (4,2) 3) ⇔C (5,3) ⇔
C (6,3) ⇔C (7,3) ⇔C (8,3) ... RA (3) C (1,4) ⇔C (2,4) ⇔C (3,4) ⇔C (4, 4) ⇔C (5,4) ⇔
C (6,4) ⇔C (7,4) ⇔C (8,4)… RA (4) C (1,5) ⇔C (2,5) ⇔C (3,5) ⇔C (4,4) 5) ⇔C (5,5) ⇔
C (6,5) ⇔C (7,5) ⇔C (8,5)… RA (5) C (1,6) ⇔C (2,6) ⇔C (3,6) ⇔C (4,5) 6) ⇔C (5,6) ⇔
C (6,6) ⇔C (7,6) ⇔C (8,6)… RA (6) C (1,7) ⇔C (2,7) ⇔C (3,7) ⇔C (4,6) 7) ⇔C (5,7) ⇔
C (6,7) ⇔C (7,7) ⇔C (8,7) ... RA (7) C (1,8) ⇔C (2,8) ⇔C (3,8) ⇔C (4,7) 8) ⇔C (5,8) ⇔
C (6,8) ⇔C (7,8) ⇔C (8,8)... RA (8) is circulated to perform contention arbitration. The data transfer from the request source R (1) to the resource S (8) will be described. (1) Data from the request source R (1) is transferred to the small-scale matrix switch G (1) by the input connection line LI (1). 1,4)
(2) Transfer data to the intersection C (1,8) via the intersection C (1,7). (3) Other request sources R (2) to R (8) for the resource S (8) Arbiter RA (8)
To select only one candidate. (4) Assuming that the selected candidate is R (1), the data is input line connection line LI
It is sent to the small-scale matrix switch G (1,4) using (1), and is transferred to the resource S (8) via the output side connection line L (8).

The route for transferring contention control data from the request source R (1) to the access request to the resource S (8) is as follows: R (1) → [LI (1)] ⇒G (1,4) ⇒ [L (8)]. If this is represented by intersections C (1,1) to C (8,8), C (1,7) ⇒ ｛C (1,8) ⇔C (2,8) ⇔C (3,8) ⇔C (4,8)
⇔C (5,8) ⇔C (6,8) ⇔C (7,8) ⇔C (8,8)｝ ⇒C (1,
7), and the maximum is 1 + 8 + 8 + 1 = 18 passing intersections including the number of intersections that the ring arbiter RA (8) passes in both directions. The maximum route for transferring data from the request source R (1) to the resource S (8) is C (1,7) ⇒ C (1,8) ⇒ C (2,8) ⇒ C (3 , 8) ⇒ C (4,8) ⇒
C (5,8) ⇒ C (6,8) ⇒ C (7,8) ⇒ C (8,8), and the number of passing intersections is nine. This is compared with the conventional example device in which the number of passing intersections when transferring conflict control data is maximum, 7 + 8 + 8 + 7 = 32, and the number of passing intersections involved in data transfer is maximum, 7 + 8 = 15. This shows that the overall operation can be speeded up.

Next, a third embodiment of the present invention will be described with reference to FIG. FIG. 3 is a block diagram of the device according to the third embodiment of the present invention. In the device of the third embodiment of the present invention, the ring arbiters RA (1,1) to RA (4,4) circulate in the vertical direction in parallel for each of the small matrix switches G (1,1) to G (4,4). 8), and one candidate is selected for each of the ring arbiters RA (1,1) to RA (4,8). Four parallel bus lines are used for the output side connection lines D (1) to D (8), and these are connected to a four-input one-output FIFO (Fir
st-In-First-Out) speed conversion circuit M (1)
To M (8). Small-scale matrix switch G (1,
Since 1) to G (4,4) are vertically arranged four by one, an access request selected one by one for each of the ring arbiters RA (1,1) to RA (4,8) is output. Connection lines D (1) to D
Using (8), a four-input one-output speed conversion circuit M
(1) to M (8) and connect to resource S (1)
This data is transferred to the resource S at the speed determined by
(1) Output sequentially to S (8).

This operation will be described in more detail. The contention arbitration in the small matrix switches G (1,1) to G (4,4) is performed by the respective ring arbiters RA (1,1) to RA (4,8). )
G (1,1), G (2,1), G (3,1), G (4,1) in parallel by output side connection lines D (1) to D (8), respectively. ) ⇒ D (1) ⇒ M
(1) ⇒ S (1) G (1,1), G (2,1), G (3,1), G (4,1) ⇒ D (2) ⇒ M
(2) ⇒ S (2) G (1,2), G (2,2), G (3,2), G (4,2) ⇒ D (3) ⇒ M
(3) ⇒ S (3) G (1,2), G (2,2), G (3,2), G (4,2) ⇒ D (4) ⇒ M
(4) ⇒ S (4) G (1,3), G (2,3), G (3,3), G (4,3) ⇒ D (5) ⇒ M
(5) ⇒ S (5) G (1,3), G (2,3), G (3,3), G (4,3) ⇒ D (6) ⇒ M
(6) ⇒ S (6) G (1,4), G (2,4), G (3,4), G (4,4) ⇒ D (7) ⇒ M
(7) ⇒ S (7) G (1,4), G (2,4), G (3,4), G (4,4) ⇒ D (8) ⇒ M
(8) Transferred as S (8). The procedure for transferring contention control data and data when an access request to the resource S (8) of the request sources R (1) and R (2) occurs will be described.
Contention control data from request sources R (1) and R (2) are transferred to small matrix switch G (1,4) by input side connection lines LI (1) and LI (2), (2) The conflict control data is transferred to the intersections C (1,8) and C (2,8) via the intersections C (1,7) and C (2,7). , 8) and a ring arbiter R circulating through C (2,8)
Contention arbitration is performed by A (1,8), and one access request from either request source R (1) or R (2) is selected.
(4) Ring arbiter RA (1,8), RA (2,8), RA
In response to the independent access permission by (3,8) and RA (4,8), the request sources R (1) to R (8) transmit the data to the input side connection lines LI (1) to LI (8 ), The small-scale matrix switches G (1,4), G (2,4), G (3,4),
G (4,4), (5) Data from these small matrix switches G (1,4), G (2,4), G (3,4), G (4,4) Output side connection lines D (1)
D (8) transfers the data to the speed conversion circuit M (8). (6) In the speed conversion circuit M (8), the data is converted to 4: 1 and transferred to the resource S (8).

In this case, the data transfer path is {R (1), R (2)} ⇒ {[LI (1)], [LI (2)]}.
⇒ G (1,4) ⇒ [D (8)] ⇒ M (8) ⇒ S (8). The transfer path of the conflict control data is as follows: {R (1), R (2)}) {[LI (1)], [LI (2)]}
⇒ G (1,4) ⇒ {R (1), R (2)}. Therefore, the passing point of the competition control data is G (1,4) = {C (1,8) {C (2,8)}. The passing point of the data transfer path is C (1,7) → {C (1,8) → C (2,8)}. Therefore, the maximum number of intersections involved in the passing transfer of the contention control data is 1 + 2 + 2 + 1 = 6, and the maximum number of intersections involved in the data transfer is 1 + 2 = 3. In the prior art device, the number of intersections involved in passing transfer of competitive control data is a maximum of 7 + 8 + 8 + 7 = 30, and the number of intersections involved in data transfer is a maximum of 7 + 8 = 15. The overall operation can be performed at a higher speed as compared with the conventional device even when the delay time of the speed conversion circuits M (1) to M (8) is taken into consideration.

In the device according to the third embodiment of the present invention, all of the maximum four data transferred to the speed conversion circuits M (1) to M (8) are stored in one unit time slot in the resources S (1) to S (S).
(8), the outputs of the speed conversion circuits M (1) to M (8) are four times faster at the maximum. The first way around this is
Four times faster resources S (1) to S (8) are used. In the second method, the outputs of the speed conversion circuits M (1) to M (8) are serial-parallel converted to four parallel low-speed data, and the resources S (1) to S (8) convert them into parallel data. Configuration. Further, the third method is that the speed conversion circuits M (1) to M
(8) is further provided with arbitration means for accumulating up to four access requests and data which have entered in one unit time slot anyway, and reserving the resources S (1) to S ( 8) It is possible to adopt a configuration using a method such as handing over to. In the case of the third method, when processing cannot be executed within a predetermined time, an alarm is returned to the access requesting side.

Next, a fourth embodiment of the present invention will be described with reference to FIG. FIG. 4 is a block diagram of an apparatus according to a fourth embodiment of the present invention. The device according to the fourth embodiment of the present invention includes OR circuits OR (1) to OR (8) having four inputs and one output instead of the speed conversion circuits M (1) to M (8) in the device according to the third embodiment of the present invention. Provide. The ring arbiters RA (1) to RA (8) are the same as those in the second embodiment of the present invention. Small matrix switches G (1,1) to G (4,
The data that passed through 4) are output connection lines LO (1) to LO (8).
G (1,1), G (2,1), G (3,1), G (4,1) ⇒ [LO (1)
] ⇒OR (1) ⇒S (1) G (1,1), G (2,1), G (3,1), G (4,1) ⇒ [LO (2)
] ⇒OR (2) ⇒S (2) G (1,2), G (2,2), G (3,2), G (4,2) ⇒ [LO (3)
] ⇒OR (3) ⇒S (3) G (1,2), G (2,2), G (3,2), G (4,2) ⇒ [LO (4)
] ⇒OR (4) ⇒S (4) G (1,3), G (2,3), G (3,3), G (4,3) ⇒ [LO (5)
] ⇒OR (5) ⇒S (5) G (1,3), G (2,3), G (3,3), G (4,3) ⇒ [LO (6)
] OR (6) ⇒ S (6) G (1,4), G (2,4), G (3,4), G (4,4) ⇒ [LO (7)
] ⇒OR (7) ⇒S (7) G (1,4), G (2,4), G (3,4), G (4,4) ⇒ [LO (8)
] ⇒OR (8) ⇒S (8). The contention control data and the data transfer path from the request source R (8) to the resource S (8) will be described. (1) The contention control data from R (1) is transmitted to the input side connection line LI (1) by G Transfer to (1,4), (2) Intersection C
(3) The contention arbitration for the resource S (8) is transferred to the intersection C (1,8) via (1,7), and the ring arbiter RA (8)
And select one candidate. (4) As a result,
Assuming that the request source R (1) is selected, the data is sent to G (1,4) using the input connection line LI (1) and transferred via the output connection line LO (8). You. The data transfer path in this case is {R (1), R (2)} ⇒ {[LI (1)], [LI (2)]}.
⇒ G (1,4) ⇒ [LO (8)] ⇒ OR (8) ⇒ S (8). The transfer path of the conflict control data is as follows: {R (1), R (2)}) {[LI (1)], [LI (2)]}
=> G (1,4) => RA (8). Therefore, the passing point of the competitive control data is as follows: C (1,7) ⇒ ｛C (1,8) ⇔C (2,8) ⇔C (3,8) ⇔C (4,8)
⇔C (5,8) ⇔C (6,8) ⇔C (7,8) ⇔C (8,8)｝ ⇒C (1,
7) The data passing point is C (1,7) ⇒ {C (1,8) ⇒ C (2,8)}. Therefore, the maximum number of intersections involved in the passing transfer of the competition control data is 1 + 8 + 8 + 1 = 18, and the maximum number of intersections involved in the passing transfer of the data is 1 + 2 = 3. The maximum number of intersections involved in passing transfer of competitive control data in the conventional example device is 7 + 8 + 8 + 7 = 30, and the maximum number of intersections involved in passing transfer of data is 7 + 8 = 15. Is greatly reduced, and the overall operation can be speeded up as compared with the conventional device even in consideration of the delay time of the OR circuits OR (1) to OR (8).

Next, a fifth embodiment of the present invention will be described with reference to FIG. FIG. 5 is a block diagram of a device according to a fifth embodiment of the present invention. In the device according to the fifth embodiment of the present invention, a group composed of small-scale matrix switches G (1,2), G (2,3), G (3,4), G (4,1) is defined as an arbitration group. . Small matrix switches G (1,1) to G constituting this arbitration group
(4,4) is sequentially shifted rightward. That is, the small-scale matrix switches G (i1, j1), G (i2, j2), G (i3, j
3), G (i4, j4) ｛i1 ≠ i2 ≠ i3 ≠ i4 and j1 ≠ j 2 ≠ j3 ≠
An arbitration group is formed by j4｝.

The small matrix switch G in FIG.
(1,2), G (2,3), G (3,4), G (4,1) are the request source R
(1) to R (8) and resources S (1) to S (8), the combination of which is G (1,2); R (1), R (2) ⇔S (3) , S (4) G (2,3); R (3), R (4) ⇔S (5), S (6) G (3,4); R (5), R (6) ⇔S ( 7), S (8) G (1,2); R (7), R (8) ⇔S (1), S (2). This indicates a range in which access arbitration is performed at one access opportunity. For example, the small matrix switch G (3,4) is involved in access requests to the resources S (7) and S (8) of the request sources R (5) and R (6), and Does not participate.

At the next timing, the arbitration group is
To the right, the next arbitration group will be the small matrix switches G (1,3), G (2,4), G (3,1),
G (4,2), and the combination of the request sources R (1) to R (8) and the resources S (1) to S (8) in which they are involved is G (1,3); R (1), R (2) ⇔S (5), S (6) G (2,4); R (3), R (4) ⇔S (7), S (8) G (3,1) R (5), R (6) ⇔S (1), S (2) G (4,2); R (7), R (8) ⇔S (3), S (4). Regarding the data transfer route, regarding the access request to the resource S (8) of the request source R (1), R (1) ⇒ [LI (1)] ⇒ G (1,4) ⇒ [LO (8) ] ⇒S
(8) The transfer route of the conflict control data is as follows: R (1) → {[LI (1)], [LI (1)]} → G (1,4). Therefore, the passing intersection of the arbitration control data is as follows: C (1,7) ⇒ ｛｛C (1,8) ⇔C (2,8)｝ ⇔ ｛C (1,7) ⇔C
(1,8)｝｝ ⇒C (1,7), and the intersection of data passing is C (1,7) ⇒ {C (1,8) 2C (2,8)｝. Therefore, the maximum number of intersections involved in the transfer of contention control data is 1 + 2 + 2 + 2 + 2 + 1 = 10, and the maximum number of intersections involved in the transfer of data is 1 + 2 = 3. The maximum number of intersections involved in passing transfer of competitive control data in the conventional example device is 7 + 8 + 8 + 7 = 30, and the maximum number of intersections involved in passing transfer of data is 7 + 8 = 15. Is greatly reduced, and the overall operation can be speeded up as compared with the conventional device.

In the first to fifth embodiments of the present invention, the request sources R (1) to R (8) and the resources S (1) to S (8)
, The number of these divisions is set to four, and the number of divisions of the arbitration group is also set to four, but these numbers are not limited and can be arbitrarily configured.

[0034]

As described above, according to the present invention, a large-scale matrix switch is formed into a set of a large number of small-scale matrix switches, and the large-scale matrix switches are divided and processed in parallel to perform contention arbitration. The operation of the entire apparatus can be accelerated by shortening various data transfer paths. In the above example, the number of access request sources or resources is 4, but it is actually tens to hundreds, and the effect of this time reduction is extremely large. In addition, flexibility of the mounting form can be achieved.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an apparatus according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram of an apparatus according to a second embodiment of the present invention.

FIG. 3 is a configuration diagram of an apparatus according to a third embodiment of the present invention.

FIG. 4 is a configuration diagram of an apparatus according to a fourth embodiment of the present invention.

FIG. 5 is a configuration diagram of an apparatus according to a fifth embodiment of the present invention.

FIG. 6 is a configuration diagram of a conventional device.

[Explanation of symbols]

C (1,1) to C (8,8) intersection D (1) to D (8), L (1) to L (8), LO (1) to LO (8)
Output connection line G (1,1) to G (4,4) Small-scale matrix switch LI (1) to LI (8) Input connection line M (1) to M (8) Speed conversion circuit OR (1) ~ OR (8) OR circuit R (1) ~ R (8) Request source S (1) ~ S (8) Resource

────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Koichi Genda 1-6, Uchisaiwaicho, Chiyoda-ku, Tokyo Nippon Telegraph and Telephone Corporation (58) Field surveyed (Int.Cl. ⁷ , DB name) H04Q 3 / 52 G06F 13/362 H04L 12/28

Claims (5)

(57) [Claims] 1. An N (N is an integer of 3 or more) request sources (R (n), where n is an integer from 1 to N) for generating an access request, and the request sources are shared by the N access request sources. (M is an integer of 3 or more) (S (m), where m is an integer from 1 to M), and an arbitration connection for an access request generated from the request source and its connection. In a matrix network circuit for making a data transfer connection from said request source to said resource according to an arbitration connection, said N request sources are divided into I (I is an integer of 2 or more) groups, and said M Resources are J resources (J
Is an integer of 2 or more), and the divided groups of the request source and the groups of the resources are mutually one small matrix switch (G (i, j), i is 1 to I). integer from an integer j is from 1 to J, connected by I × J pieces) in total, a small matrix switch request source is the data access requirements Motomema from the request source is connected connect directly transferred to the input side connection line and (LI (i), i is an integer from 1 to I), wherein from the small matrix switches Motomema principal access to the resource data to the small-scale matrix switch And at least one of output connection lines (LO (j), where j is an integer from 1 to J) for directly transferring the data to a specified resource. 2. The matrix network circuit according to claim 1, further comprising: contention arbitration means for permitting at most one access request within one unit time slot on the output side of said small-scale matrix switch. 3. The matrix network circuit according to claim 2, wherein a connection circuit between each of said M resources and an output side of said small-scale matrix switch includes an OR circuit. 4. A speed conversion circuit (M (j)) is provided in a connection circuit between each of the M resources and the output side of the small-scale matrix switch, and the speed conversion circuit is provided in one unit time slot. A means for temporarily storing the plurality of access requests and data when an access request is issued to the plurality of small matrix switches; and storing the access requests and data stored in the storing means in the next unit time slot. Means for transferring all of said resources to said resources. 5. The small-scale matrix switch (total)
I × J), SoResources connected to the output side of the
One small matrix switch for eachConsists of
Group of small matrix switches for access requests
A group that performs mediation, Arbitration of this access request for each unit time slot
The group that performs the
Access request arbitration Claim 1 comprising means
A matrix network circuit as described.