JPH10254799A - Interface control method of communication device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate a recognition wait time on a response reception side after response issue, and to obtain a high-speed interface and to prevent double issue of a command by allowing each control part to monitor each area of a common memory. SOLUTION: The common memory 21 for the interface is divided into a central control part command area 21a, a central control part response area 21b, a communication control part command area 21C, and a communication control part response area 21d. Then respective control parts monitor the respective areas 21a to 21d of the common memory 21. This control method once receiving a response to a command issued on a command issue side clears the command area of the common area 21 and when a response issue side detects the command area being cleared, the normal recognition of the response issue on the response reception side which is the command issue side is detected, thereby making it ready to issue a command.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for controlling an interface between a plurality of control units of a communication device.

[0002]

2. Description of the Related Art Conventionally, in a control method in which a shared memory is used as an interface between a plurality of control units and control information is transferred in a command / response format, a next command is transmitted without waiting for completion of reception processing on a response receiving side. When the response is issued, the response receiving side cannot receive the response due to the command reception, or the next command must be received during the response reception process.
It required complicated reception processing.

As a method for preventing such a double issue of a command from each control unit, after issuing a response to the command, the response issuing side fixedly sets a time sufficient for the response receiving side to receive the response. The method of having was adopted as the first method.

[0004] As a means for avoiding simultaneous generation of commands from the central control unit to each communication control unit or from each communication control unit to the central control unit, access right to the shared memory is hardened. As a second method, a control mechanism is provided, in which only the control unit having the right to access can write and issue a command to the shared memory and prevent simultaneous issuing of commands before issuing the command. .

[0005] A third method is a method in which the processing of the received command and the processing of the command transmitted by itself are performed in a software-based multi-way manner in both control units so as to avoid the processing after issuing the commands simultaneously. Was adopted.

[0006]

However, since the response issuing side cannot confirm whether the response receiving process has been completed on the response receiving side as in the first method, the response receiving side has the following problem during the response receiving process. If a fixed time is required to prevent double issuing of commands such as receiving a command, a certain interval of waiting time will always occur until the response issuing side issues the next command. There was a disadvantage that the interface could not be realized.

In the case where the shared memory is provided with hardware access right control as in the second method, the hardware mechanism becomes complicated and the development amount increases.
There was an inconvenience such as a high product cost.

In the case where the processing of a received command and the processing of a command issued by the apparatus itself are to be performed in a multi-operated manner by software as in the third method, all the control operations that require an interface are performed. Requires a complex mechanism that operates in multiple units, which not only increases the scale of software development, but also performs avoidance processing after the simultaneous issuance of commands. Evasion processing is performed, and the processing time is increased.

The present invention has been made to solve such a conventional problem, and a first object of the present invention is to provide a high-speed interface by eliminating the recognition waiting time of a response receiving side after issuing a response. Another object of the present invention is to prevent a command from being issued twice by allowing the response issuing side to confirm whether the response receiving side has been normally received.

A second object of the present invention is to eliminate a hardware control mechanism such as giving access rights by hardware, and to reduce the scale of hardware development and product cost.

A third object of the present invention is to eliminate a complicated mechanism for operating the software in multiple ways, and to reduce the development scale of the software and the time at the interface between the control units.

[0012]

According to the first aspect of the present invention, a command section of a communication control section and a communication control section are provided in an interface section between a central control section for controlling the plurality of communication control sections. A shared memory having respective areas of a response section and a command section and a response section of the central control section is provided. When a response to a command issued by the command issuer is received, the command area of the shared memory is cleared, and the command area of the response issuer is cleared. When this is detected, the response receiving side, which is the command issuing side, detects that the response has been normally recognized, and enters the next command issuing state.

According to the present invention, each control unit monitors each area of the shared memory, so that the response issuing side can detect that the response issued by itself has been normally recognized by the response receiving side. This eliminates the waiting time on the response receiving side at the time of issuing a response, not only realizes a high-speed interface, but also prevents double issuing of commands.

According to a second aspect of the present invention, in the first aspect of the present invention, when a command is issued from the communication control unit and the central control unit at the same time, a control unit having a predetermined lower priority order has a lower priority order. Priority is given to processing for commands from high control units and responses are issued,
When a control unit with a higher priority ignores a command from a control unit with a lower priority and receives a response from a control unit with a lower priority, the next command is issued.

According to the present invention, in order to avoid simultaneous issuance of commands between the control units, priorities are determined in advance. Since the command of the communication control unit has priority, the post-processing of the command issued by the own control unit is executed, and after executing the process for the command received from the communication control unit, a response is issued to the communication control unit. on the other hand,
Since the communication control unit that has received the command is issuing a command to the central control unit, the communication control unit ignores the command from the central control unit and waits for a response reception of the command issued by itself. Upon receiving the response, the communication control unit returns to the initial state in which a command can be issued. The central control unit that has issued the response is also in a state in which a command can be reissued to the communication control unit that has been postponed.

[0016]

FIG. 1 is a block diagram of a schematic configuration of a communication device to which a method for controlling an interface of a communication device according to the present invention is applied. In the figure, the central control unit 1
Is a SIMM that functions as a main program operation area
(Single inline memory module) 11, EEPROM functioning as main program storage area
(Electrically erasable rewritable ROM) 12, RAM 13 functioning as a backup area, ROM 14 functioning as an initial diagnosis program area, CPU (central processing unit) 15 controlling central control unit 1, FPGA (field programmable gate array) ) 16 and SC
U (serial interface control device) 17 is connected to each other via a bus, and CLK (clock supply device) 18 is connected to CPU 15. The CPU 15 is connected to an external bus line.

The communication control unit 2 has a DPRAM (dual port RAM) 21 functioning as an interface shared memory and an FPGA (field programmable
Gate array) 22, CPU for controlling communication control unit 2
(Central processing unit) 23, EPROM (ultraviolet erasable rewritable R) functioning as a main program storage area
OM) 24 and an SRAM (static RAM) 25 functioning as a main program operation area are connected to each other via a bus. Further, a SYNC (cell transmission / reception control device) 26 and a CLK (clock supply device) 27 are connected to the CPU 23. ing. A DPRAM 21 as an interface shared memory is connected to an external bus line.

FIG. 2 is a diagram showing a storage area of the interface shared memory 21 for transferring control information between the central control unit 1 and the communication control unit 2, and issues a command from the central control unit 1 to the communication control unit 2. Central control unit command area 21a, a central control unit response area 21b for issuing a response from the central control unit 1 to the communication control unit 2, and a communication control unit command area for issuing a command from the communication control unit 2 to the central control unit 1. 21c, is divided into a communication control unit response area 21d for issuing a response from the communication control unit 2 to the central control unit 1, so that control information of the central control unit 1 and control information of the communication control unit 2 can be distinguished. It has become.

FIG. 3 is a flowchart showing a processing procedure for preventing a command from being issued twice at the interface between the central control unit 1 and the communication control unit 2. In the figure, the solid arrow with the tip painted indicates the flow of processing, the solid arrow without painting indicates an interrupt, and the dashed arrow indicates monitoring of the shared memory.

Referring to FIG. 1, the interface shared memory 21 for transferring control information between the central control unit 1 and the communication control unit 2 is initially cleared (step S11).

The central control unit 1 issues a control information write command "xxx request" to the command area 1 to the communication control unit 2 (step S12), and waits for a response from the communication control unit 2 (step S13). ).

The communication control unit 2 which has received the command from the central control unit 1 in the initial state (step S14) executes the processing of the control information and sends a response "xxx complete" to the central control unit 1. The command is issued (step S15), and a clear wait is performed to monitor the clearing of the command area 1 of the central control unit 1 (step S16).

The central control unit 1 that has received the response from the communication control unit 2 (step S17) clears the command area 1 (step S18), and recognizes that the communication control unit 2 has received the response normally. Let it.

When the communication control unit 2 monitoring the clearing of the command area 1 of the central control unit 1 detects that the command area 1 has been cleared, it clears the response area 2 (step S19). As a result, all processing relating to this command is completed, and both the central control unit 1 and the communication control unit 2 return to the initial state (step S11) where the next command can be issued.

FIG. 4 is a flowchart showing a processing procedure when commands are simultaneously issued at the interface between the central control unit 1 and the communication control unit 2. In the figure, an interface shared memory (DPRAM) 21 for transferring control information between the central control unit 1 and the communication control unit 2 is cleared in an initial state (step S21).

The central control unit 1 issues a control information write command "xxx request" to the command area 1 to the communication control unit 2 (step S22), and waits for a response from the communication control unit 2 (step S23). ).

The communication control unit 2 issues a control information write command "xxx request" to the command area 2 to the central control unit 1 (step S24), and waits for a response from the communication control unit 2 (step S25). ). At this point, simultaneous commands are issued between the central control unit 1 and the communication control unit 2.

The central control unit 1 having received the command from the communication control unit 2 in the response waiting state (step S26)
The command from the communication control unit 2 is prioritized, and the processing of the command issued to the communication control unit 2 is postponed (step S27).

After executing the processing of the control information for the received command (step S28), the central control unit 1 issues a response “xxx response” to the communication control unit 2 (step S29), and the communication control unit 2 to wait for clearing of the command area 2 (step S3).
0).

The communication control unit 2 that has received the command from the central control unit 1 (step S31) ignores the command because it is waiting for a response from the central control unit 1 (step S32), and waits for a response again (step S32). S33).

Upon receiving the response from the central control unit 1 (step S34), the communication control unit 2 clears the issued command area and causes the central control unit 1 to recognize that the response has been normally received (step S35). .

When the central control unit 1 monitoring the clearing of the command area 2 of the communication control unit 2 detects that the command area 2 has been cleared, the central control unit 1 clears the response area 1 which has issued the response (step S36). .

Next, the central control unit 1 determines whether or not the postponed process of issuing the command has been performed to the communication control unit 2 (step S37). If the postponed process of issuing the command has been performed, the same command is issued. As a retry process to the communication control unit 2 (step S38), and waits for a response from the communication control unit 2 (step S3).
9).

When receiving the command from the central control unit 1 (step S40), the communication control unit 2 in which the shared area is already in the initial state performs the processing of steps S29 to S36. If no command is being issued, an initial state in which the next command can be issued (step S2)
The process of returning to 1) is repeated.

In the above-described embodiment, the command issuance priority is given to the communication processing unit 2. However, the command issuance priority may be given to the central control unit 1. Good. This case can be realized by reversing the same processing by the central control unit 1 and the communication control unit 2.

[0036]

According to the present invention, each control unit monitors each area of the shared memory, so that the response issuing side detects that the response issued by itself is normally recognized by the response receiving side. This makes it possible to eliminate the recognition waiting time of the response receiving side at the time of issuing a response, and not only to realize a high-speed interface, but also to prevent double issuing of commands.

Further, according to the present invention, priorities at the time of command issuance are determined between the control units, and when commands are simultaneously issued from each control unit, the control unit with the lower priority order is replaced by the control unit with the higher priority order. Process the command from the controller and issue a response, and the higher priority control unit ignores the command from the lower priority control unit. Can be.

Further, according to the present invention, it is possible to eliminate a hardware-based control mechanism and a software-based multi-operation complex mechanism, thereby reducing the software development scale and reducing the time required for the interface between the control units. Shortening can be achieved.

[Brief description of the drawings]

FIG. 1 is a block diagram of a communication device to which the present invention is applied.

FIG. 2 is a diagram showing a storage area of an interface shared memory.

FIG. 3 is a flowchart showing a processing procedure for preventing double issuance of a command at an interface between a central control unit and a communication control unit.

FIG. 4 is a flowchart illustrating a procedure for avoiding a case in which commands are simultaneously issued at an interface between a central control unit and a communication control unit.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Central control part 2 Communication control part 21 Interface shared memory (DPRAM) 21a Central control part command area (command area 1) 21b Central control part response area (response area 1) 21c Communication control part command area (command area 2) 21d Communication control section response area (response area 2)

Claims (2)

[Claims] An interface between a plurality of communication control units and a central control unit that controls the plurality of communication control units includes a command unit and a response unit of the communication control unit and a command unit and a response unit of the central control unit. A shared memory having each area is provided, and upon receiving a response to a command issued by the command issuing side, the command area of the shared memory is cleared, and when the response issuing side detects that the command area has been cleared, the command issuing side becomes the command issuing side. An interface control method for a communication device, wherein the response receiving side detects that the response has been normally recognized, and sets a next command issuing state. 2. When a command is issued from the communication control unit and the central control unit at the same time, a predetermined low-priority control unit gives priority to a process for a command from a high-priority control unit and sends a response. Issuing a next command issuance state when the higher priority control unit ignores the command from the lower priority control unit and receives the response from the lower priority control unit. 2. The interface control method for a communication device according to claim 1.