JP3399776B2 - Computer and method for transferring peripheral device control data in computer - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer and a method for transferring peripheral device control data in a computer, and more particularly to setting and updating control data for a peripheral device connected to a peripheral device data slave control unit. The present invention relates to a computer and a method for transferring peripheral device control data required when setting and updating control data for peripheral devices.

[0002]

2. Description of the Related Art FIG. 3 shows a conventional example of a computer for setting and updating control data of a peripheral device connected to a peripheral device data slave control unit. This computer includes a main CPU 100 that controls the entire system, a CPU main bus 101 connected to the main CPU 100, and a CPU main bus 10.
1 for peripheral device data slave control unit 102 for transmitting / receiving transfer data on the CPU main bus 101
And the peripheral device data slave control unit 102 and the plurality of peripheral devices 103 _{1 to} 103 _{i to} 103 _n (where 1 ≦ i ≦ n, and hereinafter, the plurality of peripheral devices 103 _{1 to} 103 _i A peripheral I / O common bus 10 for connecting to the peripheral device group 103 _n )
4 and a control data storage memory 105 connected to the CPU main bus 101.

Next, the transfer operation of the peripheral device control data in the above computer will be described.

The main CPU 100 creates an initial setting value of the peripheral device control code in the control data storage memory 105 on the CPU main bus 101. After creating the initial setting values, the main CPU 100 sends the peripheral device control code on the control data storage memory 105 to the peripheral device data slave control unit 1 via the CPU data bus 101.
02.

Peripheral device data slave controller 10
2 are peripheral devices 103 _{1 to} 103 _{i of} a peripheral device group corresponding to a single peripheral I / O common bus 104.
The received peripheral device control code is sequentially transmitted to each of 103 _n .

The peripheral device group includes each peripheral device 103.
Response codes indicating the statuses of _{1 to} 103 _{i to} 103 _n are sequentially sent to the peripheral device data slave control unit 102. Peripheral device data for the slave controller 102, main CPU10 the sent peripheral devices 103 ₁ receives the response code for each peripheral device has 10 @ 2 to 10 @ 3 _i 10 @ 2 to 10 @ 3 each status information of _n via CPU main bus 101
0 is sequentially notified.

Then, the main CPU 100 reads out
Peripheral device 103₁-10 _i-10_nEach
From the status information, each peripheral device 103₁-10_i~
103_nChange each initial setting value of the control code of
The initial values of the changed control code have been changed to the CPU
Write to control data storage memory 105 via bus 101
Put in.

The main CPU 100 sends the setting change value of each control code for the peripheral device group on the control data storage memory 105 to the peripheral device data slave control unit 102 again via the CPU main bus 101.

When another I / O device or another memory is connected to the CPU main bus 101, during the data transfer of the above-mentioned control code setting change value, the main CPU 100 operates on the data bus. Other devices cannot be accessed, so after the data transfer by the setting change value of the control code of the peripheral device group is completed, the main C
PU 100 can access other I / O devices or other memories.

Peripheral device data slave control section 102 which has received the setting change value of the control code of the peripheral device group.
Changes the control code change value to the peripheral I / O common bus 104.
Via peripheral devices 103 _{1 to} 103 _i
Feed every 103 _n, peripheral device 103 ₁ ~103 _i ~
The control codes of 103 _n are reset sequentially.

[0011]

Since the control data transfer for setting and updating the control data for the peripheral device in the conventional computer is performed as described above, when the control data for the peripheral device is updated. In addition, C connected to other devices directly connected to the main CPU
Control data transfer of the peripheral device group on the PU main bus operates exclusively with other I / O devices to occupy the CPU main bus, and the control data transfer processing related to the peripheral device depends on the main CPU. The frequency is high, the load on the main CPU is increased, and the control processing of peripheral devices is delayed.

Further, since the CPU main bus and the peripheral I / O common bus are shared as a single data bus, data transfer for each control data setting corresponding to a plurality of peripheral devices and transfer from the peripheral devices are performed. Data transfer for reading status information as a response cannot be performed in parallel, which also makes it impossible to speed up control processing of peripheral devices.

The present invention has been made to solve the above-mentioned problems, and minimizes the load on the main CPU, and is independent of the frequently used general-purpose memory or I / O device and peripheral devices. Control data can be set and updated in parallel at the same time to speed up the control processing of peripheral devices, and only the necessary changes in the control data (control code) from the peripheral device status information can be sent to the main CPU. An object of the present invention is to obtain a computer capable of high-speed transmission and a method of transferring peripheral device control data in the computer.

[0014]

In order to achieve the above object, a computer according to the present invention has a peripheral device data slave control unit, and a peripheral device is connected to the peripheral device data slave control unit. In the above, a main CPU and a slave control unit for peripheral device data are connected by a CPU local bus, and a DMA controller, a control data storage memory of the peripheral device, and an intermediate buffer for setting the control data of the peripheral device are connected on the CPU local bus. The control data for setting / updating the peripheral device is connected between the control data storage memory and the intermediate buffer, and between the intermediate buffer and the slave control unit for peripheral device data. The DMA transfer start command issued by the main CPU Ri is for DMA transfer by the DMA controller of the channels on the CPU local bus.

In this computer, the main CPU is
A CPU other than the main bus, which only issues a DMA transfer start command, does not constantly control data transfer related to peripheral devices, and connects the I / O device of the main CPU and other memories by the channel of the DMA controller. Peripheral device control data transfer is performed at high speed by DMA transfer on the local bus. Data transfer by the DMA method on this CPU local bus is CP
Since it does not depend on data transfer on the U main bus, C
The main CPU can access any I / O device or memory on the PU main bus at any timing.

A computer according to the next invention, in the computer according to the above invention, has a status interrupt signal line for connecting the main CPU and the peripheral device data slave control unit in addition to the CPU local bus. Generation of status information in the device is transmitted to the main CPU by a status interrupt signal from the peripheral device data slave control unit to the main CPU using the status interrupt signal line, and the main CPU receives the status interrupt signal. By the main CPU
Is to issue a DMA transfer start command of status information from the peripheral device data slave controller to the intermediate buffer.

In the computer according to the present invention, the generation of status information in the peripheral device is transmitted to the main CPU by the status interrupt signal from the peripheral device data slave controller to the main CPU using the status interrupt signal line, When the main CPU receives the status interrupt signal, the main CPU issues a DMA transfer start command of status information from the peripheral device data slave control unit to the intermediate buffer. As a result, DMA transfer of status information from the peripheral device data slave control unit to the intermediate buffer is performed as an event at any time.

A computer according to the next invention is the computer according to the above-mentioned invention, wherein a plurality of peripheral devices are connected to the peripheral device data slave control section by individual peripheral I / O data buses, respectively.
The MA controller has a plurality of channels and performs DMA transfer of control data between the control data storage memory and the intermediate buffer and between the intermediate buffer and the peripheral device data slave control unit by the DMA controller. In each channel, and the DMA transfer of the control data by each channel is performed in parallel by the multi-channel control.

In the computer according to the present invention, the DMA transfer (control data transmission / reception) of the control data for setting and updating the control data of the peripheral device is carried out in parallel by the multi-channel control of the DMA controller.

In the computer according to the next invention, in the computer according to the above-mentioned invention, the status information of the peripheral device transmitted from the peripheral device data slave control unit to the intermediate buffer includes control of each peripheral device other than the control data portion. The main CPU selectively extracts the control data portion required for the change from the status information on the intermediate buffer, and includes only the portion requiring the change from the intermediate buffer. This is a DMA transfer to the storage memory.

In the computer according to the present invention, the peripheral device status information transmitted from the peripheral device data slave control unit to the intermediate buffer includes the control data change request portion of each peripheral device in addition to the control data portion. The CPU selectively extracts the control data portion necessary for the change from the status information on the intermediate buffer, and only the portion requiring the change is DMA-transferred from the intermediate buffer to the control data storage memory.

Further, the method of transferring peripheral device control data in a computer according to the present invention has a peripheral device data slave control unit, and the peripheral device control data in a computer in which the peripheral device is connected to the peripheral device data slave control unit. In the transfer method, the main CPU and the peripheral device data slave control unit are connected by a CPU local bus, and a DMA controller, a peripheral device control data storage memory, and an intermediate device for setting the peripheral device control data are connected on the CPU local bus. Connect to the buffer and set the peripheral device
Update control data is transferred between the control data storage memory and the intermediate buffer and between the intermediate buffer and the peripheral device data slave control unit by a DMA transfer start command issued by the main CPU. The CP by the channel of the DMA controller
DMA transfer is performed on the U local bus.

In the method of transferring peripheral device control data in a computer according to the present invention, the main CPU is D
Only the MA transfer start command is issued, the data transfer related to the peripheral device is not always controlled, and the CPU other than the main bus, which is connected to the I / O device of the main CPU and other memories by the channel of the DMA controller Peripheral device control data transfer is performed at high speed by DMA transfer on the local bus. Data transfer by the DMA method on the CPU local bus is performed by the CPU
Since it does not depend on the data transfer on the main bus, CP is controlled when the control data transfer of the peripheral device is being executed.
The main CPU can access any I / O device or memory on the U main bus at any timing.

A method of transferring peripheral device control data in a computer according to the next invention is the same as the method of transferring peripheral device control data in a computer according to the above invention, wherein the generation of status information in the peripheral device is different from that of the CPU local bus. The status C signal is sent from the slave controller for peripheral device data to the main CPU by using the status interrupt signal line.
When the main CPU receives the status interrupt signal and transmits it to the PU, the main CPU issues a status information DMA transfer start command from the peripheral device data slave control unit to the intermediate buffer.

In the method of transferring peripheral device control data in the computer according to the present invention, the generation of status information in the peripheral device uses the status interrupt signal line to perform the status interrupt from the slave controller for peripheral device data to the main CPU. Signal is transmitted to the main CPU, and the main CPU receives the status interrupt signal, whereby the main CPU DMAs the status information from the peripheral device data slave control unit to the intermediate buffer.
Issue a transfer start command. As a result, DMA transfer of status information from the peripheral device data slave control unit to the intermediate buffer is performed as an event at any time.

A method of transferring peripheral device control data in a computer according to the next invention is the same as the method of transferring peripheral device control data in a computer according to the invention described above, wherein a plurality of peripheral devices are individually provided in the peripheral device data slave control section. Connected via a peripheral I / O data bus, the DMA controller has a plurality of channels, between the control data storage memory and the intermediate buffer, between the intermediate buffer and the peripheral device data slave controller. Of control data between
MA transfer is performed on each channel of the DMA controller, and DMA transfer of control data by each channel is performed in parallel by multi-channel control.

In the method of transferring peripheral device control data in a computer according to the present invention, the control data DMA for setting and updating the peripheral device control data is used.
Transfer (transmission / reception of control data) is performed by synchronous transfer in parallel by the multiple channel control of the DMA controller.

A method of transferring peripheral device control data in a computer according to the next invention is the same as the method of transferring peripheral device control data in a computer according to the above invention, the peripheral device transmitting from the slave controller for peripheral device data to the intermediate buffer. Status information includes a control data change request portion of each peripheral device in addition to the control data portion.
On the intermediate buffer, from the status information,
The control data portion required for change is selectively extracted, and only the portion required for change is DMA-transferred from the intermediate buffer to the control data storage memory.

In the method of transferring peripheral device control data in a computer according to the present invention, the status information of the peripheral device transmitted from the peripheral device data slave control unit to the intermediate buffer is not limited to the control data portion, but the control data of each peripheral device is changed. Contains the requested part,
The main CPU selectively extracts the control data portion required for change from the status information on the intermediate buffer, and only the portion requiring change is DMA-transferred from the intermediate buffer to the control data storage memory.

[0030]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a computer and a method of transferring peripheral device control data in the computer according to the present invention will be described below in detail with reference to the accompanying drawings.

FIG. 1 shows a computer used for carrying out the method of transferring peripheral device control data according to the present invention. This computer includes a main CPU 1 that controls the entire system, a CPU main bus 2, a peripheral device data slave control unit 3, and a plurality of peripheral devices 5 _{1 to} 5 _{i to} 5 _n (where 1 ≦ i ≦ n And below,
The plurality of peripheral devices 5 _{1 to} 5 _{i to} 5 _n may be referred to as a peripheral device group), a CPU local bus 6 for connecting the main CPU 1 and the peripheral device slave control unit 3, and a CPU local bus 6 A control data storage memory 7 connected to the CPU local bus 6, a DMA controller 8 connected to the CPU local bus 6, an intermediate buffer 9 and 10 connected to the CPU local bus 6 for setting / updating control data for peripheral device groups, and peripherals. device 5 ₁ ~5 _i ~5
Peripheral I / O data bus 11 for individually connecting _n and the peripheral device data slave control unit 3 for each peripheral device
_{It has 1 to} 11 _{i to} 11 _n and a status interrupt signal line 12 for transmitting a status interrupt signal from the peripheral device slave controller 3 to the main CPU 1.

This computer is equipped with peripheral devices 5 ₁ ...
Between the control data storage memory 7 and the intermediate buffers 9 and 10, and between the intermediate buffers 9 and 10 and the peripheral device data slave control unit 3 of the control data for setting / updating 5 _{i to} 5 _n. Of the DMA controller 8 by the DMA transfer start command issued by the main CPU 1.
This is performed by DMA transfer on the CPU local bus 6 by the channel of.

The DMA controller 8 has a plurality of channels, and performs DMA transfer from the control data storage memory 7 to the intermediate buffer 9, DMA transfer from the intermediate buffer 10 to the control data storage memory 7, and intermediate buffer. DMA transfer from the peripheral device data slave control unit 3 to the peripheral device data slave control unit 3 and from the peripheral device data slave control unit 3 to the intermediate buffer 9 are performed on each channel of the DMA controller. DMA transfer is performed in parallel.

The status information is generated in the peripheral devices 5 _{1 to} 5 _{i to} 5 _n by the status interrupt signal from the peripheral device data slave controller 3 to the main CPU 1 using the status interrupt signal line 12. CPU
Tell 1. When receiving the status interrupt signal, the main CPU 1 issues a DMA transfer start command of status information from the peripheral device data slave control unit 3 to the intermediate buffer 10.

The DMA transfer start command issued by the main CPU 1 includes a first channel start command to a fourth channel start command.

The first channel start command is the first channel of the DMA controller 8 and is used by the control data storage memory 7
Is a command for starting the DMA transfer of the control data to the intermediate buffer 9.

The second channel start command is the second channel of the DMA controller 8 and the D of the control data from the intermediate buffer 9 to the peripheral device data slave control unit 3 is transmitted.
This is a command for starting MA transfer.

The third channel start command is a command for starting the DMA transfer of status information from the peripheral device data slave control section 3 to the intermediate buffer 10 in the third channel of the DMA controller 8.

The fourth channel start command is a command for starting the DMA transfer of control data from the intermediate buffer 10 to the control data storage memory 7 in the fourth channel of the DMA controller 8.

The status information sent from the peripheral device data slave control unit 3 to the intermediate buffer 10 includes a control data change request portion of each peripheral device 5 _{1 to} 5 _{i to} 5 _{n in addition to} the control data portion. Main CPU1
Selects and extracts the control data portion required for change from the status information on the intermediate buffer 10 and outputs only the portion requiring change to the D channel of the fourth channel to the DMA controller 8.
By issuing the MA transfer start command (fourth channel start command), DMA transfer from the intermediate buffer 10 to the control data storage memory 7 is performed.

Peripheral device data slave controller 3
Is a peripheral device for batch transfer of each device control data between the peripheral I / O data buses 11 _{1 to} 11 _{i to} 11 _n and the CPU local bus 6 in the DMA transfer of the second channel and the third channel by the DMA controller 8. This is performed via each input / output port of the data slave control unit 3.

Next, the data format on the control data storage memory 7 and the transfer data format of the peripheral device update data will be described with reference to FIG.

The main CPU 1 has the peripheral device 5 on the control data storage memory 7 as shown in FIG.
_{In the} peripheral device control data area corresponding to _{1 to} 5 _{i to} 5 _n , the corresponding peripheral device control update data is extracted and the DMA controller 8 stores the control data storage memory 7 for the extracted peripheral device control update data. After designating the memory address, a DMA transfer start command for the corresponding control update data is issued to the DMA controller 8.

The DMA controller 8 is the main CPU 1
2 (b) in response to the DMA transfer start command from
DMA of control update data configured in the transfer data format of peripheral device update data as shown in FIG.
Start the transfer.

Similarly, when the control data of another peripheral device is changed, the transfer data format of the peripheral device update data is used, and after the new control update data is created, D is changed by the updated transfer data format structure.
The DMA transfer is activated again for the MA controller 8.

Thereafter, the DMA transfer of the control update data is repeated as necessary according to the status correspondence from the peripheral devices 5 _{1 to} 5 _{i to} 5 _n .

In each DMA transfer for the control update data of these peripheral devices, each peripheral device 5 _{1 to} 5 _i
It is not necessary to reset all 5 _n control data.

Next, the procedure of high-speed transfer of control data in the computer system having the above configuration will be described.

(1) The main CPU 1 stores in the control data storage memory 7 a group of peripheral devices (peripheral devices 5 _{1 to} 5 _i
First, each initial setting value of the control data corresponding to 5 _n ) is written.

(2) After this, the main CPU 1 sends the DM
In order to start the DMA transfer from the control data storage memory 7 to the intermediate buffer 9 in the first channel of the A controller 8, a DMA first channel start command is issued to the DMA controller 8. With this command, the DMA controller 8 executes the DMA transfer from the control data storage memory 7 to the intermediate buffer 9 on the first channel.

(3) After the completion of the DMA transfer of the first channel,
The main CPU 1 issues a second DMA channel start command to the DMA controller 8 in order to start the DMA transfer from the intermediate buffer 9 to the peripheral device data slave control unit 3. As a result, the DMA transfer of the second channel by the DMA controller 8 is executed.

(4) The peripheral device data slave control unit 3 uses the second channel of the DMA controller 8 for DMA.
After receiving the transferred control data of the peripheral device group, the peripheral I / O data bus 11 _1-
Control data for each peripheral device is sent to 11 _{i to} 11 _n .

(5) Each of the peripheral devices 5 _{1 to} 5 _{i to} 5 _n forming the peripheral device group receives the control data of the corresponding peripheral device from the peripheral device data slave control unit 3, and then receives each peripheral device. Status information of I
/ O data bus 11 _{1 to} 11 _{i to} 11 _n to the peripheral device data slave control unit 3.

[0054] (6) peripheral device data for the slave control section 3 which has received the status information of each peripheral device 5 ₁ ~5 _i ~5 _n is the occurrence of each status information of the peripheral device 5 ₁ ~5 _i ~5 _n The status interrupt signal line 12 is used as a status interrupt signal to notify the main CPU 1, and the DMA controller 8 issues a request to issue the third channel start command to the main CPU 1.

(7) Upon receiving the status interrupt signal, the main CPU 1 issues a DMA transfer start command for the third channel (third channel start command) to the DMA controller 8. As a result, the DMA controller 8
DMA transfer of status information from the peripheral device data slave control unit 3 to the intermediate buffer 10 is executed on the third channel.

(8) After the completion of the DMA transfer of the third channel,
The main CPU 1 arbitrarily selects and extracts the control data portion required for the change from the status information including the control data change request of each of the peripheral devices 5 _{1 to} 5 _{i to} 5 _n on the intermediate buffer 10.

(9) The main CPU 1 transfers, from the intermediate buffer 10 to the control data storage memory 7, only the extracted control data of the peripheral devices 5 _{1 to} 5 _{i to} 5 _n on the intermediate buffer 10 that need to be changed. A fourth channel start command is issued to the DMA controller 8 for DMA transfer. This command causes the DMA controller 8 to
DMA transfer from the intermediate buffer 10 to the control data storage memory 7 is executed on the fourth channel.

(10) After the completion of the DMA transfer from the intermediate buffer 10 to the control data storage memory 7 by the fourth channel of the DMA controller 8, the main CPU 1 stores the updated control data for each peripheral device in the control data storage memory 7. In order to send it to the intermediate buffer 9, the DMA transfer start command for the first channel is issued again to the DMA controller 8.

(11) After completion of the DMA transfer relating to the control data updated in the intermediate buffer 9, the main CPU 1
On the CPU local bus 6, the second channel DMA transfer from the intermediate buffer 9 to the peripheral device data slave controller 3 by the aforementioned DMA controller 8 is executed again.

(12) By the procedure similar to the procedure described above, the updated control data of the peripheral device passes through the peripheral device data slave control unit 3 and each of the peripheral devices 5 _{1 to} 5 of the peripheral device group. _It is sent again to _{i to} 5 _n .

In the transfer of the control data as described above, the main CPU 1 does not always participate in the processing of the control data for the peripheral device on the CPU local bus 6.
U1 can arbitrarily perform other processing during the DMA transfer.

During the DMA transfer of the first channel, DM
C by other channel (2nd-4th) of A controller 8
Control data relating to other peripheral devices on the PU local bus 6 can be transferred, and the main CPU 1 sets / controls necessary control data for each of the peripheral devices 5 _{1 to} 5 _{i to} 5 _n.
D of any DMA channel (2nd-4th) for update
The MA transfer can be executed in parallel with the above-mentioned first channel DMA transfer by issuing a corresponding DMA transfer start command.

During the DMA transfer of the second channel, at the same time, the DMA transfer of the arbitrary DMA channels (first, third and fourth) relating to the arbitrary peripheral devices is performed by the D of the main CPU 1.
It can be executed in parallel by issuing an arbitrary designated channel start command to the MA controller 8, and the main CPU 1 is not always involved in the control of each DMA transfer during the DAM transfer of each channel.

Therefore, the main CPU 1 can arbitrarily access data of various I / O devices, memories, etc. on the CPU main bus 2 during the above-mentioned DMA transfer, and control the peripheral device group of the main CPU 1. The data processing load will be reduced.

[0065]

As can be understood from the above description, according to the computer of the present invention, the main CPU is DM
Only the A transfer start command is issued, the data transfer related to the peripheral device is not always controlled, and the C / CPU different from the CPU main bus to which the I / O device of the main CPU and other memories are connected by the channel of the DMA controller.
On the PU local bus, peripheral device-controlled data transfer is performed at high speed by DMA transfer, which speeds up peripheral device data transfer and reduces the load on the main CPU relating to peripheral device data transfer.
Data transfer by the DMA method on the U local bus is C
Since it does not depend on data transfer on the PU main bus, when control data transfer of peripheral devices is being executed,
The main CPU can access any I / O device or general-purpose memory on the CPU main bus at any timing, improving the data processing performance of the computer.

According to the computer of the following invention,
The generation of status information in the peripheral device is transmitted to the main CPU by the status interrupt signal from the peripheral device data slave control unit to the main CPU using the status interrupt signal line, and the main CPU receives the status interrupt signal. As a result, the main CPU issues a DMA transfer start command of status information from the peripheral device data slave control unit to the intermediate buffer, so that DMA transfer of status information from the peripheral device data slave control unit to the intermediate buffer is an event. The control data of the peripheral device can be updated in real time.

According to the computer of the following invention,
Since the DMA transfer of control data for setting and updating the control data of the peripheral device is performed in parallel by the multi-channel control of the DMA controller, the data transfer of the peripheral device is speeded up and the data of the peripheral device is increased. Transfer processing speed performance is improved.

According to the computer of the following invention,
The peripheral device status information sent from the peripheral device data slave control unit to the intermediate buffer includes the control data change request portion of each peripheral device in addition to the control data portion, and the main CPU stores the status information on the intermediate buffer. From this, the control data portion required for change is selectively extracted, and only the portion that needs to be changed is DMA-transferred from the intermediate buffer to the control data storage memory, so that an increase in data transfer required time due to useless data transfer is avoided,
The data transfer processing speed performance of the peripheral device is improved.

According to the method of transferring peripheral device control data in a computer according to the next invention, the main CP
U only issues a DMA transfer start command, does not constantly control data transfer for peripheral devices, and DM
I / O of the main CPU depending on the channel of the A controller
The peripheral device control data transfer is performed at high speed by DMA transfer on a CPU local bus different from the CPU main bus to which the O device and other memories are connected, so that the peripheral device data transfer is speeded up. The load of the main CPU relating to the data transfer of the peripheral device is reduced, and the data transfer by the DMA method on the CPU local bus does not depend on the data transfer on the CPU main bus. Therefore, the control data transfer of the peripheral device is executed. At this time, the main CPU can access any I / O device or general-purpose memory on the CPU main bus at any timing, improving the data processing performance of the computer.

According to the method of transferring peripheral device control data in a computer according to the next invention, the generation of status information in the peripheral device is notified from the peripheral device data slave control unit to the main CPU by using the status interrupt signal line. Main C by the status interrupt signal of
When the main CPU receives the status interrupt signal by transmitting it to the PU, the main CPU sends the status information D from the peripheral device data slave control unit to the intermediate buffer.
Since the MA transfer start command is issued, the DMA transfer of the status information from the peripheral device data slave control unit to the intermediate buffer is performed as an event at any time, and the control data of the peripheral device can be updated in real time.

According to the method of transferring peripheral device control data in a computer according to the next invention, the DMA transfer of control data for setting and updating the control data of the peripheral device is synchronized in parallel by the multi-channel control of the DMA controller. Since the transfer is performed, the data transfer of the peripheral device is accelerated, and the data transfer processing speed performance of the peripheral device is improved.

According to the method of transferring peripheral device control data in a computer according to the next invention, the status information of the peripheral device transmitted from the peripheral device data slave control unit to the intermediate buffer is in addition to the control data portion, The control data change request part is included, and the main CPU selectively extracts the control data part necessary for the change from the status information on the intermediate buffer,
Since only the portion that needs to be changed is DMA-transferred from the intermediate buffer to the control data storage memory, an increase in the data transfer required time due to useless data transfer is avoided, and the data transfer processing speed performance of the peripheral device is improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a computer used for implementing a method of transferring peripheral device control data according to the present invention.

FIG. 2A is an explanatory diagram showing a data format example of a control data storage memory used in the method of transferring peripheral device control data according to the present invention, and FIG. 2B is a transfer data format example of peripheral device update data. FIG.

FIG. 3 is a block diagram showing a schematic configuration of a conventional computer with peripheral devices.

[Explanation of symbols]

1 main CPU, 2 CPU main bus, 3 peripheral devices
Vise data slave controller, 5₁~ 5_i~ 5_n  Lap
Edge device, 6 CPU local bus, 7 control data
Storage memory, 8 DMA controller, 9, 10 intermediate
Buffer, 11 ₁~ 11_i~ 11_n  Peripheral I / O data
Bus, 12 status interrupt signal line.

─────────────────────────────────────────────────── ─── Continuation of front page (56) Reference JP-A-61-139865 (JP, A) JP-A-57-39439 (JP, A) JP-A-55-97630 (JP, A) JP-A-60- 136851 (JP, A) JP 62-196755 (JP, A) JP 4-350752 (JP, A) JP 8-77099 (JP, A) JP 9-62610 (JP, A) (58) Fields surveyed (Int.Cl. ⁷ , DB name) G06F 13/28 G06F 13/10 G06F 13/12

Claims (8)

(57) [Claims] 1. In a computer having a peripheral device data slave control unit and a peripheral device connected to the peripheral device data slave control unit, the main CPU and the peripheral device data slave control unit are connected by a CPU local bus. A DMA (Direct Memory) controller, a peripheral device control data storage memory, and a peripheral device control data setting intermediate buffer are connected to the CPU local bus, and the peripheral device setting / updating control data is connected. To
The main CP is provided between the control data storage memory and the intermediate buffer and between the intermediate buffer and the peripheral device data slave control unit.
The DMA transfer start command issued by U
A computer characterized by performing DMA transfer on the CPU local bus by a channel of a controller. 2. A status interrupt signal line for connecting the main CPU and the peripheral device data slave control unit is provided separately from the CPU local bus, and status information generation in a peripheral device is performed by the status interrupt signal line. A peripheral device data slave control unit sends a status interrupt signal to the main CPU from the peripheral device data slave control unit using a signal line, and the main CPU receives the status interrupt signal. 2. The computer according to claim 1, wherein a DMA transfer start command of status information from the copy unit to the intermediate buffer is issued. 3. The peripheral device data slave control unit includes a plurality of peripheral devices each having a separate peripheral I / O.
The data controller is connected by a data bus, the DMA controller has a plurality of channels, and control data between the control data storage memory and the intermediate buffer and between the intermediate buffer and the peripheral device data slave control unit. 3. The computer according to claim 1, wherein the DMA transfer is performed on each channel of the DMA controller, and the DMA transfer of the control data on each channel is performed in parallel by the multiple channel control. 4. The peripheral device status information transmitted from the peripheral device data slave control unit to the intermediate buffer includes a control data change request portion of each peripheral device in addition to the control data portion, and the main CPU
On the intermediate buffer, from the status information,
4. The computer according to claim 3, wherein the control data portion required for the change is selectively extracted, and only the portion required for the change is DMA-transferred from the intermediate buffer to the control data storage memory. 5. A method of transferring peripheral device control data in a computer having a peripheral device data slave control unit, wherein the peripheral device is connected to the peripheral device data slave control unit, wherein a main CPU and peripheral device data slave control are provided. To the CPU local bus, and a DMA (Direct Memory) controller, a peripheral device control data storage memory, and a peripheral device control data setting intermediate buffer are connected on the CPU local bus.
The main CPU issues control data for setting / updating the peripheral device between the control data storage memory and the intermediate buffer and between the intermediate buffer and the peripheral device data slave control unit. A method of transferring peripheral device control data in a computer, wherein DMA transfer is performed on the CPU local bus by a channel of a DMA controller by a DMA transfer start command. 6. The status information generation in the peripheral device is performed by a status interrupt signal from the slave controller for peripheral device data to the main CPU by using a status interrupt signal line different from the CPU local bus. 6. When the main CPU receives the status interrupt signal, the main CPU issues a status information DMA transfer start command from the peripheral device data slave control unit to the intermediate buffer. A method for transferring peripheral device control data in the computer according to [1]. 7. A plurality of peripheral devices are provided to the peripheral device data slave control unit, respectively.
The DMA controller is connected by a data bus, and the DMA controller has a plurality of channels, and control data between the control data storage memory and the intermediate buffer and between the intermediate buffer and the peripheral device data slave control unit. 7. The peripheral device control data in the computer according to claim 5, wherein the DMA transfer of the peripheral device control data is performed in each channel of the DMA controller, and the DMA transfer of the control data in each channel is performed in parallel by the multiple channel control. Transfer method. 8. The peripheral device status information transmitted from the peripheral device data slave control unit to the intermediate buffer includes a control data change request portion of each peripheral device in addition to a control data portion, and a main CPU
On the intermediate buffer, from the status information,
8. The peripheral device control data in a computer according to claim 7, wherein the control data portion required for change is selectively extracted, and only the portion required for change is DMA-transferred from the intermediate buffer to the control data storage memory. Transfer method.