JPH10143445A - Satellite line connector - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable repair or exchange while operation by improving operational reliability as the terminal station of a satellite communication network, making clear the substance of majority discrimination circuit or comparator circuit and preventing the influence of a fault or the like caused by another circuit block. SOLUTION: This device is constituted so as to write common data from a bus master 1 to N (N is an integer more than 3) memory blocks 2, 3 and 4. In this case, a control means 5 is provided. Thus, when reading the respective written data out of N memory blocks 2-4 to the bus master 1, data in (n) [(n) is an intecter less than N but more than 2] memory blocks having common data among N memory blocks 2-4 can be selectively outputted as reliable data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a satellite network connection device, and more particularly, to a redundant configuration of a memory using a majority decision.

[0002]

2. Description of the Related Art In a mesh type satellite communication network, a large number of slave stations (VSATs) are managed as control stations of the satellite communication network. In order to establish a network for communication between slave stations, management of connection information, management of channel information, and the like are performed. It also performs status management such as alarms for slave stations. In this case, high reliability is required because a single device manages the network. When a failure occurs, the system is switched to the standby system, but it is required to perform switching in a short time and hold the connection information up to that time so as not to hinder communication between slave stations. Further, when the device is switched from the active system to the standby system, the connection information up to that time is taken over, so a memory common to the redundant system devices is required.

Conventionally, a parity bit is added as a means for guaranteeing the contents of a memory. By this means,
Although an odd number of bit errors can be detected, an even number of bit errors cannot be detected. There is also a means for performing error correction by adding a redundant word. In this means, since the circuit scale is large and it is necessary to perform processing at high speed, an LSI circuit is required.

[0004] To make the memory redundant, a double C
There is a system having a memory corresponding to a PU board and a dedicated bust connecting each memory. In this method, when a failure occurs in the memory or the CPU board accessing the memory, the set of the CPU board and the memory is switched to the standby system.

FIG. 7 shows a conventional majority circuit having an error correction writing function (Japanese Patent Laid-Open No. 1-282659).
It is shown. This circuit is composed of N (odd number of N ≧ 3) memory circuits 41 and 4 storing exactly the same data.
, 43,... When outputting data, the data of the N memory circuits 41, 42, 43,. In the majority circuit having a function of outputting correct data even if a memory error occurs and detecting the memory circuit in which the error has occurred, when an error occurs in a certain memory circuit as a result of majority logic, A data latch / output circuit 54 for latching data on the majority output data path S52 using the memory error detection signal S53 for notifying an error and outputting the latched data to the data path of each memory is provided. The memory circuit which stores the incorrect data by using the error detection signal S54 as the data latch signal Since the circuit configuration includes the memory control signal generation circuit 44 for writing correct data, if an error is detected in the memory circuit serving as the majority decision circuit 45, the data after majority logic is replaced by the memory in which the error has occurred. Since the data is written into the circuit, even if an error occurs, the error is quickly corrected.

However, in such a configuration, since the majority decision circuit 45 has no specificity, its substance is unknown, and the memory control signal generation circuit 44 and the data latch / output circuit 54 themselves have failures. In
There is a disadvantage that correct data is not written in the memory circuit and the correction operation is continued forever. Further, since no erroneous data is left in the memory circuit, it becomes impossible to perform a failure analysis such as specifying a location where a failure has occurred. Also, it is not a slave station of the satellite communication network.

[0007] Further, this conventional technique requires N (N) in order to increase reliability in a bad environment such as outer space.
≧ 3 (odd number) memory circuits, and n (n <N /
In response to the error 2), correct data is determined by majority decision.

Since the number of memory circuits is increased in order to enhance the reliability, there is a disadvantage that the configuration of the control circuit portion of the memory is increased. Since the control circuit portion of the memory is a common circuit, if the reliability of this portion is reduced, the reliability of the entire memory circuit is reduced. Since the errors are only compensated for by a large number of memory circuits, the life of the device cannot be extended. Further, the reliability can be improved by error correction, but when a failure occurs in the memory, the replacement is not easy, so that the life of the device cannot be extended.

When an error occurs, a circuit that latches correct data and writes the correct data to the memory circuit in which the error has occurred generally uses a random access memory.
A memory (RAM) rarely repeats reading only, and is frequently used for repeating reading and writing. Therefore, the effect of increasing the reliability is small despite the complexity of the circuit configuration.

Japanese Patent Application Laid-Open No. 2-207355 discloses a memory reading system as shown in FIG. In FIG. 8, the CPU (central processing unit)
In response to a single read instruction to an M (read only memory) 66, the program data written in the ROM 66 three times is read three times, and the read register 6
7, the data is temporarily stored in the comparison circuit 7, and the comparison circuit 68 performs comparison and collation. Therefore, it is possible to guarantee the normality of the program data and the restoring property of the ROM 66 against garbled bits, thereby providing an effect of configuring a highly reliable system.
Even if an inexpensive, low-quality portion that is apt to be garbled is adopted, high reliability can be achieved by increasing the degree of majority of the majority logic.

[0011]

However, even in such a configuration, the substance of the comparison circuit 68 is unknown, and no coincidence data is obtained for a failure of the read register 67. Absent. Nor does it relate to a slave station of a satellite communication network.

Accordingly, an object of the present invention is to improve the operational reliability of a satellite communication network as a slave station, clarify the entities such as a majority decision circuit and a comparison circuit, and reduce the effects of failures caused by other circuit blocks. It is an object of the present invention to provide a satellite line connection device which can be repaired or replaced during driving without receiving the satellite line connection.

It is another object of the present invention to provide a memory assurance method without using a large-scale high-speed LSI and a redundancy function and hot-swapping of a memory board in which the frequency of failure occurrence is higher than that of other devices. There is also to provide a satellite line connection device having a function.

[0014]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, a satellite line connection apparatus according to the present invention provides a satellite line which writes common data from a bus master to N (N is an integer of 3 or more) memory blocks. In the connection device, the N
When reading written data from the memory blocks to the bus master, data of n (n is an integer of 2 or more) memory blocks having common data among the N memory blocks And a control means for selecting and reading the data as reliable.

Here, N = 3 and n = 2, and the data written in the first or second memory block can be selectively output. Further, data to be read from each memory block is read to the bus master via each buffer, and the control means compares data in the N memory blocks with each other and selectively outputs matched data. .

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows the configuration of an embodiment of the satellite line connection device according to the present invention. In FIG. 1, an embodiment of the present invention includes a bus master 1 (CPU (Central Processing Unit), a CPU board, a DMA (Direct Memory)).
abbreviated as "ry Access"), a controller for performing memory access using a bus or the like, a memory block 2, 3, 4, a control circuit 5 including a logic unit for controlling the memory block 2, 3, 4, and an address. It includes buffers 6, 7, and 5 for separating the bus S3.

From the bus master 1 to the memory blocks 2, 3,
4 when writing data to each memory block 2,
The common data is written to 4, 5 simultaneously. The address bus S3 is separated by buffers 6, 7, 8 so that the state of each memory block 2, 3, 4 does not affect other memory blocks. When the bus master 1 reads data from the memory blocks 2, 3, and 4, the data output from each of the memory blocks 2, 3, and 4 is subjected to majority decision processing by the control circuit 5 composed of a logic unit, and correct data is transferred to the bus master. 1 is output.

If there is a mismatch in the data output from each of the memory blocks 2, 3, and 4, the status of the memory block in which the mismatch has occurred is notified to maintenance personnel via the bus master 1 or the display of the control circuit 5. Is done. The memory blocks 2, 3, and 4 are a hot-swap unit, and a defective memory block can be repaired / replaced during operation of the apparatus. While the memory block is being pulled out, the block does not match the other blocks, and the logic unit determines that the data is correct by matching the output data from the remaining two memory blocks.
At this time, it is rare that all of the memory blocks 2, 3 and 4 do not coincide with each other, and it is very rare that the blocks actually occur. The first, second, and third buffers 6, 7, and 8 are not required when writing data to the memory blocks 2, 3, and 4, but are indispensable when reading data.

FIG. 2 is a block diagram showing details of one embodiment of the present invention. In FIG. 2, the addresses output from the bus master 201 are stored in different first, second, and third buffers 20 in order to maintain the independence of each memory block.
5, 206, 207 and output to the memory blocks 202, 203, 204 via the address bus S3. From the bus master 201 to the memory blocks 202, 203, 20
4 is written to another fourth, fifth, and sixth buffers 208, 208 similar to the address via the data bus S4.
209, 210, the memory blocks 202, 20
3, 204.

The read data to the bus master 201 output from the memory blocks 202, 203, 204 is
First, the first, second, and third comparators 211, 212, and 213
As a result, the logic values of A = B, B = C, and C = A are checked, and the result is sent to the logic circuit 215 including a logic unit. Here, A, B, and C are data stored in the memory blocks 202, 203, and 204, respectively. When all the comparison results match, the selector 214 outputs the data from A to the bus master 201 according to the output signal from the logic circuit 215. If there is a mismatch in the comparison result, the logic circuit 215 controls the selector according to the truth table of FIG.
4 outputs data to the bus master 201.

As can be seen from the truth table of FIG. 3, the output data from the memory block 204 is only input to the third comparator and is not output to the bus master 201 via the select 214. . As a result, the number of bus buffers can be reduced.

According to the comparison result, the memory block 202,
When one of the mismatches 203 and 204 is detected, the logic circuit 215 outputs the information of the memory block in which the mismatch has occurred to the bus master 201 as the status S2.
The operator performs software processing of the bus master 201,
Alternatively, the failure can be confirmed by directly confirming the status S2 with the display. Also,
The operator can remove the failed memory block at an arbitrary timing and repair / replace it. During this time, the logic unit 215 sees a mismatch between the output data from the remaining two memory blocks and outputs the data to the bus master 201 via the selector 214.

Since the memory circuits 2, 3, and 4 are hot-swap units, they can be inserted or removed at any time during operation. Even when the package of one memory circuit is removed, the bus master 1 can read the correct contents as long as the output data of the other two memories match.

FIG. 3 is a diagram showing the operation of the embodiment of FIG. In FIG. 3, the memory blocks 202,
This is the case where the stored data A, B, and C of 203 and 204 are all equal. In this case, the selector 14 selects and outputs the data A, but the same applies to the data B.

Data A and data B are equal and data C
If the data B differs from the data B, it is considered that the reliability of the data C is low, and the selector 214 selects and outputs the data A. In this case, data B may be output.

Data A and data C are equal and data C
If the data B is different from the data B, it is considered that the reliability of the data B is low, and the data A is selectively output.

When the data A and the data B are different and the data B and the data C are equal, it is considered that the reliability of the data A is low, and the data B is selectively output.

If the data A, B, and C are all different, the reliability of any of the data is low, there is no reliable data, and the system goes down. The output result at this time is denoted by X.

FIG. 4 is a circuit block diagram showing a specific circuit example of the logic circuit 215 of FIG. In FIG. 4, the logic circuit 215 includes a first matching circuit 11 for detecting a match or mismatch between data A and data B, and a second matching circuit 11 for detecting a match or mismatch between data B and data C. , A third matching circuit 13 for detecting a match or mismatch between the output signals of the first and second matching circuits 11 and 12, an output signal of the first matching circuit 11, and a second matching circuit. A fourth matching circuit 14 for detecting whether the output signal of the circuit 12 matches or does not match the inverted value with an inverter 26, and an inverted value of the output signal of the first matching circuit 11 by the inverter 27 and the second matching circuit 12 A fifth match circuit 15 for detecting a match or mismatch with the output signal, and a match or mismatch between the inverted value of the inverter 28 of the first match circuit 11 and the inverted value of the inverter 29 of the second match circuit 12 are detected. Sixth matching circuit
6, the third, fourth, fifth, and sixth matching circuits 13, 14,
First, second, third, and fourth drivers 17, 18, 19, and 20, respectively having inputs of the outputs 15 and 16;
First, second, third, and fourth alarm devices 21, 22, 23, and 24 that receive, as inputs, outputs amplified to required levels of the second, third, and fourth drivers 17 to 20, respectively. .

Here, the first to sixth matching circuits 11 to 16
Outputs a logic level 1 or H (high level), respectively, when they match, and outputs a logic level 0 or L (low level), respectively, when they do not match. First to fourth alarm devices 21,
For 22, 23, and 24, an alarm lamp or an alarm sound is used.

When the alarm lamp is used, the first alarm device 21 turns green because the data A, B, and C are all the same. The second and third alarm devices 22,
23 is preferably a yellow lamp because any one of the data A, B, and C does not match. Also, the fourth
The alarm device 24 is preferably a red lamp because none of the data A, B, and C match.

The terminals 36 and 37 are connected to the selector 215 of FIG.
When the signal level of the terminals 36 and 37 is [1, 1], the data A is selected, when the signal level is [0, 1], the data B is selected, and when the signal level is [1, 0], the data C is selected. Respectively.

The first to sixth matching circuits 11 to 6 used in FIG.
Referring to FIG. 5, which shows a specific circuit example of the first A.16, a first A having an input X and an output of the input Y inverter 30 as inputs is provided.
An ND gate 32, a second AND gate 33 that receives the output of the inverter 31 having an input X and the input Y,
O which receives each output of the second AND gates 32 and 33 as an input
An R gate 34 and an inverter 35 having an output of the OR gate 34 as an input are provided. Here, a NOR gate may be used instead of the OR gate 34 and the inverter 35.

Referring to the truth table of FIG. 6 showing the operation of the inputs X and Y and the output Z of the circuit of FIG. 5, a logic 1 level is output when they match, and a logic 0 level is output when they do not match. This is the simplest configuration logic circuit that can be used as the first to sixth matching circuits 11 to 16 in FIG.

As described above, according to the embodiment of the present invention,
The following configuration solves the problem. The minimum number of memory blocks required for majority decision is three. For reading, high reliability is obtained by outputting the value obtained by majority decision. By writing common data to each memory block at the same time as data writing, a correction data rewriting circuit is not required. The occurrence of an error in the read data is reported not to the memory block but to a mask (CPU or the like). The memory block is hot-swappable and can be replaced during operation of the device. Since the exchange of the memory blocks can be performed in a very short time, the majority decision of the two memory blocks is performed during that time.

As described above, according to the embodiment of the present invention, N (N is an odd integer of 3) memory circuits and data of the N memory circuits are determined by majority decision, and N-
Since a majority decision circuit that determines the correct value of data of n (n is an integer smaller than N) memory circuits and an error detection circuit that detects an error of the memory circuit are provided, highly reliable data is output. Automatic correction is possible by adding a latch circuit that latches the correct value after majority decision and an error correction write circuit that writes the correct value to n memory circuits that store incorrect data, if necessary. Becomes

At this time, the data output from the N memory circuits is subjected to a majority decision by a majority decision circuit, and correct data is output. However, the memory circuit which is determined by the majority decision to have an error in the data is output. Is notified of an error from the memory error generation circuit. The data latch circuit corrects the memory data by latching the correct data determined by the majority decision and rewriting the data in the memory circuit in which the error has occurred.

[0038]

According to the present invention, high reliability and continuous operation for a long period of time are possible under a general operation environment, and interruption of operation is not permitted. It is possible to switch, modify and exchange. In particular, high reliability can be obtained in a poor environment such as outer space, where repair and replacement cannot be easily performed. The function and reliability are the most important issues, and the cost is a secondary issue.

By using the redundant configuration of the memory using the majority decision of the present invention, it is possible to guarantee the contents of the memory without using an error correcting LSI.
At the same time, multiplexing of memories and hot-swapping can be performed without duplicating a bus having a low failure rate.

According to the embodiment of the present invention, the case where the number of memory blocks is three has been described. However, the present invention is not limited to this, and may be any number.

Although the matching circuit is used as the logic circuit, the present invention is not limited to this, and any logic circuit configuration may be used as long as the logic circuit has an equivalent configuration.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a block diagram showing a specific configuration example of FIG. 1;

FIG. 3 is a diagram showing a truth table of the logic circuit of FIG. 2;

FIG. 4 is a diagram illustrating a configuration of a logic circuit in FIG. 2;

FIG. 5 is a block diagram illustrating a specific example of the matching circuit of FIG. 4;

FIG. 6 is a diagram showing a truth table of FIG. 5;

FIG. 7 is a block diagram showing a first conventional technique.

FIG. 8 is a block diagram showing a second conventional technique.

[Explanation of symbols]

 1,201 Bus master 2,3,4,202-204 Memory block 5 Control circuit 6,7,8,205-210 Buffer 11-16 Matching circuit 21-24 Alarm device 26-31,35 Inverter 32,33 AND gate 34 OR gates 41 to 43 Memory circuit 44 Memory control signal generation circuit 45 Majority decision circuit 54 Data latch / output circuit 61 CPU 66 ROM 67 Read register 68, 211 to 213 Comparison circuit 214 Selector 215 Logic circuit

Claims (5)

[Claims] (1) N (N is an integer of 3 or more) from a bus master
In the satellite line connection device for writing common data to the N memory blocks, when reading the written data from the N memory blocks to the bus master, the device has the common data among the N memory blocks. A satellite line connection apparatus comprising a control means for selecting and reading data of n memory blocks (n is an integer of 2 or more smaller than N) as reliable data. 2. The satellite line connection device according to claim 1, wherein N = 3 and n = 2. 3. The satellite line connection device according to claim 2, wherein the data written in the first or second memory block is selectively output. 4. Data read from each memory block is:
The satellite line connection device according to claim 1, wherein the data is read out to the bus master via each buffer. 5. The satellite line connection device according to claim 1, wherein said control means compares data in said N memory blocks with each other and selects and outputs matched data.