JPH0922387A - Memory unit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the fault tolerance of the system of a memory unit by invalidating a memory data line in which errors frequently occur arid newly using a different memory data line instead of it. SOLUTION: Among the (m+1+x) pieces of data read from memory devices i(o)-i(m+x), only the data of valid bit lines g(o)-g(m) are outputted to data buses e(l)-e(m) by a programmable device 4. Then, checking is performed by the ECC checker of a memory controller 2. At the time, when a 1-bit error is present, an ECC 1-bit error counter (d) corresponding to the bit is increased by only one. Then, the processing is repeated, and when the ECC 1-bit error counter (d) reaches a determined number of times, it is judged that abnormality is present in the pertinent defective memory address inside the memory device (i) and the replacement operation of the data to a redundant memory line without defects is executed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to memory devices, and more particularly to fault tolerance for memory in any computer system.
e; fault tolerance) and a memory device suitable for improving reliability.

[0002]

2. Description of the Related Art As a conventional technique, Japanese Patent Laid-Open No. 6-2599
As described in Japanese Patent Publication No. 89, there is a technique of switching between two series of memory elements using a fuse. However, this technique has a problem that all the memory elements provided in two series must be switched, the utilization efficiency of the memory elements is poor, and the memory elements can be switched only once. Further, the above-mentioned conventional technology does not particularly mention the error checking method.

[0003]

A two-bit error is detected when writing to or reading from a memory.
Assume a system that uses an ECC error check code capable of 1-bit error correction. When a memory element (1 bit) is destroyed in the memory of this system, ECC1 is always used when accessing the memory element.
There is a problem in that a bit error occurs, and it takes time to correct the bit error for each access, which directly leads to system performance degradation.

Further, when another memory element (1 bit) is destroyed in the data area of the address where the already destroyed memory element (1 bit) exists, an ECC 2 bit error occurs and the system goes down. There is a point.

The present invention has been made in view of the above-mentioned problems of the prior art. Even if a memory element in the memory section is destroyed, the performance of the system is not deteriorated, and 2 bits are stored at the same address in the memory section. It is an object of the present invention to provide a memory device having improved system fault tolerance and improved reliability so that the system does not go down even if a breakdown occurs.

[0006]

A memory device according to the present invention comprises:
The present invention is applied to a memory device including a memory unit including m memory elements and a controller for the memory unit, wherein the memory unit includes the m memory elements for all memory addresses. In addition to the above, x (where x is an integer of 1 or more) memory elements for redundant bits are provided.
The control device is provided between an input / output data bus connected to an external device and a memory data signal line of the memory section, and the connection between the input / output data bus and the memory data signal line of the memory section. It is characterized by having a means for changing the.

[0007]

According to the present invention, when a defective memory element is present in the memory section, the input / output data bus connected to the external device is disconnected from the memory data signal line of the defective memory element. Instead, connect to the memory data signal line of the memory element for redundant bit and transfer the data to the memory element for redundant bit via the newly connected memory data signal line to improve the fault tolerance of the system. Can be made.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The embodiments shown in the accompanying drawings will be described below.

FIG. 1 is a block diagram showing one embodiment of the present invention. In FIG. 1, reference numeral 1 is a memory device. Further, b (0) to b (n) are, for example, C other than the memory device 1.
An input / output data bus connected to a PU, etc., (n +
1) It consists of one signal line, and may or may not include an ECC code. 2 is a memory controller,
It includes a checker / correction circuit / code generation circuit, which is a circuit for ECC code, a register used for memory line replacement described later, and the like. 3 is a counter section,
(M + 1) ECC 1-bit error counters d (0)
.About.d (m). e (0) to e (m) are (m + 1) data buses, and g (0) to g (m + x) are (m + 1 + x) memory data signal lines (however, x).
≧ 1) and 4 are programmable devices that connect the data buses e (0) to e (m) and the memory data signal lines g (0) to g (m + x) one to one. A programmable device control circuit 5 controls the programmable device 4. A memory unit 6 is composed of (m + 1 + x) memory elements i (0) to i (m + x) each having a data width, and the memory elements i (0) to i (m + x) include, as shown in FIG. Addresses 0 to h are given. The data width of the memory elements i (0) to i (m + x) is (m + 1 + x) lines as described above, but the effective signal is (m
+1) lines and the remaining x lines are redundant bit lines.

At this time, the memory elements i (0) to i (i)
(M) and memory data signal lines g (0) to g (m)
Is effective, and memory elements i (m + 1) to i (m + x)
And memory data signal lines g (m + 1) to g (m +
x) is invalid. That is, the memory data signal lines g (0) to g (m) are connected to the programmable device 4
Through the memory data signal lines g (m + 1) to e (0) to e (m), respectively.
g (m + x) is not connected to the data buses e (0) to e (m) in the programmable device 4.

Next, the programmable device 4 described above
The operation of the embodiment shown in FIG. 1 will be described based on the connection state of FIG. The ECC 1-bit error counters d (0) to d (m) shown in FIG. 1 are reset every unit time z. This is because whether or not the memory elements i (0) to i (m) are abnormal should be determined not by the total amount of errors but by the number of errors per unit time. Therefore, first, the error count time z, which is the upper limit of the timer existing in the memory controller 2, is set. And
Next, E, which is a standard for determining that the memory is defective
The maximum value y of the count numbers of the CC1 bit error counters d (0) to d (m) is set. Then, when the timer reaches the specified time z, the ECC 1-bit error counter d
The timers (0) to d (m) are reset.

When writing data to the memory device 1 of FIG. 1, the data input from the input / output data buses b (0) to b (n) b is corrected by the memory controller 2 using the ECC error correction code. , Data buses e (0) to e
Sent to (m). At this point, the data should be error free. Then, it is stored in the memory elements i (0) to i (m) through the programmable device 4 and the memory data signal lines g (0) to g (m). At this time, the effective signal width is (m + 1) lines, the remaining x lines are redundant bit lines, and are not connected to the data buses e (0) to e (m).

Next, consider the case of reading data from the memory device 1 of FIG. Memory elements i (0) to i (m +
Of the (m + 1 + x) pieces of data read from x), only the valid data of the bit lines g (0) to g (m) is transferred by the programmable device 4 to the data bus e.
(1) to e (m) are output. Then, it is checked by the ECC checker of the memory controller 2. if,
At this time, if there is a 1-bit error, the ECC 1-bit error counter d corresponding to the corresponding bit is incremented by 1. Then, this process is repeated, and when the ECC 1-bit error counter d reaches the determined number y, it is determined that there is an abnormality in the corresponding defective memory address line in the memory element i, for example, the memory element i (3) has a defect,
Assuming that the memory element i (m + 1) is a redundant memory line having no defect, data replacement work from i (3) to i (m + 1) is executed.

FIG. 2 is a flow chart showing the operation of the memory device 1 described above. In step 100 of FIG. 2, the error count time z which is the upper limit of the timer existing in the memory controller 2 is set. Next, in step 101, an ECC 1-bit error counter d (0) serving as a reference for determining that the memory is defective.
The maximum value y of the count numbers of ~ d (m) is set. Next, in step 102, the ECC 1-bit error counters d (0) to d (m) are reset. Next, in step 103, the timer in the memory controller 2 is reset.

Next, at step 104, it is judged if the count value of the timer has reached the error count time z, and if it is judged that it has reached the error count time z, the routine returns to step 102. When it is determined that the processing has not arrived, it is determined in step 105 whether the processing to be executed is the memory read processing. If it is determined that the memory read processing is not performed, in step 111,
After the general processing such as the memory write processing and the memory refresh processing described above is performed, the process returns to step 104. If the memory read process is determined in step 105, the memory read process is executed in step 106. Then, in step 108, E
It is determined whether or not a CC1 bit error has occurred. If it is determined that a CC1 bit error has not occurred, the process returns to step 104, and if it is determined that it has occurred, then in step 108 the ECC1 bit error counter corresponding to the relevant bit. Increase d by 1. Next, in step 109, it is determined whether or not the count value of the ECC 1-bit error counter d has reached the determined number of times y. If it has not reached, the process returns to step 104, and if it has reached, In step 110, the memory data signal line g corresponding to the bit is replaced. For example,
Memory data signal line g (3) of memory device i (3)
From the memory element i (m + 1) to the memory data signal line g (m + 1). Two examples of this work are given below.

FIG. 3 is a flowchart showing the first replacement process. In the following description, the memory element i
From the memory data signal line g (3) of (3) to the memory data signal line g (m + 1) of the memory element i (m + 1).
The replacement work will be described as an example. In step 120, the addresses are set to memory elements i (0) to i (m + x).
The lowest value of In the embodiment shown in FIG. 1, the address is set to "0" which is the lowest address. Then, in step 121, the data is read from the memory elements i (0) to i (m) into the register of the memory controller 2, and in step 123, if there is an ECC 1-bit error, it is corrected. Next, in step 123, the programmable device control circuit 5 is used to rewrite the contents of the programmable device 4, and the connection is changed from e (3) to g.
Change from (3) to e (3) to g (m + 1). next,
In step 124, the memory data read into the register of the memory controller 2 in step 121 is written in the memory element i. At this time, the memory elements i (0) to i
(2), data may be written to all bits of i (4) to i (m + 1), or memory data may be written only to the memory element i (m + 1). Then, in step 125, it is determined whether or not the address is the maximum value. If it is determined that the address is not the maximum value, the address is incremented by 1 in step 126. Subsequently, in step 127, the programmable device control circuit 5 is used to rewrite the contents of the programmable device 4, and the connection is returned from e (3) to g (m + 1) to e (3) to g (3), Return to step 121. The cycle of steps 121 to 127 is repeatedly executed until the address reaches the maximum value. In step 125, when the address reaches the maximum value of the memory element i, the programmable device 4
From e (3) to g (3) to e (3) to g (m +
The process is terminated in the state of changing to 1), and the programmable device control circuit 5 stores information that i (3) has a defect. By these operations, the memory element i (3) becomes invalid and the memory element i (m + 1) becomes valid.

FIG. 4 is a flowchart showing the second replacement process. In the following description, the memory element i
From the memory data signal line g (3) of (3) to the memory data signal line g (m + 1) of the memory element i (m + 1).
The replacement work will be described as an example. In step 130, the address is set to the lowest value of the memory device i. FIG.
In the embodiment shown in (1), the address is set to "0" which is the lowest address. Next, in step 131,
By using the programmable device control circuit 5, the contents of the programmable device 4 are rewritten and the connection is changed.
Change from (3) to g (3) to e (3) to g (m + 1). At this time, bit 3 of the defective data, that is, the data of the portion corresponding to i (3) of the memory is completely lost. Next, in step 132, the data is read from the memory device i into the register of the memory controller 2, bit 3 of the data is created using the ECC code, and the data is written in the memory device i. At this time, the memory element i
Data may be written to all bits of (0) to i (2) and i (4) to i (m + 1), or may be written only to the memory element i (m + 1). Next, in step 135, it is determined whether or not the address is the maximum value. If it is determined that the address is not the maximum value, the address is incremented by 1 in step 136 and the process returns to step 132. Step 13
At 5, when the address reaches the maximum value of the memory element i, the processing is terminated, and information that the memory element i (3) has a defect is stored in the programmable device control circuit 5. By these operations, the memory element i (3) becomes invalid and the memory element i (m + 1) becomes valid.

In the above example, the information that the memory device i (3) is defective is stored in the programmable device control circuit 5, but in order to efficiently perform this defective memory storage processing, To do so. First, when the system is operated for the first time, it is assumed that the memory element i having a low number (i (0) to i (m)) is used, and the maximum value p (in this case) of the numbers used. Then, p = m) is stored in a valid data number register (not shown) in the programmable device control circuit 5. When a defect occurs, the memory element i (p + 1)
In order to newly make effective, the memory device i (p + 1) is connected to the system using the programmable device 4, and the value p of the effective data number register is incremented by 1. In this case, the memory elements i (1) to i (p) are either valid or defective, and i (p + 1) to
i (max) is all invalid (redundant), but it is not defective.

In the embodiment shown in FIG. 1, redundant bits (memory elements i (m + 1) to i (m + x)) of the entire memory elements i (0) to i (m) of the memory section 6 are regarded as one block.
Then, the memory data line was replaced. However, in this case, when one memory cell is defective, it is necessary to invalidate the entire address area and replace the data. For this reason, it takes a very long time to transfer data, and it is inefficient in terms of effective utilization of memory resources. Therefore, in the case where a defective memory cell is detected by dividing the memory unit 6 into a plurality of blocks, and providing each of the divided memory blocks with the circuit shown in FIG. 1 in whole or in part. A defective data bit line (defective memory) may be partially replaced in the address area of the memory as in the above-described embodiment.

When a defective data bit (defective memory) is found, the memory data line is replaced by the above procedure. Since this replacement usually requires a considerable processing time, the CPU processing must be stopped. Therefore, when the programmable device control circuit 5 of FIG. 1 is provided with an interrupt signal issuing logic to the CPU to detect a defective data bit (defective memory) and replace the memory data line, this interrupt signal is issued. Then, a normal CPU process may be temporarily stopped and the memory data line may be replaced.

As is clear from the above description, ECC check of input data and 1-bit error correction are possible,
In a memory device including a control device capable of performing an ECC check of output data and a memory unit, a counter having the same number as the input / output data bus width of the memory device is provided, and the input / output data bus and the counter are provided for each bit (each memory element). ), When the memory device detects an ECC 1-bit error when outputting data from the memory unit, the corresponding counter is incremented by 1, and the number of occurrences of the ECC 1-bit error is calculated for each input / output bit of each memory data. By making it possible to record, which memory element of the memory unit is corrected by the ECC code for each access and causes the performance deterioration due to the increase in processing time, or which bit (memory element) is abnormal You can know.

When the counter reaches a certain value within a certain fixed time, it is recognized that the corresponding memory element has an abnormality, the programmable device is rewritten, and the memory data signal of the memory having the abnormality is detected. The line is disconnected from the input / output data bus of the memory device, and instead the redundant bit of the memory is connected to the input / output data bus of the memory control device. The fault tolerant against the error of the memory part is improved by providing the controller or software that corrects the stored contents of the memory device disconnected at this time using the ECC code and then stores it in the newly connected memory device. Can be made.

As is clear from the above description, according to the above embodiment, the following effects can be obtained. That is, in the prior art, the ECC capable of detecting a 2-bit error and a 1-bit error correction for writing to or reading from the memory
In the system that uses error check code,
When a certain bit of this memory is destroyed, an ECC 1-bit error always occurs when accessing that bit, and a time for correcting this error is required for each access, resulting in system performance degradation. Further, if the data area is destroyed by another bit at the same address, an ECC 2-bit error occurs and the system goes down. On the other hand, in the above-described embodiment, the data bit line in which the ECC 1-bit error frequently occurs is detected, the error frequent memory data line is invalidated, and another memory data line is newly used instead, so that the system It is effective in improving fault tolerance, can prevent performance degradation and system down, and helps improve reliability.

[0024]

According to the present invention, even if a memory element in the memory section is destroyed, the performance of the system is not degraded, and even if two bits are destroyed at the same address in the memory section, the system does not go down. As described above, it is possible to improve the fault tolerance of the system, prevent performance deterioration and system down, and have an effect of improving reliability.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a flowchart showing the operation of the embodiment shown in FIG.

FIG. 3 is a flowchart showing an example of a data replacement process shown in FIG.

FIG. 4 is a flowchart showing an example of a data replacement process shown in FIG.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Memory device, 2 ... Memory controller, 3 ... Counter part, 4 ... Programmable device, 5 ... Programmable device control circuit, 6 ... Memory part, b (0) -b
(N) ... Input / output data bus, d (0) to d (m) ... EC
C1 bit error counter, e (0) to e (m) ... Data bus, g (0) to g (m + x) ... Memory data signal line, i (0) to i (m + x) ... Memory device.

Claims (1)

[Claims] 1. A memory section comprising m memory elements,
In a memory device including a memory unit control device, the memory unit has x (where x is an integer of 1 or more) for all memory addresses, in addition to the m memory elements.
The redundant bit memory element is provided, and the control device is provided between an input / output data bus connected to an external device and a memory data signal line of the memory section, and the input / output data bus is provided. And a means capable of changing the connection between the memory section and the memory data signal line of the memory section.