JPH0316655B2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention provides a method for coexisting data, error detection/correction bits, and parity bits in a storage module.
Regarding storage devices that detect and correct data errors,
More specifically, if a parity error is not detected during partial write, the process immediately switches to a write cycle, composes a word with data read from the storage module and data to be actually written, and writes it to the storage module. The present invention relates to a storage device that achieves shortened access time and improved reliability.

[Prior Art] Computer systems are required to have higher reliability and higher speed as the amount of information processed increases and as service formats evolve to online real-time processing. For this purpose, a storage device that can perform data storage operations and input/output operations at high speed and has high reliability is required.

As a technology for increasing the reliability of storage devices, there is a technology that incorporates an error detection and correction (ECC) circuit to check whether there are any errors in the information read from the storage module and to correct any errors found. .

There is also a device that stores parity bits along with data in a storage module, and performs a parity check upon reading to detect errors.

[Problems to be solved by the invention] There are various methods for error detection/correction circuits, but
Since high-speed performance is required in the main storage device, a single error correction/double error detection code is often used. However, even if this error detection/correction code is used, time is required to detect and correct errors, which is a major obstacle in increasing the speed of storage devices.

For example, 1 word = 32 bits (4 bytes) + ECC
In the case of a storage device with a bit (7-bit) configuration, it is not necessarily always accessed using 32 bits.
The byte length of write operations to the storage device by microprocessor instructions, etc. is random (1, 2, 3...bytes), and it is necessary to rewrite only a certain byte of one word (this is called a "partial write"). Particularly in the case of such a partial write operation, there is a problem that the access time becomes long because the following access procedure is normally used.

(1) Read data from the storage module (memory read cycle).

(2) Input the read data to the error detection/correction circuit and inspect the data.

(3) Construct a word by combining the output data of the error detection/correction circuit and the data to be actually written.

(4) Write the data configured in this way to the storage module (memory write cycle).

On the other hand, the method of detecting errors by parity check can speed up the access time during normal operation, but since it only detects errors, the system can go down even if a parity error occurs. There is a risk that the data will deteriorate, and a highly reliable storage device cannot be realized. This is because when a parity error is detected, the error is detected or the contents are reported and stored, and subsequent operations are temporarily discontinued.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the drawbacks of the prior art as described above, and to provide a storage device that is highly reliable and can operate at high speed during partial writing.

[Means for Solving the Problems] The present invention, which can achieve the above objects, uses a storage module in which error detection/correction bits and parity bits coexist with data, and incorporates parity checking into error detection/correction operations. This is a storage device in which data is corrected using an error detection/correction circuit only when a parity error occurs.

The storage device according to the present invention includes data, error detection and
A storage module in which correction bits and parity bits are stored, means for writing parity bits into the storage module, means for parity checking information read from the storage module, and writing of error detection/correction bits into the storage module and reading from the storage module. an error detection/correction circuit that detects and corrects errors in the data; a first multiplexer that selects and outputs write data from the data bus and output data from the error detection/correction circuit; and a second multiplexer for selecting the output of the write data register and read data from the storage module and supplying the selected data to an error detection/correction circuit.

When partially writing to the storage module, if there is no parity error in the information read from the storage module, the program immediately switches to the write cycle, composes a word with the data read from the storage module and the data to be actually written, and eliminates the parity error. When this occurs, the read data from the storage module is input to the error detection/correction circuit, and the corrected data and the data to be actually written form a word.

[Operation] The access procedure for partial writing in this storage device is as follows.

() Reads information from the storage module and performs a parity check (memory read cycle).
If a parity error is detected in this step, the same procedure as in the prior art is followed.

(a) Input the read data to the error detection/correction circuit to detect and correct data errors.

(a) The corrected data and the data to be actually written are combined to form a word, and the word is input again to the error detection/correction circuit.

(a) Create a parity bit using the data passed through the error detection/correction circuit and the error detection/correction bit (generated by the error detection/correction circuit). The data, error detection/correction bits, and parity bits are then written to the storage module.

In normal operation, parity errors are not detected in the above steps. In this case, the above step is omitted, and (b) the data read from the storage module and the data to be actually written are combined into a word structure and input to the error detection/correction circuit.

(b) Create parity bits from the data passed through the error detection/correction circuit and the error detection/correction bits. Data, error detection/correction bits, and parity bits are then written to the storage module (same as step a).

In this way, during normal operation, the data read from the storage module and the data to be actually written are combined into a word structure, eliminating time loss for data checks in the error detection/correction circuit and increasing speed. be able to.

Furthermore, in the event that an abnormality occurs, the error detection/correction circuit operates to detect and correct the error, so that high reliability can be maintained.

[Embodiment] FIG. 1 is a block diagram showing an embodiment of a storage device according to the present invention. A part of the storage module 10, which is an aggregate of a large number of storage elements, is data areas 10a and 10b, and the rest is an area 10c for error detection/correction bits and an area 1 for parity bits.
It becomes 0d. In other words, in the present invention, the storage module 1
0, data bits, error detection/correction bits, and parity bits coexist.

The present invention provides such a storage module 10, a parity bit writing means 12 to the storage module 10, a parity check means 14 for information read from the storage module 10, and a parity bit writing means 12 for the storage module 10.
An error detection/correction circuit (ECC) 16 is provided for writing error detection/correction bits to 0 and detecting/correcting errors in data read from the storage module 10. Furthermore, a first multiplexer 20 selects and outputs write data from the data bus 18 and output data from the error detection/correction circuit 16.
a write data register 22 that holds the output of the first multiplexer 20; a second selector that selects the output of the write data register 22 and the read data from the storage module 10 and supplies it to the error detection/correction circuit 16; multiplexer 24.

In this embodiment, the data and error detection/correction bits from storage module 10 are once latched in read data register 26. Therefore, this read data register 16 also has a data area (upper 26
a, the lower one is 26b) and an error detection/correction code area 26c. The output of this read data register 26 is sent to the second multiplexer 24 (upper 24a, lower 24b), error detection/correction circuit 16, and third multiplexer 2 for reading.
8.

The error detection/correction circuit 16 includes a single error correction/2
A double error detection method is used, and a double error detection signal is sent to an interrupt generation circuit (not shown) to generate an interrupt signal. Third multiplexer 2
The output of 8 is connected to the data bus 18 via the driver 30.
The data supplied to the data bus 18 and conversely sent by the data bus 18 are sent via the receiver 32 to the first multiplexer 20 .

Next, the operation of this storage device will be explained.

When writing all digits (full write), data sent via the data bus 18 is latched into the write data register 22 via the receiver 32 and the first multiplexer 20. Its output is sent through a second multiplexer 24 to an error detection and correction circuit 16. Error detection/
The parity bit writing means 12 is processed by the data from the correction circuit 16 and the error detection/correction bits.
A parity bit is created, and the data, error detection/correction bit, and parity bit are written into a predetermined area of the storage module 10.

When writing the upper digit part, upper digit data sent via the data bus 18 is sent to the upper side 22a of the write data register 22 via the receiver 32 and the first multiplexer 20.
It also reads data from the storage module 10 and latches it into the data register 26. At this time, the read information from the storage module 10 is sent to the parity check means 14 to perform a parity check. The data flow is divided into the following two depending on the result of the parity check.

(-1) No parity error: A signal obtained by inverting the parity error signal by the inverter 34 (a signal indicating no parity error) and a PWTU (higher digit write) signal are sent to the AND circuit 36a. The second multiplexer 24 forms a word using the lower data of the read data register 26b and the upper data of the write data register 22a. The word-structured data is input to the error detection/correction circuit 16.
The subsequent data flow is the same as the data flow for writing all digits described above. The data and error detection/correction bits from the error detection/correction circuit 16 are sent to the parity bit writing means 12 to create parity bits, and the data, error detection/correction bits, and parity bits are written in a predetermined area of the storage module 10. .

(-2) When a parity error occurs: The output of the read data register 26 is sent to the second multiplexer 26, and the error detection/correction bit is sent directly to the error detection/correction circuit 1.
Enter 6. and error detection/correction circuit 1
6. Correct the data. The corrected data is latched into the lower side 22b of the write data register 22 via the first multiplexer 20. The latched data is sent to the error detection/correction circuit 16 via the second multiplexer 24.
Enter it again. The data flow from this point on is the same as the data flow for all-digit writing, and the data and error detection/correction bits from the error detection/correction circuit 16 are sent to the parity bit writing means 12 to generate a parity bit, and the data and error detection/correction bits are sent to the parity bit writing means 12. The bit and parity bit are written to a predetermined area of the storage module 10.

Note that detection of a 2-bit error is performed by inputting the latch data to the error detection/correction circuit 16 during the storage element access prohibition time (see FIG. 2).

When writing the lower digit part It is basically the same as when writing the upper digit part described above. The lower data sent from the data bus 18 is latched into the lower side 22b of the write data register 22. Data from storage module 10 is read from data register 26.
is latched to. At this time, memory module 10
A parity check is performed on the read information, and depending on the result, the data flow is divided into the following two data flows.

(-1) No parity error: A signal obtained by inverting the parity error signal by the inverter 34 and a PWTL (lower digit write) signal are sent to the AND circuit 36b, thereby controlling the upper data of the read data register 26a. and the lower data of the write data register 22b are word-configured by the second multiplexer 24. The word-structured data is input to the error detection/correction circuit 16. The data flow after this is the same as the data flow for writing all digits.

(-2) When a parity error occurs: The output of the read data register 26 is sent to the second multiplexer 26, and the error detection/correction bit is sent directly to the error detection/correction circuit 1.
Enter 6. and error detection/correction circuit 1
6, the data is corrected and the corrected data is latched into the upper side 22a of the write data register 22 via the first multiplexer 20. The latched data is input again to the error detection/correction circuit 16 via the second multiplexer 24. The data flow after this is the same as the data flow for writing all digits.

FIG. 2 is a time chart during writing. Here, the signal *MWTC is a negative logic memory write command signal issued by the processor to the storage device, and the code *XACK is a negative logic response signal that notifies the processor that the storage device has started a write operation. RAS,
*CAS is a negative logic signal that instructs address switching to the storage element, and *WE is a negative logic write signal to the storage element.

Figure A shows a partial write operation when a parity error occurs, and Figure B shows a partial write operation when there is no parity error. As is clear from comparing the two, in the case of Figure B, the *WE signal is generated earlier by time T than in Figure A, and the rises of *RAS, *CAS, and *WE are earlier. This is (ECC
This is because the period (data check by the error detection/correction circuit) is omitted in FIG. In this way, the present invention achieves high speed during normal operation (no parity error).

At the time of reading When reading from the storage module 10, the read data and error detection/correction bits are set in the read data register 26, and at the same time, the read information is sent to the parity check means 1.
Parity is checked at 4. The output of the read data register 26 is sent to a third multiplexer 28
and the error detection/correction circuit 16. If no parity error is detected, the data from the read data register 20 is made valid by the third multiplexer 28 and sent to the data bus 18 via the driver 30. If a parity error is detected, the output from the error detection/correction circuit 16 is sent to the third multiplexer 2.
8, the corrected data is sent to data bus 18 by driver 30. Note that when an error of 2 bits or more occurs, a signal is sent to an interrupt generation circuit (not shown) to generate an interrupt signal and notify the processor.

Although a preferred embodiment of the present invention has been described in detail above, it goes without saying that the present invention is not limited to this configuration. The storage module only needs to have an area capable of storing data, error detection/correction bits, and parity bits, and does not necessarily require a single physical storage module. The error detection/correction method in the error detection/correction circuit is not limited to the single error correction/double error detection method, and any error detection/correction method may be adopted.

[Effects of the Invention] As described above, the present invention stores data, error detection/correction bits, and parity bits in a storage module, is provided with a parity check means and an error detection/correction circuit, and selects and controls data by a multiplexer. Therefore, during partial write operation, error detection and
High-speed operation can be achieved by omitting the correction operation, and also in the event of an abnormality (when a parity error occurs)
However, high reliability can be achieved because subsequent operations are not interrupted and the corrected data that has passed through the error detection/correction circuit is used.

Therefore, the storage device according to the present invention has both high speed and high reliability, and can improve the performance of the system when processing a large amount of information in real time, while also preventing system downtime due to the occurrence of errors. This has the excellent effect of minimizing the

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a storage device according to the present invention, and FIG. 2 is a time chart of a partial write operation thereof. DESCRIPTION OF SYMBOLS 10... Storage module, 12... Parity bit writing means, 14... Parity checking means, 16... Error detection/correction circuit, 18... Data bus, 20... First multiplexer, 22...
...Write data register, 24...Second multiplexer.

Claims (1)

[Claims] 1 A storage module in which data, error detection/correction bits, and parity bits are stored, means for writing parity bits into the storage module, means for parity checking information read from the storage module, and error detection/correction bit writing into the storage module. an error detection and correction circuit that detects and corrects errors in data written and read from the storage module;
The first selector selects and outputs the write data from the data bus and the output data from the error detection/correction circuit.
a multiplexer, a write data register that holds the output of the first multiplexer, and a second multiplexer that selects the output of the write data register and the read data from the storage module and supplies it to an error detection/correction circuit. During partial writing, if there is no parity error in the information read from the storage module, the program switches to the write cycle and configures a word with the data read from the storage module and the data to be actually written, and if a parity error occurs. A storage device characterized in that, at times, data read from a storage module is input to an error detection/correction circuit, and the corrected data and data to be actually written form a word.