JP2001290710A - Device for detecting data error - Google Patents

Abstract

PROBLEM TO BE SOLVED: To secure the reliabilities of a produced program and control data while using a general-purpose computer without a memory check function. SOLUTION: A data processor generating output data from input data, is provided with two memories for storing the same data and a discrepancy detecting means for detecting that a discrepancy exists in data between the two memories.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data error detecting device comprising a processor and a memory.

[0002]

2. Description of the Related Art FIG. 14 is a functional block diagram of a conventional data processing apparatus having no memory check function. In this data processing device, after input data a is input in input processing 11, it is stored in input buffer 12. In the actual main processing 13, a calculation is performed based on the data in the input buffer memory 12, and the data being processed is stored in the internal state memory 16. The processing result of the data is output to the output buffer 14 and output to the outside as output data b by the output processing 15. Here, data is stored in the memory in each step of the data processing, and there is a possibility that such data may lose information due to a defective memory element or a soft error in the memory.

[0003]

As a method of detecting a memory error in a conventional computer device, a parity check, an EC check, and the like have been proposed.
C has been adopted to ensure data reliability. However, in recent years, there has been an increasing demand for handling business-purpose data using a general-purpose personal computer that does not have a memory error detecting means due to the low cost of the apparatus.

For example, in order to ensure reliability, an industrial control device uses a dedicated hardware to perform a parity check and an ECC check for a memory check, but a memory check is performed for a program to be downloaded and control data to be created. There is a case where the operation is performed by a personal computer that is not executed, and the case where the reliability of the created program or control data is directly connected to the reliability of the operation of the industrial control device is considered, and the reliability of the control device is concerned. Was.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and uses a general-purpose computer having no memory check function to prevent data errors that can ensure the reliability of created programs and control data. It is intended to provide a detection device.

[0006]

According to a first aspect of the present invention, there is provided a data error detecting device, comprising: a data processing device for generating output data from input data; two memories for storing the same data; Mismatch detecting means for detecting that there is a data mismatch between the two memories. The operation will be described. The input data is input, the data processing mechanism performs processing, and output data is output as the processing result. At this time, the same contents are stored in both memories as a buffer during processing and input / output data. If the contents of one of the memories are changed due to a data error when the data in the memory is read, the occurrence of the data error is detected by the mismatch detecting mechanism. This mismatch occurrence information is transmitted to the processor, the adoption of the read data is stopped, and the process is performed again.

A data error detecting device according to a second aspect of the present invention is a data processing device for generating output data from input data, comprising two series of data processing mechanisms for performing similar processing, and each of the data processing mechanisms. And a memory for storing an intermediate state, and mismatch detecting means for detecting that there is a mismatch between the result data output from the two-series data processing mechanisms. In operation, input data is passed to two data processing mechanisms. Here, the two data processing mechanisms perform exactly the same data processing in parallel, and the state during the processing is stored in each memory. The result of this processing is output as each result data. In the non-coincidence detection processing, it is checked that the respective result data are exactly the same, and if they match, the result data is output to the outside as output data, and the processing ends. If a mismatch is found in the mismatch detection processing, no output data is output, and in order to obtain correct output data, input data is input again and the data processing is redone.

According to a third aspect of the present invention, there is provided a data processing apparatus for generating output data from input data, wherein at least three or more memories storing the same data; And a mismatch detecting and correcting means for detecting that there is a data mismatch between the memories. Next, the operation will be described. There are three sets of memories that hold the same data, and the same data is written to the three memories. The data read from the memory is input to the data error detection / correction means, which detects whether or not the contents of the memory are damaged, and obtains correct data. When an error that cannot be corrected by the data error detection and correction means is found, the error is notified to the data processing mechanism as inconsistency information, and the data must be processed again from the beginning.

A data error detecting device according to claim 4 of the present invention is a device for detecting a data error in a memory, wherein the first processing means generates data in which the bit position is replaced with the original data, Second processing means for generating inverted data for each bit of the original data, and logically divided memories for storing the original data, the data in which the bit positions are exchanged, and the inverted data for each bit And third processing means for detecting a data line whose value read from the memory is fixed to 1 or 0, and restoring the data in which the bit positions are interchanged and the inverted data for each bit, respectively, to restore the data. A fourth processing unit that generates the data; and a mismatch detection processing unit that detects that there is a content mismatch between the restored data. Next, the operation will be described. In this configuration, data rotated one bit to the right and data obtained by inverting all bits are held as data. Therefore, all the bits of the three held data are not set to 1 or 0. Therefore, when there is a bit in which all 0s or all 1s are included in the read data, it is understood that the bit may have a data line error. If no data line error has occurred, the data error in the memory can be repaired by returning the rotated data and the inverted data and checking the data. When a data line error has occurred, the data lost as a result of the data line error in one memory is shifted by one bit in the other memory, so that the data lives as another bit. The original data can be restored using this information.

According to a fifth aspect of the present invention, there is provided a data error detecting device for detecting a data error in a memory, wherein the same data is stored at different addresses via an access control circuit. Means for performing a collation check upon reading the stored data. Next, the operation will be described. In a data write operation, the access control circuit performs the same data write operation twice on two different addresses of the memory. In the data read operation, the access control circuit performs the read operation twice for the two memory addresses that have been written. At this time, the data read in the first access is latched in the data latch, and is compared with the data read in the second access to check. Since the same data should be written in the two data, if they match, it is determined that no data error has occurred in the read data, and the data read in the second access is determined. Adopt and perform data processing. If the two data read are different, 1
Since it is considered that there is a data error in either the second or the second read data, an error signal is used to notify the processor of a data error. When the processor detects a data abnormality, it performs the data processing again from the beginning.

[0011] A data error detection device according to claim 6 of the present invention is a data error detection device for performing an error check on data transmission between devices, means for transmitting one address information and data information a plurality of times, Error detecting means for both the address information and the data information is provided. Next, the operation will be described. When data is written from the control device to the input / output device, an address signal and a data signal are sent from the control device to the input / output device. At this time, the same data is transmitted twice at the same address in order to check whether an error has occurred in the address and data information. The input / output device receiving these information checks whether there is a mismatch between the first and second addresses. It is checked whether there is any mismatch between the first and second writing data. If both the address and the data are normal, the input / output circuit outputs the data. When data is read from the input / output device to the control device, an address signal is sent from the control device to the input / output device, and a data signal is sent from the input / output device to the control device. At this time, the same data is read twice at the same address in order to check whether an error has occurred in the address and data information. The I / O device checks whether there is a mismatch between the first and second addresses as in the case of writing. The controller checks whether there is any mismatch between the first and second read data. If both address and data are normal,
Use the read data.

A data error detecting device according to claim 7 of the present invention is a data error detecting device for performing an error check on data transmission between devices, means for transmitting one address information and data information a plurality of times, In addition to providing error detection means for both the address information and the data information, the polarity of the address information and the data information transmitted multiple times is inverted with the original information that does not change bits and the information whose bit position has been changed. Three pieces of information including the information made to be used were used. Next, the operation will be described. As data, three types of data are transmitted: original data, data in which the upper and lower parts of the data are replaced, and data in which all bits are inverted. For this reason, all three bits of the data do not become 1 or 0. If there is a bit in the read data that is all 0s or 1s, there is a possibility that the bit is a data line error. If a data line error has not occurred, the rotated data and the inverted data are returned to the original state, and the data error can be repaired by checking the data. Further, even when all the upper or lower data have a data line error, the information lost due to the data line error remains in the second data. The original data can be restored using this information.

[0013]

FIG. 1 is a functional block diagram showing a first embodiment of a data error detecting device according to the present invention. In FIG. 1, the same reference numerals are given to the same functional portions as in FIG. 14, and the description will be omitted. In the present embodiment, the reliability of programs and control data created using a general-purpose computer having no memory function is ensured.

The features of this embodiment are as follows.
The input part is composed of an input processing 11, an input buffer memory 12, an input buffer memory 12-1, and a mismatch detection processing 17, and the intermediate part is a main processing 13 and a temporary storage for temporarily storing the data-processed internal state. It comprises an internal state memory 16, an internal state memory 16-1 and a mismatch detection process 18, and the output portion comprises an output buffer memory 14 and an output buffer memory 14-1, and a mismatch detection process 19 and an output process 15.

Next, the operation will be described. Input data a
Are stored in the input buffer memory 12 and the input buffer memory 12-1 by the input processing 11. In order to perform data processing, when reading the contents of each of the input buffer memories 12 and 12-1, data is read from each of them, and whether or not there is a mismatch is checked by a mismatch detection process 17. If there is no mismatch, the read data is regarded as correct and data processing is performed.

Next, in the main processing, the internal state is stored in the internal state memory 16 and the internal state memory 16-1 in order to store the intermediate state of the data processing. When referencing this internal state again, a check is made by the mismatch detection processing 18 for a mismatch between the internal state memory 16 and the internal state memory 16-1, and if there is no mismatch, data processing is performed.

The result of the main processing 13 is output to the output buffer memory 14 and the output buffer memory 14-1.
Lastly, when outputting the result of the data processing to the outside, the data is read from the output buffer memory 14 and the output buffer memory 14-1, and a check is made by the mismatch detection processing 19; b is output to the outside. If a mismatch is detected in the above mismatch detection, the data is discarded and the process is executed again from the point where the data is input.

FIG. 2 is a conceptual diagram showing an example in which the present data error detection function is applied to a data processing device. In this example, only the error detection unit of the main processing is clearly indicated by a dashed line with respect to the data processing mechanism 100. According to the present embodiment, it is possible to detect a data error by the above-described processing even if the memory itself does not have a data error detection mechanism,
The reliability of output data can be ensured.

FIG. 3 is a functional block diagram showing a second embodiment of the data error detecting device according to the present invention.
3, the same functional portions as those in FIG. 14 are denoted by the same reference numerals, and description thereof will be omitted. In the present embodiment, while using a general-purpose computer without a memory check function, another method for ensuring the reliability of a created program or control data is to simplify the processing of the program. .

Therefore, in this embodiment, each processing is divided into two series. That is, the input buffer memory 12,
The processing consisting of the main processing 13 and the output buffer memory 14 is performed in parallel, and the output of the output buffer memory of each series is connected to the mismatch detection processing 19 to detect an error.

Next, the operation will be described. Input data a
Is written to the input buffer 12 and the input buffer 12-1 by the input processing 11. Main processing 13 and 13-1
Performs data processing based on the data in the input buffers 12 and 12-1, respectively, writes the intermediate results in the internal state memories 16 and 16-1, and stores the final processing results in the output buffer 1.
Write to 4 and 14-1. When the processing results are complete, the mismatch detection processing 19 confirms that there is no mismatch between the output buffer 14 and the output buffer 14-1, and the output processing outputs the result data as output data.

FIG. 4 is a conceptual diagram showing an example in which the data error detection function is applied to a data processing device. In this example, the data processing mechanisms 100 and 100-1 independently perform two-series main processing, and the main processing is provided with independent internal state memories 16 and 16-1, respectively. is there.

According to the present embodiment, the data processing mechanism 1
In the process of writing and reading data to and from the internal state memory in the data processing mechanism 100-1 and the data processing mechanism 100-1, it is not necessary to write the same data one by one or to check for mismatch of read data. In addition, since input data need only be written to two buffers and only the inconsistency of data resulting from processing needs to be checked, the processing program can be simplified while having the function of checking data errors.

FIG. 5 is a functional block diagram showing a data error detecting and correcting means of a data error detecting device according to a third embodiment of the present invention. In this embodiment, as a memory check method, erroneous data is restored to obtain correct data. In FIG. 5A, three internal state memories (16, 16-1, 16-2) are provided, and a data error detection / correction means 20 is provided. The data error detection and correction means includes a mismatch detection process 20-1 and a data selection process 20-2.
FIG. 5B shows a configuration of read data of each memory.

Next, the operation will be described. At the time of writing, the same data is written in each of the memories 16, 16-1 and 16-2. Thereafter, at the time of data reading, data is called from each of the memories 16, 16-1, and 16-2 and is input to the mismatch detection processing 20-1. In the data mismatch processing, a combination of memories having matching data is checked. This determines which data is to be adopted in the data selection processing 20-2.

An example of the read data is shown in FIG.
As shown in (b), in this case, it is assumed that there is an error in the data of the memory 16-1 (the filled part is an error, that is, a part different from other data). For example, when only the data in the memory 16-1 is different from the others in the read data as in the example of FIG. 5B, if the data in the memory 16 and the data in the memory 16-2 match, Is read, and this is adopted as data d and functions to return to the data processing mechanism.

The detection of a memory mismatch and the use of data are determined by the following logic.

[Table 1]

In this embodiment, the memory 16 and the memory 16
Since the read data of -2 match, the data of the memory 16-2 is adopted as the data. However, if all the data do not match, the data processing mechanism 1 is notified as the mismatch information e and the data processing is restarted from the beginning.

FIG. 6 is a conceptual diagram showing an example in which the data error detection function is applied to a data processing device. In this example, three internal state memories 1 are provided for the data processing mechanism 100, respectively.
6, 16-1 and 16-2 are provided, these outputs are connected to the data error detection and correction means 20, and the correction results are returned to the data processing mechanism.

Here, instead of the method of having three memories, the ECC code is stored in another memory area at the time of data writing, and both memories are read at the time of data reading to check and correct data by ECC. A method is also conceivable. Also, in the present embodiment, three memories are used.
Although the case of having a plurality has been described, the present invention is not limited to this, and three or more may be provided. In this case, the logic for detecting the mismatch of the memory and adopting the data may be renewed. According to the present embodiment, even when an error occurs in one piece of data, correct data can be obtained, so that data processing can be continued.

FIG. 7 is a block diagram showing a data error detection and correction means of a data error detection device according to a fourth embodiment of the present invention. In this embodiment, normal data is obtained by avoiding a one-bit failure of data. The configuration of the data error detection and correction processing will be described with reference to FIG. Memory for storing write data is 16,1
6-1 and 16-2. At the time of data writing, a right rotation process 21 and an inversion process 22 for changing the bit position of the data are used.

When data is read, data in which a data line error has been corrected is generated by a data line error detection circuit 20-3 and a bit selection circuit 20-4. or,
The data read from the memory 16-1 is input to the left rotation processing 20-5, and the data read from the memory 16-2 is input to the inversion processing 20-6 and returned to the original data. These data and the data read from the memory 16 generate correct read data d from the mismatch detection processing 20-1 and the data selection processing 20-2 as in FIG.

Next, the operation will be described. At the time of data writing, the following processing is performed. 1) The write data c is stored in the memory 16 as it is. 2) The write data c is put into the right rotation process 21 and the rotated data is written into the memory 16-2. 3) The write data c is input to the inversion processing 22 and the data obtained by inverting all the bits is written to the memory 16-2. For example, when the write data c is “10110011”,
As shown in FIG. 7B, the memory 16, the memory 16-1,
Data is written to each of the memories 16-2.

At the time of data reading, the following processing is performed. 1) The following check is performed in the data line error detection processing 20-3. An AN for each bit of the memories 16, 16-1, 16-2
Take D. If the result is all 0, the data line is normal. OR for each bit of memories 16, 16-1, 16-2
Take. If the result is all 1, the data line is normal. A data line error has occurred in a bit that has become 1 or a bit that has become 0. If a data line error of 2 bits or more has occurred, the data cannot be corrected.

2) The following processing is performed in the bit selection processing 20-4. In the case of a 1-bit data line error, the data of the bit where no data line error has occurred is created with the data read from the memory 16, and the data of the bit where the data line error has occurred is read from the memory 16-2. The data is complemented by data generated by the left rotation processing 20-5.

3) The data in the memory 16-1 is subjected to a left rotation process 20-5, and the data in the memory 16-2 is subjected to an inversion process 20-6 to generate original data. 4) Using the data of the memory 16-1 in addition to the data generated in 3), correct read data d is generated by the mismatch detection processing 20-1 and the data selection processing 20-2 as in FIG. 5) If there is an uncorrectable error, the data processing mechanism is notified by the mismatch information e.

According to the present embodiment, even when a 1-bit data line error occurs, data can be restored to normal data, and data reliability and availability can be improved.

FIG. 8 is a functional block diagram showing a data error detecting apparatus according to a fifth embodiment of the present invention.
In the present embodiment, the memory check method is executed by hardware at the time of memory access, and the cost is reduced by reducing the number of memories used and the reliability is improved by reducing the number of components.

In FIG. 8, 81 is a processor, 82 is a memory, 83 is an access control circuit, 84 is a data latch circuit, 85 is a comparator, and the memory 82 is 8 bits × 1.
Assuming that you are using 28 kbytes of memory,
Eight data lines D0-7, address line ADR
Assume that there are 17 S. Since two pieces of data having the same contents are written in the memory 82, the number of address lines as viewed from the processor side is 16 (64 kbytes).

Next, the operation will be described with reference to the time chart of FIG. The processor 81 first issues a request to write the data 55h to the address 0010h.
The access control circuit 83 determines that the memory 82 has 00010h and 1
The same data 55h is written twice to two different addresses of 0010h.

Next, the processor 81 issues a request to read data from the address 0010h. The access control circuit 83 first reads data from 00010h, and the read data is latched by the data latch 84 at this time. In FIG. 9, the data 55h is read out and latched.

The access control circuit 83 reads data from 10010h in the second access and returns the data to the processor 81. In FIG. 9, data 54h is read. At the same time as returning the data to the processor 81, the comparator 85 compares the data read first and the data read second.

If the data match, it can be determined that no data error has occurred in the read data, but if different data is read as shown in FIG. 9, it is considered that a data error has occurred ( In FIG. 9, 54h is read even though 55h is written). In this case, E
The data error is notified to the processor 81 using the RR signal. When the processor detects an abnormality in the read data, the data processing using the read data is interrupted, and the data processing is performed again from the beginning.

According to the present embodiment, it is not necessary to increase the number of memory elements for storing check codes such as parity bits and ECC codes in addition to the memory for storing data. Thus, reliability can be improved by reducing the number of parts.

FIG. 10 is a functional block diagram showing a sixth embodiment of the data error detecting device according to the present invention. In the present embodiment, the memory check method is applied to data transmission between devices to ensure the reliability of data transmission. In FIG. 10, reference numeral 110 denotes a control device, which comprises a processor 111, an address generation circuit 112, a data control circuit 113, and a comparison circuit 114. Also, 12
0 is an input / output device, which is an input / output circuit 121, a comparison circuit 122,
123 and a data generation circuit 124.

The processor 111 and the input / output circuit 12
1 is directly connected by an access control signal c, and is also connected by an address signal a between an address generation circuit 112 on the control device side and a comparison circuit 122 on the input / output device side. Data generation circuits 1 provided respectively
13 and 123 and the comparison circuits 114 and 124 are also connected by the data signal b.

In this case, 15 bits are used as an input / output address, and the upper 1 bit is used for discriminating the first access or the second access. When the most significant bit is 0, it indicates the first access, and when the most significant bit is 1, it indicates the second access. The data bus has 8 bits, and the data for reading and writing uses a common data line. A write signal WR and a read signal RD are used as control signals.

Next, the operation will be described with reference to the time chart of FIG. First, in the waveform on the input / output device side at the time of normal,
First, data 55h is written to the address 0023h. Subsequently, 1 is set in the most significant bit to write the same address in the second access, and 802 is set.
55h is written in 3h. Next, data AAh is read from the address 0034h. Then 2
In order to perform reading from the same address in the second access, 1 is set to the most significant bit, and AAh is read from 8034h.

In the first half of the waveform on the input / output device side when a data error occurs, 55h is written in 0023h in the first time, and 54h is written in 8023h when writing to the same address in the second access. . 1
Since the comparison circuit 123 knows that the second data is different from the second data, the data in which the data error has occurred is not output to the outside.

In the second half of the waveform, data AAh is read from 0034h at the first time, but data is read from 8035h at the second access, and correct data cannot be read. The occurrence of an error in the address is detected by the comparison circuit 25, and the read data is not used.

According to the present embodiment, since the address and data are checked, there is no danger of inputting / outputting erroneous data or address due to a transient data error or the like. Reliability is improved.

FIG. 12 is a block diagram showing a seventh embodiment of the data error detecting device according to the present invention. In the present embodiment, normal data is obtained by detecting a stuck-at fault in a byte unit for one bit. In FIG. 12, reference numeral 30 denotes a data generation circuit, which is an upper / lower inversion process 31;
It comprises a bit inversion process 32. A data restoring circuit 200 corresponds to the data error detecting and correcting means 20 shown by a dashed line in FIG. Therefore, the reference numerals shown here are the same as those shown in the above-mentioned figures. It should be noted that what is newly provided in the present embodiment is an upper / lower selection process 20-7 and an upper / lower replacement process 20-8.

Here, the data restoration circuit will be described again. In the data restoration circuit, the data line error detection processing 20-3 is applied to the first to third data. If there is a data line error, the upper / lower selection process 20-7 restores the original data d according to the position where the data line error occurred.

The data restoration circuit restores the original data by applying the upper / lower substitution processing 20-8 and the bit inversion processing 20-6 to the second and third data. This and 1
The occurrence of a 1-bit data error is checked by the mismatch detection processing 20-1 using the second data, and correct restored data d is generated by the data selection processing 20-2.

Next, the operation will be described. At the time of data generation, the following processing is performed. 1) Output the original data c as it is as the first data. 2) The original data c is put into the upper / lower replacement processing 31 and the upper 4
The data in which the lower 4 bits are replaced with the bits are output as the second data. 3) The original data c is put into the bit inversion processing 32, and the data obtained by inverting all the bits are output as the third data. These generated data are shown in FIG.

At the time of data restoration, the following processing is performed. 1) AND for each bit for the first to third data
Take. If the result is all 0, the data line is normal. 2) OR the first to third data for each bit. If the result is all 1, the data line is normal. 3) A data line error has occurred in the bit that became 1 in 1) or the bit that became 0 in 2). If a data line error has occurred across the upper 4 bits and the lower 4 bits, the data cannot be corrected.

4) When only the upper or lower 4 bits have a data line error, the 4-bit data in which no data line error has occurred is created from the first data, and the 4-bit data in which the data line error has occurred is generated. Is complemented by the second data. 5) The second data is subjected to the upper / lower replacement processing 20-8, and the third data is subjected to the bit inversion processing 20-6 to generate the original data. 6) Using the first data in addition to the data generated in 5), correct read data d is generated by the mismatch detection processing 20-1 and the data selection processing 20-2 as in FIG. 7) If there is an error that cannot be corrected, the data processing mechanism is notified by the mismatch information e.

According to the present embodiment, it is possible to provide a means for detecting a stuck-at fault in units of 1 bit or byte of data and obtaining normal data.

[0059]

As described above, according to the present invention, while using a general-purpose computer having no memory check function,
The reliability of created programs and control data can be ensured.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing a first embodiment of a data error detection device of the present invention.

FIG. 2 is a configuration diagram of a data processing device to which the data error detection function of FIG. 1 is applied.

FIG. 3 is a configuration diagram illustrating a data error detection device according to a second embodiment of the present invention.

FIG. 4 is a configuration diagram of a data processing device to which the data error detection unit of FIG. 3 is applied.

FIG. 5 is a configuration diagram showing a data error detection / correction unit of a data error detection device according to a third embodiment of the present invention.

FIG. 6 is a configuration diagram of a data processing apparatus to which the data error detection and correction unit of FIG. 5 is applied.

FIGS. 7A and 7B are a configuration diagram and an operation explanatory diagram showing a data error detection and correction unit of a fourth embodiment of the data error detection device of the present invention.

FIG. 8 is a configuration diagram showing a fifth embodiment of the data error detection device of the present invention.

FIG. 9 is an operation time chart of the data error detection device of FIG. 8;

FIG. 10 is a configuration diagram showing a sixth embodiment in which a data error detection device is applied to transmission between devices.

FIG. 11 is a transmission time chart between devices.

FIG. 12 is a configuration diagram showing a data error detection device according to a seventh embodiment of the data generation circuit and the data restoration circuit according to the seventh embodiment;

FIG. 13 is an example of the generated data of FIG. 12;

FIG. 14 is a configuration diagram of a conventional data processing device.

[Explanation of symbols]

 Reference Signs List 11 input processing 12 input buffer memory 13 main processing 14 output buffer memory 15 output processing 16 internal state memory 17, 18, 19 mismatch detection processing 20 mismatch detection processing correction means 100 data processing mechanism 81, 111 processor 82 memory 83 access control circuit 84 Data latch 85 Comparator 110 Control device 112 Address generation circuit 113, 124 Data generation circuit 114, 122, 123 Comparison circuit 120 Input / output device 121 Input / output circuit 30 Data generation circuit 200 Data restoration circuit 20-1 Mismatch detection processing 20-2 Data selection processing 20-3 Data line error detection processing 20-4 Bit selection processing 20-5 Left rotation processing 20-6 Inversion processing 20-7 Upper / lower selection processing 20-8 Upper / lower replacement processing

Claims (7)

[Claims] 1. A data processing device for generating output data from input data, comprising: two memories for storing the same data; and mismatch detecting means for detecting that there is a data mismatch between the two memories. A data error detection device. 2. A data processing apparatus for generating output data from input data, comprising: a two-series data processing mechanism for performing similar processing; a memory for storing an intermediate state in each of the data processing mechanisms; A data error detection device comprising: a mismatch detection unit configured to detect a mismatch between result data output by the data processing mechanism. 3. A data processing apparatus for generating output data from input data, wherein at least three or more memories for storing the same data and a mismatch for detecting that there is a data mismatch between the three or more memories. A data error detection device comprising: a detection and correction unit. 4. An apparatus for detecting a data error in a memory, comprising: first processing means for generating data in which the positions of bits of the original data are interchanged with each other; and second processing means for generating inverted data for each bit of the original data. (2) logically divided memories for storing the original data, the data in which the bit positions are exchanged, and the inverted data for each bit, and the value read from the memory is fixed to 1 or 0 A third processing means for detecting a data line which is performing the data processing, a fourth processing means for generating data by restoring the data in which the bit positions are exchanged and the inverted data for each bit, respectively, A data error detection device comprising: a mismatch detection processing means for detecting that there is a content mismatch. 5. A data error detecting device for detecting a data error in a memory, comprising: means for storing the same data at different addresses via an access control circuit; and means for performing a collation check when reading the stored data. A data error detection device. 6. A data error detecting device for performing an error check on data transmission between devices, means for transmitting one address information and data information a plurality of times, and error detecting means for both the address information and the data information. A data error detection device comprising: 7. A data error detecting device for performing an error check on data transmission between devices, means for transmitting one address information and data information a plurality of times, and error detecting means for both the address information and the data information. And three pieces of information including original information that does not change bits, information in which the bit position of information is changed, and information in which the polarity is inverted are used as the address information and data information to be transmitted a plurality of times. A data error detection device characterized by the above-mentioned.