JPH01231151A - Address distributing system in storage device - Google Patents

Abstract

PURPOSE:To allow an address fault to remain within a correctable error range even if the address fault is generated by storing the data in the same error correcting code unit to different memory modules by distributing the addresses. CONSTITUTION:At the time of storing the same error correcting code unit consisting of 80 bits in a RAM, it is divided into 4 bits each, and for instance, stored in memory elements of addresses 250-259. In this regard, a memory module 2' is connected to distributing gates 47, 48, as well in the same way as 45 and 46. As for said addresses 250-259, since they are distributed to each separate memory module, for instance, even if a fault is generated in a distributing gate 54', an error in said single error correcting code unit goes to only 4 bits stored in the address 254 among 80 bits, and remains within a correctable error range by a single byte error correcting.double byte error detecting code.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention is an error correcting code.
This storage device is related to an address distribution method applied to a storage device that detects and corrects faulty data using onCode; This paper relates to an address distribution method.

[Conventional technology]

Error correction code
As a storage device that detects and corrects faulty data using ECC (ECC), a configuration shown in FIG. 3, for example, has been proposed. As shown in FIG.
, an address decoder 4 which provides an address input to the address input end of the memory array 2, and an ECC generated from the write data given to the data input/output end of the memory array 2 and supplies it to the data input/output end of the memory array 2. An ECC generation circuit 6, a test bit generation circuit 8 that generates test bits from stored data read from the data input/output terminals of the memory array 2, and a test bit analysis circuit 10 that analyzes data from the test bit generation circuit 8. and,
It is comprised of an error correction circuit 12 that performs error correction based on the analysis result from the check bit analysis circuit 10 and the stored data from the memory array 2. ECC generation circuit 6;
A test bit generation circuit 8, a test bit analysis circuit 10,
The error correction circuit 12 constitutes an error correction means.

Regarding error detection and error correction methods using ECC, please refer to the magazine "Electronic Science J, August 1979 issue, page 29~
Since the method is described in detail in "Hidehiko Kobayashi, page 35," the method will only be briefly explained using the explanatory diagram of FIG. 4.

Write operation> The address input from the central processing unit, etc. is sent to the address decoder 4.
For example, when 4-bit write data D0 to D3 is applied to the data output terminal of the memory array 2 as shown in FIG. 4(1), the ECC generation circuit 6 outputs write data D. -D3 to Figure 4 (2)
By performing the logical calculation of equation (1) below,
3-bit ECC (C,), C as shown in Figure 4 (3)
, , C2).

However, ■ represents exclusive OR.

Then, the address of the memory array 2 is designated by the address decoder 4, and after the designation, a control signal is applied to the control signal input terminal, thereby writing data D shown in FIG. 4 (4). ~D, and E CC(Co,
C1, Ca) are written to the memory array 2 as storage data DT.

Readout operation> On the other hand, the data read out from the memory array 2 (5) in FIG.
The stored data DT in (8) is transmitted to the check bit generation circuit 8,
and the error correction circuit 12.

The test bit generation circuit 8 generates a test bit S from the stored data DT using the following equation (2) in (6) and (9) in FIG. , S, , S2 is generated.

This check bit is provided to a check bit analysis circuit 10. This check bit analysis circuit 10 has the following table,
Based on this, the check bit So, $1.32 is analyzed in FIG. 4 (7) and (10).

(Margins below) Table 1 This check bit analysis circuit 10 provides the results to the error correction circuit 12. This error correction circuit 12 outputs the stored data DT as data RD when there is no error, but when there is an error, the stored data DT and the analysis result from the error correction circuit 12 are output as shown in FIG. 4 (11). Errors are corrected and data RD' is output.

Here, the stored data DT (Do, Do, D2
.

It will be explained that error detection and correction can be performed when Ds) is, for example, logical 1, 0.0.1.

First, from the data WD, in Fig. 4 (2),
When the FCC is generated using the formula, the ECC becomes 001. Next, in (5) and (6) of FIG. 4, if a check bit is generated from equation (2), then in this case, the check bit is
So, S, , S2 are all 0, and correct data RD is obtained.

On the other hand, in FIG. 4 (8) and (9), if a check bit is generated from equation (2), in this case the check bit So
, Sl* s2 becomes 101, and from Table 1, data D
It is possible to detect that there is an error in I. Therefore, correct data RD' can be obtained from this.

The storage device operates as described above.

Incidentally, the address distribution system of such a storage device is realized by an address decoder 4, the details of which are shown in FIG. 5, for example.

The address distribution system shown in FIG.
RAM elements 200 to 209 .
210-219.220-229.230-239.2
40~249°250~259.260~269.27
0 to 279.280 to 2.89.290 to 299, etc., and distribution gates 45 to 48.50 to 59, respectively.

Further, the unit memory of the memory array 2 is composed of ten memory modules. RAM element 200-2
09 is the first memory module, RAM element 210~
219 is the second memory module, RAM element 220
229 is the third memory module, and similarly, RAM elements 290 to 299 are the tenth memory module. The distribution gate 50 connects the RAM elements 200 to 20
9, the distribution gate 51 connects the RAM elements 210 to 219 to
Distribution gate 52 connects RAM elements 220 to 229, and similarly, distribution gate 59 connects RAM elements 290 to 299.
Addresses are distributed to each. Distribution gate 50
Addresses are distributed from the distribution gates 46 to 54 and from the distribution gate 45 to the distribution gates 55 to 59, respectively. Also, distribution gate 45.46.50~5
For example, if the address is 1 bit, each of 9 is composed of 16 bits.

The distribution gates 47 to 48 also have the same configuration as described above.

The operation of such a configuration will be explained.

First, let us consider an 8-byte unit as an FCC for detecting and correcting data, and for example, it is made up of an 80-bit ECC. The RAM element forming f11 of each memory module consists of 40 bits, and the breakdown is that each RAM element is a set of 10 RAM elements each having a 4-bit structure.

Therefore, if an ECC consisting of 80 bits is distributed to a memory module consisting of 10 RAM elements (4)
It will distribute 40 bits through 5.46 and 40 bits through 47.48 to other memory modules. In other words, 80-bit ECC
In the end, 20 memory elements are required to store the data.

Here, for example, what happens to the write data when one gate in the distribution gate 54 fails will be described below.

If one of the distribution gates 54 that distributes addresses to the RAM elements 240 to 249 fails, the RAM element 24
One bit of the address that distributes addresses from 0 to 249 becomes incorrect, and data is written to the incorrect address. Then, the 40-bit ECC distributed by the distribution gates 45 and 46 becomes incorrect.

On the other hand, the 40-bit ECC distributed via the distribution game 47.48 is correct because the correct address is distributed. Therefore, 80
The bit ECC ends up consisting of 40 incorrect bits and 40 correct bits, and even if error detection and correction is performed based on this, the written data will be written to the memory module as an uncorrectable error. It ends up. Such erroneous stored data DT is detected as an uncorrectable error when read from the memory module. In some cases, the data may become garbled without being detected as an uncorrectable error.

[Problem to be solved by the invention]

The conventional address distribution system described above has the disadvantage that if even one of the address distribution gates fails, an uncorrectable error or garbled data will result, significantly reducing the reliability of the storage device.

Furthermore, a memory module in which an uncorrectable error has been detected needs to be disconnected from the system, but there is a drawback in that a failure of only the l gate requires disconnecting the memory module, which is a large memory area.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide an address distribution method in a storage device that makes it possible to stay within a correctable error range even in the event of an address failure.

[Means to solve the problem]

In order to achieve the above object, the address distribution method in the storage device of the present invention includes a memory array that stores write data according to a given address input, generates an ECC from the write data given to this memory array, and generates an ECC from the write data given to this memory array. and data are written to the above-mentioned memory array as stored data, and check bits are generated from the stored data read from the above-mentioned memory array, and error correction is performed based on the analysis result of the check bits and the stored data from the above-described memory array. In an address distribution system that distributes an address to a memory module made up of a plurality of R/'M elements constituting the above-mentioned memory array via an address distribution gate, From each address distribution gate described above, the same -
The present invention is characterized in that, when data constituting an ECC unit is stored, an address is distributed only to one of the basic unit RAM elements of the memory module.

According to the present invention, even if an address failure occurs, the same ECC
Since the address of the data constituting the unit is only distributed from each address distribution gate to one RAM element among the plurality of RAM elements constituting the memory module, it is assumed that the address is distributed to the memory module. Even if there is a failure in the gate, only the data for that RAM element will be incorrect, and the data in other memory modules will be normal, making it possible to keep the error within the correctable error range.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of an address distribution system in a storage device of the present invention.

The embodiment of the address distribution system in the storage device shown in FIG. 1 differs from the structure shown in FIG. 5 in the structure of the distribution gates 50' to 59' and the memory module.
When storing data constituting the same unit ECC, one of the basic unit RAM elements constituting the same memory module
The point is that addresses are distributed only to That is, from the distribution gate 50', the RAM elements 200, 210
．． 220. ..., 290, and the RAM elements 201, 211, 221 . . . from the distribution gate 51'. ..., 291, RAM elements 202, 212,
232. ..., 292, and similarly below, the distribution gate 5
From 9' are RAM elements 209, 219, 229. ...
, 299, addresses are distributed to each of them. this is,
For example, for 10 memory modules, 40 bits of the data constituting the 80-pit FCC are transferred from the distribution gate 50' to 4 bits of the RAM element 240.
Distribution gate 51' supplies 4 bits of RAM element 241, distribution gate 52' supplies 4 bits of RAM element 242, and so on, distribution gate 59' supplies 4 bits of RAM element 249, and so on. , addresses are distributed to the basic unit RAM elements of each module. By doing so, it is possible to configure a storage device with fewer errors.

Next, as described in FIG.
Let us now discuss the case where the gate fails.

RAM elements 204.214, 224, 234°244.
If one gate in the distribution gate 54 that distributes addresses to RAM elements 254, 264, 274, 284, 294 fails, RAM elements 204, 214, 224, 234, 244
,254,264°274.284.294
Data is written to an address in which 1 bit of the address distributed to 4 bits of each data in CC unit is incorrect. The data that makes up the 80-bit ECC is
As shown in Figure 2, the incorrect 4 Biff) AD and the correct 7
It will be composed of 6 bit BD. Therefore, if one of the distribution gates 54 were to fail, 40 bits would be erroneous data in the prior art;
According to this embodiment, only 4 bits become error data.

In this example, the RAM element has a 4-pit configuration, so E
If a single byte error correction/double byte error detection code (S4 EC-D, ED) is adopted as the CC, the above 4-bit error becomes a correctable error. This is true for distribution gates 50-59 in general; failure of an address distribution gate results in a correctable error.

According to this embodiment, when an address is distributed from a distribution gate to a plurality of RAM elements, each distribution gate distributes the address only to one of the RAM elements constituting the same ECC unit. As a result, even if an address distribution gate fails, an uncorrectable error does not occur, and a highly reliable storage device that can prevent an error from becoming a correctable error can be achieved.

〔Effect of the invention〕

As explained above, in the present invention, when an address is distributed from a distribution gate to a plurality of memory elements, each distribution gate distributes the address only to one of the unit memory elements constituting the same ECC unit. By doing so, even if the address distribution gate fails, it can be stopped as a correctable error, and a highly reliable storage device can be provided.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is an explanatory diagram for explaining the embodiment, FIG. 3 is a block diagram showing the configuration of a storage device using FCC, and FIG. 4 is a block diagram showing an embodiment of the present invention. Third
Explanatory diagram shown for explaining the operation of the storage device shown in FIG.
The figure is a block diagram showing a conventional example. 40...address register, 45-48.50'-59'...distribution gate,
200-299...RAM element (basic unit memory element).

Claims (1)

[Claims] a memory array for storing write data according to a given address input; generating an error correction code from the write data given to the memory array; writing the error correction code and data as storage data in the memory array; A storage device comprising an error correction means for generating check bits from stored data read from a memory array and performing error correction based on an analysis result of the check bits and stored data from the memory array, the storage device comprising: In an address distribution method in which addresses are distributed to memory modules consisting of a plurality of basic unit memory elements constituting a plurality of basic unit memory elements through address distribution gates, data constituting the same error correction code unit is stored from each address distribution gate. An address distribution method in a storage device, characterized in that an address is distributed only to one of the basic unit memory elements of the memory module.