JPH09252253A - Digital modulation method and demodulation method and digital modulation circuit and demodulation circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the system of m-n modulation so that a DC level of a recording signal subject to m-n modulation and further NRZI modulation is not largely changed. SOLUTION: To a head of input data, m-bit dummy data are multiplexed, an error check code is added and j-kinds of elements α<i> of Galois field are multiplied. Block data multiplied with the j-kinds of elements α<1> of Galois field are stored in a 1-block memory 74a and each |DSD| is compared mutually and block data whose absolute value is minimized are selected. The information denoting the selection result is fed to a selector 76, block data corresponding to the selection result are read from the 1-block memory 74a and subject to RLL modulation. Then NRZI modulation is applied to the resulting data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention modulates an m-bit digital signal into an n-bit bit string to generate an NRZI signal.
(Non Return to Zero Inversion) Digital modulation method and circuit for modulation, and NR for n-bit modulation data
The present invention relates to a digital demodulation method and circuit for ZI demodulation to demodulate an original m-bit digital signal.

[0002]

2. Description of the Related Art As a method of storing and reproducing binary data at a high density on a recording medium, there is a method of RLL modulation and NRZI modulation. In this method, the number of 0s existing between 1 and 1 is limited to d or more and k or less, the signal of bit 1 is inverted, and 0 is not inverted. In this system, the following conditions are required.

(1) Large detection window width (Tw) A value proportional to m / n. This value is the time that can be used for detecting the reproduction bit, and shows the permissible capacity for the phase fluctuation of the reproduction pulse due to the waveform interference or noise accompanying the higher density. Therefore, the larger Tw is, the better. (2) The minimum polarity reversal interval (Tmin) is large. Tmin is obtained by the product of "d + 1" and Tw. When this value becomes small, the waveform interference between the reproduction pulses becomes large and the detection error at the time of demodulation increases. Therefore, the larger Tmin is, the better.

(3) The maximum polarity reversal interval (Tmax) is small Tmax is obtained by the product of "k + 1" and Tw. In order for the bit clock to follow the jitter of the reproduction signal, the polarity must be frequently inverted. Therefore, Tma
x should be small. (4) The constraint length Lc is small The length of the data before and after the reference when demodulating the modulated data is called the constraint length. The larger this value, the larger the error propagation and the more complicated the circuit. Therefore, the smaller Lc is, the better.

(5) Low amount of low frequency components As a measure for evaluating the amount of low frequency components, DSV (Digital Sum)
Variation) is used. This value is obtained by allocating "+1" to bit 1 of the recording signal and "-1" to bit 0 and calculating the sum from the beginning of the signal to a certain point. When recording / reproducing a signal on / from a recording medium, a direct current component and a low frequency component are cut off. That is, when the total sum has a large value of + or −, the recording signal waveform has a DC component in its frequency spectrum, but normally the recording signal or the reproduction signal is transmitted through the AC coupling element. Therefore, when the recording signal waveform has a DC component as described above, the recording signal waveform is distorted during transmission, which is not preferable. Moreover, even if the same waveform as the original recording signal waveform is reproduced at the time of reproduction, the DC component lost by the AC coupling element cannot be reproduced. For this reason, it is desirable that the recording signal waveform does not include a DC component.

As a method focusing on the above conditions (1) to (4), for example, Japanese Patent Publication No. 5-34747 discloses (d, k; m, n) = (2, 7; i). , 2i) R
LL code (i is a natural number) and JP-A-52-128024.
(D, k; m, n) = (1,7;
2i, 3i) There is an RLL code. Further, as a modulation method that also pays attention to the condition (5), there is an EFM modulation method disclosed in Japanese Patent Publication No. 1-27510. In this modulation method, 8-bit input data is “d = 2” “k = 10”
Is modulated into a 14-bit channel code subject to the constraint of “d = 2” and “k = 1” at the boundary value of each code.
Three bits are added to satisfy the constraint of "0" and to bring the DSV close to 0. Therefore, this modulation code corresponds to a (2,10; 8,17) RLL code.

[0007] Another method is Japanese Patent Publication No. 4-77991.
As shown in No. 6, there is a method of performing modulation from 8 bits to 14 bits so that the run length of bit 0 satisfies the constraint even at the boundary part of the modulation code. "CDS (Cord word
The 14-bit conversion code "Digital Sum) = 0" corresponds to the 8-bit input code in a one-to-one correspondence. Also, "CDS
The modulation code of "= 0" has a different CDS code,
In addition, one set of modulation codes having different CDS absolute values corresponds to the input code. As a result, the modulation code is selected so that the DSV approaches 0, and the low frequency component is suppressed. This modulation code is (1,7; 8,14) RL
It corresponds to the L code.

Further, in Japanese Unexamined Patent Publication No. 6-311042, in the (d, k; m, n) RLL code, modulation from m bits to "nd" bits is performed, and DSV is close to 0, Moreover, d bits are added so as to satisfy the constraint of (d, k). However, | CDS | (absolute value of CDS)
When is relatively small, the variation of DSV is small, so the modulation code from m bits to "nd" bits is in a one-to-one correspondence. It corresponds to the input code. As a code satisfying this modulation rule, (2,9; 8,17) RLL
Codes and (1,7; 8,13) RLL codes are listed.

[0009]

In any of the methods considering the above condition (5), the purpose is to bring the DSV close to 0. Therefore, additional bits are prepared and a plurality of modulation tables are prepared. Is used. Therefore, there is a problem that the restriction on the number of 0s between 1 and 1 must be relaxed and the number of bits after modulation must be increased.

Therefore, as compared with Japanese Patent Publication No. 5-34747 and Japanese Patent Laid-Open No. 52-128024, the detection window width Tw becomes smaller and the minimum polarity reversal interval Tmin.
Is small, and the maximum number k of 0s between 1 and 1 is large. In consideration of the above-mentioned conventional problems, the present invention is disclosed in Japanese Patent Publication No. 5-34.
While maintaining the parameters d, k, m, and n possessed by Japanese Patent Laid-Open No. 747 and Japanese Patent Laid-Open No. 52-128024, D
An object of the present invention is to provide a modulation method and a circuit that bring SV close to 0, and a demodulation method and a circuit.

[0011]

According to the present invention, an arbitrary m-bit array is replaced with an arbitrary n-bit (where n> m) array.
By the m-n modulation method in which the conversion is performed in association with each other, each m bit of the input digital data is used as a code modulation unit, and each m bit is converted into n-bit modulated data by m-n.
In a digital modulation method for modulating, a non-zero arbitrary element of a Galois field GF (2 ^m ) is multiplexed as dummy data at the head of input block data composed of a predetermined number of code modulation units, and the dummy data By adding the Reed-Solomon code calculated on the multiplexed block data to the block data to form an RS code added block, and multiplying the RS code added block by elements of a plurality of types of Galois field GF (2 ^m ). A plurality of types of block data are generated, and the DC components of the respective modulation block data obtained by m-n modulating the plurality of types of block data are compared with each other to obtain modulation block data having a small absolute value of the DC component. be multiplied select the corresponding original Galois field GF (2 ^m), the original selected Galois field GF (2 ^m) to the RS code adding block To generate a modulated block data obtained block data m-n modulation on by a digital modulation method.

Further, in the above, the selection is based on specifying the modulation block data in which the absolute value of the cumulative value of the DC component at the final bit of the modulation block data is the smallest, is there. Further, in the above, it is a digital modulation method in which the selection is performed based on specifying the modulation block data having the smallest absolute value of the maximum amplitude of the modulation block data.

Further, according to the present invention, each m of the input digital data is converted by an mn modulation method in which an arbitrary n-bit (where n> m) arrangement is converted into an arbitrary m-bit arrangement in a one-to-one correspondence. In a digital modulation circuit that m-n-modulates each m-bit into n-bit modulation data with m bits as a code-modulation unit, a Galois field is placed at the beginning of input block data composed of a predetermined number of code-modulation units. GF (2 ^m )
A multiplex circuit that multiplexes any non-zero element as dummy data, and an RS code added block by calculating a Reed-Solomon code for the block data in which the dummy data is multiplexed by the multiplex circuit and adding it to the block data. An RS encoding circuit to configure, a Galois field multiplication circuit that generates a plurality of types of block data by multiplying the RS code addition block by an element of a plurality of types of Galois field GF (2 ^m ), and the plurality of types of blocks Computation means for obtaining the DC component of each modulated block data obtained by m-n modulating each data, comparison means for mutually comparing the absolute values of the DC components, and comparison results by the comparison means. based on the selection hand to select the original of the DC Galois absolute value corresponds to a small modulation block data components GF (2 ^m) If the selected Galois GF (2
^m ) is applied to the RS code-added block to modulate the block data obtained by m-n modulation to generate modulated block data.

Further, in the above, the selecting means is an element of the Galois field GF (2 ^m ) corresponding to the modulation block data in which the absolute value of the cumulative value of the DC component at the final bit of the modulation block data is the minimum. Is a digital modulation circuit for selecting. Further, in the above, the selecting means is a digital modulation circuit for selecting the element of the Galois field GF (2 ^m ) corresponding to the modulation block data having the minimum absolute value of the maximum amplitude of the modulation block data. Further, in the above, further, each of the plurality of types of block data obtained by the original multiplication of the plurality of types of Galois field GF (2 ^m ) has a memory for storing, respectively, the modulation means, from the memory Galois field GF (2 selected by the selecting means
read the block data corresponding to the element ^m )
It is a digital modulation circuit that modulates. Further, in the above, further, a memory for storing the RS code addition block, and RS code addition block data is read from the memory, and the Galois field G selected by the selecting means is selected.
And a second Galois field multiplication circuit for generating a plurality of types of block data by multiplying the elements of F (2 ^m ) and outputting the block data to the modulation means.

Further, according to the present invention, each n-bit of the input digital data is used as a code demodulation unit, and n-m demodulation is performed on each m-bit (where n> m) demodulation data to obtain a predetermined number of code demodulation units. The demodulation block data corresponding to is sequentially generated, the Reed-Solomon code added to the sequentially generated demodulation block data is used to error-correct the demodulation block data, and the demodulation block data after the error correction is added to the head. and which detects the original of the block data multiplied Galois field GF (2 ^m), the demodulation block data after error correction, the detected Galois field GF (2 ^m)
It is a digital demodulation method of generating original block data by dividing by.

Further, according to the present invention, each n-bit of the input digital data is used as a code demodulation unit, and n-m demodulation is performed on each m-bit (where n> m) demodulation data to obtain a predetermined number of code demodulation units. A demodulation circuit that sequentially generates the demodulation block data corresponding to R, and R that performs error correction on the demodulation block data by using the Reed-Solomon code added to the demodulation block data sequentially generated by the demodulation circuit.
The S circuit, the detection circuit for detecting the element of the Galois field GF (2 ^m ) that is added to the head of the demodulated block data after error correction and multiplied by the block data, and the demodulated block data after error correction And a division circuit for dividing by the Galois field GF (2 ^m ) detected by the detection circuit.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION

1. DSV of information word First, an information word (original data to be recorded / reproduced; “information word” for distinguishing from modulation method number which is ancillary data
In the case of NR-modulating the above) and NRZI modulating this, an example of minimizing the absolute value of DSV will be described.

1-1. Principle of Modulation (FIG. 4) First, the principle of modulation of the present invention will be described with reference to FIG. In the present invention, m bits of input data are used as a modulation unit, and each m bits is m-n modulated (code conversion) into n bits to obtain a (d, k; m, n) RLL code, and then this is converted. , NRZI modulation. A plurality of types of modulation methods are prepared as the mn modulation method, and among them, an mn modulation method that minimizes the DC component after mn modulation and NRZI modulation is selected for each block. , Mn modulation is performed on each block by the selected modulation scheme, and data for identifying the selected mn modulation scheme (modulation scheme number data) is added to the mn modulation data of the block,
The data after the identification data is added is NRZI-modulated and output.

In FIG. 4, the input data supplied to the input terminal 28 is input to the serial / parallel converter 29 and output as m-bit parallel data. The m-bit data is converted into n-bit modulation data by the m-n modulator 30. The m-n modulator 30 is composed of j kinds of m-n modulators 30a, 30b, ... Which have different modulation systems, and simultaneously generates j kinds of m-n modulated data.

The generated j kinds of mn modulated data are
It is supplied to the DSV calculator 31 and the memory 37. The DSV calculator 31 has j kinds of DSV calculators 31a, 31b, ... Inside, and each DSV calculator 31a, 31b ,.
The absolute value | DSV | of the DSV of each NRZI modulated data when the mn modulated data output from the -n modulators 30a, 30b, ... Is NRZI modulated is calculated. This calculation is performed for a block (a unit composed of a predetermined number of m bits, which is a modulation unit).

The minimum | DSV | selector 32 is a DSV calculator.
By comparing the data output from 31a, 31b, ..., the output that minimizes the absolute value | DSV | of DSV is specified, and the mn modulation method corresponding to this is selected. This selected m-
The n modulation method number information (corresponding to the type selection identification information in the claims) is supplied to the selector 33 and the modulation method number adder 36.

After the operation of the minimum | DSV | selector 32 is completed, the selector 33 sequentially inputs each m-n modulation output read from the memory 37 and corresponds to the number selected by the minimum | DSV | selector 32. Select only the output that you want to output. The mn modulated data output from the selector 33 is sent to the parallel / serial converter 34, converted into serial data, and then supplied to the modulation method number adder 36.

The modulation system number adder 36 has a minimum | DSV |
The number information of the modulation method selected by the selector 32 is multiplexed on the serial data, and the output is input to the NRZI modulator 38. The NRZI modulator 38 NRZI-modulates the input multiplexed data and outputs the NRZI-modulated data to the output terminal 35.

Thus, in the present invention, a plurality of m-
Among the n modulation methods, D after mn modulation and NRZI modulation
An mn modulation method that minimizes the absolute value of SV is selected for each block, the block is mn modulated by the selected mn modulation method, and the selected mn modulation method is selected. The identification data shown is multiplexed and this multiplexed data is NRZI modulated.

In the present invention, the memory 37 is omitted, and instead of the memory 37, the m-n modulator 30 is used again.
It may be configured to output n-modulated data. Also,
Instead of providing j kinds of mn modulators 30a, 30b ,,, by replacing the input bit string with j kinds of bit strings and inputting these into a single mn modulator, mn modulation is performed. , J types of modulation can be performed. Further, by using the CDS and the polarity information about the n-bit modulation code, it is possible to calculate the DSV without using the m-n modulator. Instead of providing j m-n modulators, j kinds of m-n modulations may be realized by driving a single m-n modulator at high speed.

1-2. First Embodiment (Embodiment of Modulator: FIG. 1) In the first embodiment, DSV after mn modulation and NRZI modulation is performed.
The mn modulation method that minimizes the absolute value at the end of the block is selected from 24 kinds of mn modulation methods as the mn modulation method for the block. In addition, each m-bit information word of the block is converted into an n-bit code word (mn modulation) by the selected m-n modulation method. This m-n modulated data is NRZI modulated and output. One block is composed of a predetermined number of information words, and each information word is composed of m bits. For example, one block is composed of 800 bits of input data.

The input data input from the input terminal 1 is
First, it is stored in 1 block memory 2. This one block memory 2 is composed of a FIFO (First In First Out) memory, and its capacity corresponds to one block of information words (the number of bits of input data existing between synchronous data). Each m-bit information word stored in the 1-block memory 2 is read in the order of storage, and RLL is performed every m bits.
The modulator 3 performs m-n modulation to obtain a (d, k; m, n) code. The type of mn modulation used here is |
DSV | Specified by the comparator 17a. The m-n modulation data converted from the m-bit information word to the n-bit code word by the RLL modulator 3 is NRZ-modulated by the NRZI modulator 4 together with the synchronization signal and the number data indicating the m-n modulation method.
The data is I-modulated and output from the output terminal 5 as recording data on the recording medium.

In the first embodiment, the m-n modulation system used in the RLL modulator 3 has 24 kinds of m-n so that the absolute value at the block end of DSV after NRZI modulation is minimized. From the modulation methods, each block is selected by the following processing.

First, the input data input from the input terminal 1 is stored in the one block memory 2 as described above, and is also sent to the CDS calculator 10 composed of a ROM.
The table number data “0 to 23” is input to the CDS calculator 10 from the table number generator 11 for every m bits of input data. That is, 24 table number data are sequentially input corresponding to the input of m bits of input data.

The CDS calculator 10 outputs the polarity data designated by the table number data and the m-bit input data to the exclusive OR circuit 13 in the order of the table numbers. Also,
The CDS calculator 10 outputs the CDS data designated by the table number data and the m-bit input data to the calculator 12 in the order of the table numbers.

The polarity data means m bits of input data by m-n modulation method of each table of "0-23".
In the case of n modulation and further NRZI modulation, the final bit is data indicating whether it is a high level "1" or a low level "0", and each m bit and each table number. And is stored in advance in the CDS calculator 10 in association with. However, input m-bit mn
If the beginning of the n bits after modulation is “1”, the NR
ZI modulated data starts with "1" and has m bits of input m bits.
If the beginning of n bits after n modulation is “0”, the N
The RZI modulated data shall start with "0".

The CDS data is m of the input data.
When the bits are mn modulated by the mn modulation method of each table of "0 to 23" and further NRZI modulated, it is data indicating a direct current component of each modulation data,
Corresponding to each m bit and each table number, the CDS is set in advance.
It is stored in the calculator 10. However, when the beginning of n bits after m-n modulation of the input m bits is "1", the NRZI modulated data starts with "1" and the input m
When the head of n bits after mn modulation of the bit is "0", the NRZI modulated data is assumed to start with "0".

The polarity data output from the CDS calculator 10 is exclusive OR'ed with the polarity data input immediately before and processed by the same table number in the exclusive OR circuit 13, The result is input to the 24-stage polarity shift register 14. The polarity data input immediately before and processed by the same table number is supplied to the exclusive OR circuit 13 from the output side of the 24-stage polarity shift register 14 as shown in the figure.

The CD output from the CDS calculator 10
The S data is added to or subtracted from the CDS data that was input immediately before and processed by the same table number by the arithmetic unit 12, and the result is input to the 24-stage intra-block DSV shift register 15. The CDS data that was input immediately before and processed with the same table number is
As shown in the figure, it is supplied from the output side of the 24-stage DSV shift register 15 in the block to the arithmetic unit 12.

The selection of the addition or the subtraction in the arithmetic unit 12 is performed according to the polarity data which is input immediately before and processed by the same table number. That is, when the immediately preceding polarity data is low level "0", there is no need to invert the sign, so addition is selected. Further, when the immediately preceding polarity data is at the high level "1", the sign needs to be inverted, so that the subtraction is selected. Whether or not the sign inversion is necessary is determined by the polarity data and the CDS as described above.
“If the beginning of n bits after m-n modulation of the input m bits is“ 1 ”, the NRZI modulated data starts with“ 1 ”, and the n-bit data after m-n modulation of the input m bits is When the head is “0”, the NRZI modulated data is “0”
It begins with "."

Through the above-described processing, the 24-stage polarity shift register 14 performs m-n modulation on the latest input m bits by the method of each table number, and further, the modulated data obtained by NRZI modulation. The polarity of the last bit is stored in the order of table numbers. Similarly, within a 24-stage block D
The SV shift register 15 performs m-n modulation on the latest input m bits by the method of each table number, and further, NR
DS at the last bit of the modulated data obtained by ZI modulation
V is stored in the order of table numbers.

Therefore, when the processing for one block is completed, the 24-stage polarity shift register 14 performs mn modulation on the block by the method of each table number, and
The polarities of the final bits of the modulated block data obtained by NRZI modulation are stored in the order of table numbers.
Similarly, in the 24-stage intra-block DSV shift register 15, the DSV at the final bit of the modulated block data obtained by mn modulation of the block by the method of each table number and further NRZI modulation is They are stored in the order of table numbers. The polarity data and the DSV data are sent to the DSV calculator 16a in the order of table numbers when the processing for one block is completed. After that, the 24-stage polarity shift register 14 and the 24-stage in-block DSV shift register 15 are both reset, and the process for the next block is similarly performed.

The DSV calculator 16a uses the register 18a to select m- by the method selected in the immediately preceding block.
DSV data at the final bit of the modulation block data that has been n-modulated and further NRZI-modulated is input. Also,
The DSV calculator 16a receives the polarity data of the final bit of the modulation block data, which is mn-modulated by the method selected in the immediately preceding block and further NRZI-modulated, from the register 18b. The polarity data and the DSV data are transferred from the registers 18a and 18b to the DSV when the processing for one block in the shift registers 14 and 15 is completed.
Each value is input to the calculator 16a, held in the register of the DSV calculator 16a until the processing relating to the block is completed, and used for the following calculation.

The DSV calculator 16a uses the last bit of the current block (the block currently being processed) input from the shift register 15 in the order of table numbers to the DSV data of the last bit of the immediately preceding block input from the register 18a. DSV data is added or subtracted, and the result is
Table number order: | DSV | Comparator 17a and register
Output to the input side switch terminal of 18a. That is, the DS at the last bit of the current block obtained by considering the history
V data in the order of table numbers | DSV | Comparator 17a
And output to the input side switch terminal of the register 18a.

The addition or subtraction is selected by the DSV calculator 16a according to the polarity data of the last bit of the immediately preceding block input from the register 18b. That is,
When the polarity of the last bit of the immediately preceding block is low level “0”, addition is selected because it is not necessary to invert the sign. When the polarity of the last bit of the immediately preceding block is high level “1”, the sign needs to be inverted, and therefore subtraction is selected. Whether or not the sign inversion is necessary is basically determined by referring to the polarity data and the CDS as described above, in the case where “the beginning of n bits after m-n modulation of input m bits is“ 1 ””. , The NRZI modulated data starts with "1",
The beginning of n bits after m-n modulation of input m bits is "0"
In this case, the NRZI modulated data is defined as "beginning with 0".

The | DSV | comparator 17a is a DSV calculator 16
DSV data at the last bit of the current block sent from a in the order of table numbers (DS with history considered)
V data) is compared with the previously stored DSV data relating to the conventional table number, and the one having the smaller absolute value is stored as the DSV data. That is, the DSV data
Update with a smaller absolute value.

As a result of the above comparison, the | DSV | comparator 17a determines that the absolute value of the DSV data input from the DSV calculator 16a is greater than the absolute value of the DSV data regarding the previous table number stored previously. If it is smaller, switch each switch on the input side of the registers 18a and 18b to the DSV calculator.
Set on each output side of 16a. This allows register 18a
Stores the DSV data having a smaller absolute value than before, and the register 18b stores the polarity.

Therefore, when the processing of the current block is completed, the register 18a is subjected to mn modulation and NRZI modulation in such a manner that the absolute value of the DSV data at the final bit of the modulation block data is minimized. The DSV data is stored. Also register
In 18b, the polarity data of the last bit of the modulation block data in the above case is stored.

When the process for the final table number is completed, the | DSV | comparator 17a outputs the m-value that minimizes the absolute value of the DSV data at the final bit of the modulation block data.
The table number data indicating the n modulation method is converted into the RLL modulator.
3 and modulation method number generator 6 are output. After that, | DS
The V | comparator 17a is reset and the processing for the next block is similarly performed.

The RLL modulator 3 reads out the data in the 1-block memory 2 in the order of storage, mn-modulates it by m bits, and converts it into a (d, k; m, n) code. The mn modulation method used at this time is a method specified by the table number data sent from the | DSV | comparator 17a as described above.

The modulation method number generator 6 generates n-bit number data corresponding to the table number data input from the | DSV | comparator 17a as described above. The sync signal generator 8 also generates an n-bit sync signal. These n-bit data are transferred to the RLL modulator 3 by the switch 9.
Of the NRZI modulator 4 and the NRZI modulator 4
I is modulated, but D of this NRZI modulated data
The number data and the synchronizing signal are selected so that the absolute value of SV becomes small.

1-3. Second Embodiment (Modulator Embodiment: FIG. 2) In the second embodiment, in the block of the absolute value of the DSV of the modulation block data which is m-n modulated and further NRZI-modulated. The mn modulation method that minimizes the maximum value is selected from 24 kinds of mn modulation methods as the mn modulation method of the block. In addition, according to the selected m-n modulation method, each m-bit information word of the block is converted into an n-bit code word (mn modulation) as in the first embodiment. n modulation data is NRZI
Modulated and output. The structure of one block is the same as that of the first embodiment. Hereinafter, in the second embodiment, the same components as those of the first embodiment will be designated by the same reference numerals in the drawings, and the description thereof will be simplified.

The input data input from the input terminal 1 is
First, it is stored in 1 block memory 2. The input data stored in the 1-block memory 2 is read out in the order of storage and is m-n modulated by the RLL modulator 3 by m bits to be a (d, k; m, n) code. The mn modulation scheme used here is specified by the | DSV | comparator 17b. From the m-bit information word to n in the RLL modulator 3
The mn modulated data converted into the bit codeword is NR
The data is NRZI-modulated by the ZI modulator 4 and is output from the output terminal 5 as recording data on the recording medium.

In the above, in the mn modulation method used in the RLL modulator 3, the maximum value of the absolute value of the DSV of the mn modulated and NRZI modulated modulation block data in the block is the maximum. The smallest m-n modulation method is
Each block is selected from the 24 types of m-n modulation methods by the following processing.

First, the input data input from the input terminal 1 is C, which is composed of a ROM, as in the first embodiment.
It is also sent to the DS calculator 10. In this CDS calculator 10,
The table number data “0 to 23” is input from the table number generator 11 for every m bits of input data.

The CDS calculator 10 outputs the polarity data designated by the table number data and the m-bit input data to the exclusive OR circuit 13 in the order of the table numbers. Also,
The CDS calculator 10 outputs the CDS data designated by the table number data and the m-bit input data to the calculator 12 in the order of the table numbers. The polarity data and the CDS data have the same meaning as in the first embodiment.

The polarity data output from the CDS calculator 10 to the exclusive OR circuit 13 is 2 as in the first embodiment.
It is input to the four-stage polarity shift register 14. Also CD
The CDS data output from the S calculator 10 is added to or subtracted from the CDS data input immediately before and processed by the same table number by the calculator 12 as in the first embodiment, and the result is obtained. Is input to the 24-stage intra-block DSV shift register 15. The selection of addition or subtraction is performed in the same manner as in the first embodiment.

By the above-described processing, the 24-stage polarity shift register 14 performs m-n modulation of the latest input m bits by the method of each table number, and further, the modulated data obtained by NRZI modulation. The polarity of the last bit is stored in the order of table numbers. Similarly, within a 24-stage block D
The SV shift register 15 performs m-n modulation on the latest input m bits by the method of each table number, and further, NR
DS at the last bit of the modulated data obtained by ZI modulation
V is stored in the order of table numbers.

In the second embodiment, the polarity data of the last bit of the latest m-bit input modulation data stored in the shift register 14 by the above-mentioned operation and the shift register
DSV data of the last bit of the modulation data of the latest m-bit input stored in 15 and DSV data from the respective output sides of the shift registers 14 and 15 are sequentially displayed in the order of table numbers.
It is output to the calculator 16b.

The DSV calculator 16b sends m-values from the register 18a according to the method selected in the immediately preceding block.
DSV data at the final bit of the modulation block data that has been n-modulated and further NRZI-modulated is input. Also,
To the DSV calculator 16b, the polarity data of the final bit of the modulation block data that has been mn modulated by the method selected in the immediately preceding block and further NRZI modulated is input from the register 18b. The polarity data and the DSV data are transferred from the registers 18a, 18b to D when the processing for the first m bits in the shift registers 14, 15 is completed.
It is input to the SV calculator 16b, held in the register of the DSV calculator 16b until the processing for the current block is completed, and used for the following calculation.

The DSV calculator 16b receives the DSV data at the last bit of the immediately preceding block input from the register 18a and the DSV data (each table) sequentially input from the shift register 15 for each m-bit process. Mn modulation by the number m-n modulation system, and further NRZ
DSV data at the final bit of each I-modulated n-bit modulation data) is added or subtracted, and the result is shown in the order of table numbers | DSV | comparator 17c and delay memory 21a.
Output to That is, the DSV data obtained in consideration of the history are output to the | DSV | comparator 17c and the delay memory 21a in the order of table numbers. Further, the polarity data of the final bit after the addition or subtraction is output to the delay memory 21b. The selection of addition or subtraction by the DSV calculator 16b is
It is selected according to the polarity of the last bit of the modulated block data which is mn modulated and NRZI modulated by the method selected in the immediately preceding block. That is, when the polarity of the last bit of the immediately preceding block is low level “0”,
Addition is selected because there is no need to invert the sign. On the contrary, when the polarity of the last bit of the immediately preceding block is the high level “1”, the sign needs to be inverted, and thus the subtraction is selected. The principle of the necessity of this sign inversion is
This is similar to each case described above.

The | DSV | comparator 17c is used for the DSV calculator 16
The DSV data (DSV data in which the history is taken into account) at the last bit of the modulation data obtained from the latest input m bits sent from b in the order of the table number is the same table number obtained from the immediately preceding input m bits. DSV data at the last bit of the modulation data (considering history, and
DSV data with the largest absolute value in the block), the one with the larger absolute value is the DS of the table number.
The V data is output to the maximum | DSV | shift register 20a of 24 stages. That is, D related to the table number
The SV data is updated with a large absolute value and output to the maximum | DSV | shift register 20a of 24 stages. In addition,
The DSV data of the final bit of the modulation data for the same table number obtained from the immediately preceding input m bits is
The maximum | DSV | shift register 20a of 24 stages supplies the | DSV | comparator 17c from the output side.

With the above processing, the maximum | DSV of 24 stages
The shift register 20a stores the DSV data having the maximum absolute DSV value in the current block in the order of table numbers.

Therefore, when the processing for one block is completed, the maximum absolute value of DSV in the current block is stored in the maximum | DSV | shift register 20a of 24 stages in the order of table numbers. . Each DSV data (maximum value data) has a | DSV | comparator in the order of table numbers when the processing of the current block is completed.
Sent to 17b. Then, the maximum | DSV | shift register 20a of 24 stages is reset, and the processing for the next block is similarly performed.

| DSV | Comparator 17b has a maximum of 24 stages |
DSV | The DSV data of the current block sent from the shift register 20a in the order of the table numbers (the DSV data having the largest absolute value regarding the table number in the current block in consideration of the history) is previously stored. Compared with the DSV data relating to the conventional table number, the one having the smaller absolute value is stored as the DSV data. That is, the DSV data is updated with a small absolute value.

Further, as a result of the above comparison, the | DSV | comparator 17b determines that the absolute value of the DSV data relating to the current table number input from the maximum | DSV | shift register 20a of 24 stages is previously stored. If it is smaller than the absolute value of the DSV data for the table number of, the switches on the input side of registers 18a and 18b are
Set on each output side of 21a, 21b. This allows the register
The DSV data at the final bit of the modulation block data relating to the current table number is stored in 18a, and its polarity is stored in the register 18b.

Therefore, when the processing of the current block in the | DSV | comparator 17b is completed, the register 18
a is the final value of the modulation block data in the case where mn modulation is performed by the mn modulation method in which the maximum absolute value of the DSV data in the modulation block is minimized, and further NRZI modulation is performed. DSV data in bits is stored. Further, in the register 18b, in the above case,
The polarity data of the last bit of the modulation block data is stored.

When the process for the final table number is completed, the | DSV | comparator 17b outputs the table number data indicating the mn modulation method in which the maximum absolute value of the DSV data in the modulation block is the minimum. , RLL modulator 3 and modulation method number generator 6 are output. After that, | DSV |
The comparator 17b is reset, and the process for the next block is similarly performed.

The RLL modulator 3 reads out the data in the 1-block memory 2 in the order of storage, performs m-n modulation on every m bits, and converts it into a (d, k; m, n) code. The mn modulation method used at that time is a method specified by the table number data sent from the | DSV | comparator 17b as described above.

The modulation method number generator 6 generates n-bit number data corresponding to the table number data input from the | DSV | comparator 17b as described above. The sync signal generator 8 also generates an n-bit sync signal. These n-bit data are transferred to the RLL modulator 3 by the switch 9.
Of the NRZI modulator 4 and the NRZI modulator 4
I is modulated, but D of this NRZI modulated data
The number data and the synchronizing signal are selected so that the absolute value of SV becomes small.

1-4. Third embodiment (embodiment of demodulator: FIG. 3) Modulated by the modulator of the first or second embodiment,
The information recorded on the optical disc is reproduced by a device including the demodulation circuit of FIG.

That is, in this circuit, the reproduced data input to the input terminal 40 is demodulated by the NRZI demodulator 41, and the demodulated output is input to the modulation method number detector 42. This modulation system number detector 42 detects the modulation system number following the synchronization signal,
The detection output is supplied to the RLL demodulator 44. The RLL demodulator 44 performs demodulation by the nm demodulation method corresponding to the detected modulation method number and supplies the demodulation output to the output terminal 45.

2. Modulation number Next, r-bit (r is preferably a small value) modulation number data is generated from the modulation number, and each m-bit of input data is mn-modulated (converted) into n-bit. An example of multiplexing the obtained m-n modulated data and minimizing the absolute value of the DSV when the multiplexed data is NRZI-modulated will be described in the case of "d = 2, r = 15". To do. Note that d is the (d, k; m, n) RLL code d. The r-bit modulation number data is composed of an information section and an inspection section, and this r-bit modulation number data is (d, k; m, n) R as a whole (information section + inspection section).
An example in which the d constraint of the LL code is satisfied is d = 2, r
The case of = 15 will be described. In other words, an example will be described in which d constraint is satisfied when d is relatively large and r is relatively small.

2-1. Principle of Modulation (FIG. 11) First, the principle of modulation of the present invention will be described with reference to FIG. The portion for converting each m bit of the input data into each n bit is the same as in FIG. The parts common to FIG. 4 are the input terminal 28,
Serial / parallel converter 29, mn modulator 30, DSV
An arithmetic unit 31, a minimum | DSV | selector 32, a memory 37, a selector 33, a parallel / serial converter 34, a modulation method number adder 36, an NRZI modulator 38, and an output terminal 35.

In FIG. 11, j numbers corresponding to j m-n modulation schemes are converted into bit data, and error correction codes are added to the respective bit data to obtain r bits. The added r-bit bit data satisfies the d constraint as a whole, and this is multiplexed by the modulation method number error correction code adder 39 as the modulation method number data.

The d constraint is (d, k; m, n) R.
This is a restriction on the LL code, and in the modulation data code-converted to n-bit data, at least "d""0" s must be present between each "1" and "1". .

For example, FIG. 6 shows 24 numbers "0 to 23" in the case of (1, k; m, n) RLL code, that is, in the case of "d = 1". 24 called "0-23"
Since the number of individual pieces is less than 32, it can be originally represented by 5-bit data, but 7 bits are required to satisfy the constraint of “d = 1”. Therefore, 7 bits are allocated to the information part (number part of "0 to 23").

In each of the above 7-bit data, (a) of FIG.
By multiplying the generator polynomial G shown in (1) (the generator polynomial in the case of d = 1), a 4-bit error correction code is obtained. However, these 4-bit error correction codes may not be able to satisfy the constraint of “d = 1” as they are. That is, it may be continuous with "11". Therefore, by assigning a 4-bit error correction code to the odd bits of the 8-bit check unit and substituting "0" for the even bits, the error correction is made to comply with the constraint of "d = 1". The code is used as the code to generate the modulation system number data.

Further, if the bits before and after the "0" assigned to the even bits of the inspection section are both "0", even if "1" is assigned instead of "0", "d = 1""
Can be satisfied. Such bits are indicated by "*" in FIG. In such a case, "0" or "1" is selected so that the DC component is minimized.

FIG. 8 shows 24 modulation scheme numbers "0 to 23", which satisfies the constraint of (2, k; m, n) RLL code, that is, the constraint of "d = 2", and the modulation. An example in which the bit number r of the scheme number data is reduced will be shown. In FIG. 8, r
= 15, a slightly larger number of 11 bits are allocated to the information part, and information words satisfying the constraint of "d = 2" are selected from them. Furthermore, a 4-bit check unit obtained by multiplying the generator polynomial of FIG. 9B is added to each of the above information words,
Twenty-four combinations (combination of 11 bits of information part and 4 bits of check part) satisfying the constraint of “d = 2” are extracted and adopted as the modulation method number data. By selecting in this way, it is possible to obtain modulation method number data that satisfies “d = 2” and has a small r.

In the present invention, the mn modulation data of the input data is multiplexed on the synchronization signal and the modulation method number data, and when these are NRZI-modulated, the DSV thereof becomes small so that the above-mentioned 2 One of the types of modulation method number data is selected. Further, in the present invention, (d, k;
(m, n) RLL code d is increased (d = 2) and the number r of bits is suppressed to be small, and modulation method number data is provided. In the following, an embodiment in which one of two types of modulation method number data is selected (an example in which “d = 1”) and a modulation method number data in “d = 2” are given according to a specific circuit. An example will be described.

2-2. Fourth Embodiment (Modulator Embodiment: FIG. 5) The fourth embodiment (FIG. 5) is substantially the same as the first embodiment (FIG. 1). Therefore, the description of the same parts as those in FIG. 1 is omitted.
The common part with FIG. 1 is input terminal 1 and 1 block memory.
2, RLL modulator 3, NRZI modulator 4, output terminal 5,
CDS calculator 10, table number generator 11, exclusive OR circuit 13, calculator 12, 24-stage polarity shift register 14, 2
4-stage DSV shift register 15, DSV calculator 16a, |
DSV | comparator 17a, register 18a, register 18b, modulation method number generator 6, and sync signal generator 8. The part not shown in FIG. 1 is a modulation system number error correction code generator 27. Also, the part that is slightly different from FIG. 1 is the switch 9
It is.

As described above, when the | DSV | comparator 17a completes the comparison process of the DSV data indicated by the final table number of the current block, the | DSV | comparator 17a outputs the last bit of the modulation block data. DSV at
The table number data indicating the m-n modulation method that minimizes the absolute value of the data is output to the RLL modulator 3 and the modulation method number generator 6.

Corresponding to this, the modulation system number generator 6
Generates 7-bit number data (FIG. 6; "d = 1") corresponding to the table number data. This 7
The bit number data is output to the terminal of the switch 9 and is also sent to the modulation method number error correction code generator 27.

The modulation system number error correction code generator 27 uses the 7-bit number data input from the modulation system number generator 6 to generate the polynomial G (a) of FIG. 9 (in the case of "d = 1").
And the 4-bit data obtained by this is multiplied by "d
An 8-bit error correction code is generated by arranging four "0" s so as to satisfy the constraint "= 1".

When there are two types of error correction codes (see "*" in FIG. 6), the modulation method number error correction code generator 27 outputs m-n according to the selected method output from the RLL modulator 3. When the modulated data is multiplexed and NRZI-modulated, the error correction code having the smaller DSV is selected and output to the terminal of the switch 9.

The switch 9 generates a sync signal generated by the sync signal generator 8, 7-bit modulation method number data generated by the modulation method number generator 6, and a modulation method number error correction code generator 27. 8-bit error correction code,
Also, the m-n modulation data for one block output from the RLL modulation circuit 3 is multiplexed and output to the NRZI modulator 4. Thus, the multiplexed data is NRZI modulated.

In the above, the case of "d = 1" has been described, but in the case of "d = 2" (FIG. 8), since there is only one type of error correction code as described above, modulation is performed. The system number error correction code generator 27 outputs the error correction code to the terminal of the switch 9 without comparing the magnitude of the absolute value of DSV.

2-3. Fifth Embodiment (Modulator Embodiment: FIG. 7) The fifth embodiment (FIG. 7) is substantially the same as the second embodiment (FIG. 2). Therefore, the description of the same parts as those in FIG. 2 is omitted.
The common part with FIG. 2 is input terminal 1 and 1 block memory.
2, RLL modulator 3, NRZI modulator 4, output terminal 5,
CDS calculator 10, table number generator 11, exclusive OR circuit 13, calculator 12, 24-stage polarity shift register 14, 2
4-stage DSV shift register 15, | DSV | Comparator 17c
, A maximum of 24 stages | DSV | shift register 20a, register 18a, register 18b, | DSV | comparator 17b, delay memory 21a, delay memory 21b, modulation method number generator 6,
This is the synchronization signal generator 8. 2 are the modulation system number error correction code generator 27, | DSV | comparator 17d, 2
4-stage maximum | DSV | shift register 20b, | DSV |
A comparator 17e, a delay memory 21c, a delay memory 21d, and a selector 22. 2 are a DSV calculator 16c (DSV calculator 16b in FIG. 2) and a switch 9.

In the example of FIG. 2 described above, the DSV calculator 16b,
| DSV | Comparator 17c and 24 stages of maximum | DSV |
The shift register 20a calculates, for each m-n modulation data of the current m bits in the current block, DSV in consideration of the history after NRZI modulation for each table number, and these are calculated in the | DSV | comparator 17b in order. As a result of comparison, the m-n modulation method that minimizes the maximum absolute value of the DSV in the current block is selected.

In the present example, this selection is performed in two ways in consideration of the two types of history resulting from the two types of modulation method number data (see "*" in FIG. 6). That is, the modulation method number data is added at the beginning of the m-n modulation block data output from the RLL modulator 3 by the switch 9, but there are two kinds of modulation method number data as shown in FIG. In that case, the above-mentioned DSV differs depending on which modulation method number data is added, and as a result,
The m-n modulation method that minimizes the maximum absolute value of the DSV in the current block also differs.

Therefore, in this example, the DSV calculator of FIG.
A DSV calculator 16c is provided in place of 16b, and two systems are processed from this DSV calculator 16c.
| Comparing with the comparator 17e, considering the two types of histories resulting from the two types of modulation method number data, the maximum absolute value of the DSV in the current block is the minimum value mn
The DSV of the bit stream output from the NRZI modulator 4 is minimized by specifying the modulation method and also specifying one of the two kinds of modulation method number data.

In the above, the processing of the two systems is
The system of "| DSV | comparator 17c, maximum of 24 stages | DSV | shift register 20a, delay memory 21a, delay memory 21b" and "| DSV | comparator 17d, maximum of 24 stages | DS
V | Shift register 20b, delay memory 21c, delay memory
21d ”system. The selector 22 is switched depending on which system is being processed.

The processing results of both systems are "| DSV |
As a result of comparison by the comparator 17e, as described above, the m-n modulation method that minimizes the maximum absolute value of the DSV in the current block is specified, and the modulation method number data for realizing this is specified. After being specified, these are output to the modulation method number generator (modulation mode signal generator) 6 and the modulation method number error correction code generator 27, and are subjected to the above-described processing.

That is, the switch 9 is the synchronization signal generator 8
Signal generated from the modulation method number generator, 7-bit modulation method number data generated from the modulation method number generator 6, 8-bit error correction code generated from the modulation method number error correction code generator 27, and RLL modulation circuit. NRZI modulator that multiplexes one block of m-n modulation data output from
Output to 4. Thus, the multiplexed data is NRZI modulated.

In the above, the case of "d = 1" has been described, but in the case of "d = 2" (FIG. 8), since there is only one type of error correction code as described above, Of the two processings, one is unnecessary.

2-4. Sixth Embodiment (Embodiment of Demodulator: FIG. 1)
0) modulated by the modulator of the fourth or fifth embodiment described above,
The information recorded on the optical disc is reproduced by a device including the demodulation circuit of FIG.

Since the circuit of FIG. 10 is substantially the same as the circuit of FIG. 3 described above, the same elements as those of the circuit of FIG. 3 are designated by the same reference numerals and the description thereof will be omitted. The circuit of FIG. 10 is different from the circuit of FIG. 3 in that an error correction decoder 43 for modulation method number is provided.

The modulation method number error correction decoder 43 uses the parity check matrix H in the lower 8 bits of the modulation method number data.
By multiplying ((a) of FIG. 9) and comparing the result with the inspection unit (FIG. 6), the presence or absence of an error is inspected and the modulation scheme number data is specified. 9A and FIG. 6 show the case of “d = 1”, “d = 2”
In this case, (b) of FIG. 9 and FIG. 8 are used.

3. In the case where the modulation method number is included in the information word In the above-described first to sixth embodiments, the information word, that is, the original data to be recorded / reproduced is m-n modulated by the selected method and is selected. The data obtained by encoding the modulation method number indicating the m-n modulation method so as to satisfy the d constraint is added, but in place of this, the modulation method number is included in the information word for mn modulation. You can also Hereinafter, such a method will be described with reference to each of the seventh to ninth embodiments.

3-1. Data Format FIG. 12 shows the data format (upper row) in the above-mentioned first to sixth embodiments and the data format (lower row) in the following seventh to ninth embodiments.

As shown in the upper part of the figure, in the first to sixth embodiments, the data of one block, which is the selection unit of the mn modulation system, is the synchronization signal SYNC and the modulation system indicating the mn modulation system of the block. Number part (modulation mode signal part in the figure),
And a data section having information of original recording / reproduction target. The error correction code is added to each of the modulation method number part and the data part as a "check part" and an "data error code".

On the other hand, in the seventh to ninth embodiments, as shown in the lower part of the figure, one block of data consists of the synchronization signal SYNC and the data part, and the data part is the original recording / reproducing target in the block. The number data indicating the description method of the information is included. Further, the error correction code is collectively calculated and added to the data group consisting of the number data indicating the description method and the information to be originally recorded / reproduced.

In the above description, the description system is a system in which arbitrary information is associated with an arbitrary m-bit array, and the m-bit array corresponding to at least one piece of the same information is different between the description systems. , Multiple description methods are available. For example, with respect to the information "A", "0000" is assigned in the first description method, "1000" different from the first method is assigned in the second description method, and the second is used in the third description method. The same "1000" as in the above method is assigned. Further, to the information "B", "0001" is assigned in the first description method, "0001" is assigned in the second description method, which is the same as the first method, and the second description method is used in the second description method. "0010" different from the method is assigned. In this way, the m-bit array corresponding to at least one piece of the same information is assigned differently depending on the description method.

3-2. Seventh Embodiment (Modulator Embodiment: FIG. 1)
3) The input data is first converted into j types of data having different description methods. For example, using m bits, which is a unit of code modulation in mn modulation, as a unit of data conversion, j kinds of data converters 51a are used for j kinds of data having different description systems and the unit of code modulation is The data is converted into m-bit data (m-m conversion). The m-m conversion refers to data conversion of m-bit data of a certain description method into corresponding m-bit data of another description method. The j-type data converter 51a only needs to have a function of converting input data into j-type data having different description systems. For example, the conversion unit does not necessarily have to be m bits. That is, the converted data may be described using m bits as the unit of code modulation, as in the case before conversion.

The data of each description method for one block, which has been m-m converted, is next converted into the j type data conversion number multiplexer 52a.
Thus, the data conversion number data indicating the description method of the block is multiplexed. Here, one block means a data amount composed of a certain predetermined number of m bits, and | DSV
| It becomes the unit of comparison.

A block (numbered block) of each description system in which number data indicating the description system is multiplexed is next subjected to an error correction code operation of the numbered block by the j type error correction encoder 53a. It is added to form the error correction code addition block described in the claims. As described above, in this embodiment, since the error correction is performed on the entire data composed of the number data and the original information to be recorded / reproduced, the product code or the like can be applied and the error correction capability is enhanced. . Each data of the error correction code addition block of each description method is stored in the 1-block memory 54a and is input to the j type | DSV | calculator / comparator 55.

Next, the error correction code addition block of each description system is
DSV | are compared with each other and the error correction code added block having the smallest absolute value is selected. Here, the absolute value to be compared is, for example, the value in the final bit of the error correction code added block. Alternatively, the error correction code addition block in which the absolute value of the maximum amplitude in the error correction code addition block is the smallest may be selected. This point has been described in detail in the above-described first embodiment and the like, and thus the description thereof will be omitted. The configuration of the j type | DSV | arithmetic / comparator 55 has also been described in detail in the above-described first embodiment and the like, and thus the description thereof will be omitted.

When the error correction code added block with the minimum | DSV | is selected, the information is sent to the selector 56, and the selector 56 outputs the error correction code added block with the minimum | DSV | to the RLL modulator 57. Is input to. As a result, the RLL modulator 57 performs m-n modulation, and then the NRZI modulator 58 performs NRZI modulation. R
The configurations and functions of the LL modulator 57 and the NRZI modulator 58 have been described in detail in the above-described first embodiment and the like, and therefore the description thereof is omitted here.

3-3. Eighth Embodiment (Modulator Embodiment: FIG. 1)
4) The eighth embodiment is a circuit configured to reduce the number of block memories. That is, in the above-described seventh embodiment, since the error correction code added blocks of each description method are stored in the 1-block memory 54a, the block memory 54a as a whole needs a capacity of j blocks. . In view of this, in the eighth embodiment, the required capacity of the one block memory 54b is set to one block by storing the input data in the one block memory 54b. In the following description, the description of the same parts as those in the seventh embodiment will be simplified.

First, the j type data converter 51a, the j type data conversion number multiplexer 52a, and the j type error correction encoder 53a calculate error correction code addition blocks based on each description method, and j type | DSV | operation
The comparator 55 compares them with each other to select the error correction code added block having the smallest | DSV |. The result of this selection is sent to the data converter 51b.

When the selection result is input, the data converter 51b reads the data read from the 1-block memory 54b so that the data of the description system based on the error correction code added block with the minimum | DSV | Is converted to m-m. Number data indicating the description system is multiplexed by the data conversion number multiplexer 52b on the m-m converted data, and an error correction code is calculated and added by the error correction encoder 53b. , RLL modulator 57 m-
The signal is n-modulated and further NRZI-modulated by the NRZI modulator 58 and output.

3-4. Ninth Embodiment (Embodiment of demodulator: FIG. 1)
5) FIG. 15 is a circuit for demodulating data configured as shown in the lower part of FIG. 12 by the modulator of FIG. 13 or 14.

The data input to this demodulator is first N
The RZI demodulator 61 performs NRZI demodulation, and then the RLL demodulator 62 performs nm demodulation. An error correction decoder 63 performs error correction on the nm demodulated data. Next, from the data after error correction, the data conversion number detector 64 detects the number data indicating the description method,
This number data is sent to the data inverse converter 65.

The data reverse converter 65 reverses the data input from the error correction decoder 63 by m-m based on the number data input from the data conversion number detector 64. As a result, the data is returned to the data of the original description method (data when input to the modulation circuit of FIG. 13 or 14).

4. When the conversion by the conversion table is performed by the conversion based on the Galois field multiplication In the above-described seventh to ninth embodiments, the information word, that is, the original data to be recorded / reproduced is obtained by data conversion j. Since the modulation scheme number is multiplexed on each type of data and the error correction code is calculated and added to each multiplexed data, j types of error correction encoders are required.

In the following embodiment, R is used as the error correction code.
By using the S (Reed-Solomon) code, it is possible to perform conversion for generating j types of data based on Galois field multiplication instead of data conversion by a conversion table, and thus one error correction encoder is provided. I'm trying to get enough. Hereinafter, the basic Galois field and the properties of the RS code will be briefly described, and then the system using these will be described with reference to the tenth to twelfth embodiments.

4-1. Galois Field The Galois field GF (2 ^m ) is one capable of performing four arithmetic operations on 2 ^m types of numbers (elements). FIG. 16 shows an example of the Galois field GF (2 ³ ). The addition is performed by adding elements of the vector. However, since the element is an element (0 or 1) of GF (2 ³ ), addition is performed by mod2 calculation. The subtraction also has the same result as the addition because it is a mod2 operation. The multiplication / division can be performed using an exponent of the power of the element α, as shown in FIG. However, since there is no exponent for the 0 element, the 0 element detector is required.

4-2. Reed-Solomon (RS) Code As shown in FIG. 18, the RS code handles data with m bits of the information bit string as a unit of 1 byte, and this data is on GF (2 ^m ). It is expressed as the origin of the Galois field of. The method of generating the RS code is as shown in FIG.
The information polynomial I (x) input to the error correction encoder is set to 2
After shifting by t bytes, this is divided by the generator polynomial G (x) to obtain the remainder polynomial P (x). However, AmodB
Indicates the remainder when A is divided by B. An information polynomial I obtained by shifting the remainder polynomial P (x) by 2t bytes
The one connected after (x) x ^2t is the code polynomial W (x) output from the error correction encoder.

This code polynomial W (x) is the generator polynomial G
It is clearly divisible by (x). However, when an error occurs, the error polynomial E (x) is added to the code polynomial W (x). Therefore, the receiving polynomial R
(X) is a generator polynomial G when an error occurs.
It is not divisible by (x). On the decoder side, it is the syndrome polynomial S (x) shown in the conventional RS code column of FIG. Here, S (x) = (I (x) x 2t + P (x) + E (x)) modG (x) = (I (x) x 2t + P (x)) modG (x) + E (x) modG It is possible to correct the error by using (x) = E (x) modG (x). However,
The condition is that the error is t bytes or less.

4-3. Multiplication of Reed-Solomon code and Galois field Here, the coefficient of the code polynomial W (x) of this RS code is
Consider a case where a Galois field element α ⁱ (≠ 0: constant value) on GF (2 ^m ) is multiplied. FIG. 21 shows a case of a code polynomial W ′ (x) generated by multiplying the code polynomial output from the RS encoder by an element α ^j of a certain Galois field, in comparison with FIG. 19.

As shown in the figure, the error polynomial E (x) is added in the same manner as in FIG. 19 to obtain the reception polynomial R ′ (x). On the decoder side, error correction is performed by performing a process of dividing the reception polynomial R ′ (x) by the generator polynomial G (x). The polynomial expression of the division process is the syndrome polynomial S (x) shown in the RS code column when the Galois field of FIG. 20 is multiplied. Here, S (x) = (α ⁱ (I (x) x ^2t + P (x)) + E (x)) modG (x) = α ⁱ (I (x) x ^2t + P (x)) modG (x ) + E (x) mod G (x) = E (x) modG (x).

In this way, R when the Galois field is multiplied
The syndrome polynomial S (x) shown in the column of S code and the syndrome polynomial S (x) shown in the column of conventional RS code are both E (x) modG (x), and both are equal. Therefore, it is possible to perform error correction even on data in which the code word is changed by multiplying the code polynomial W (x) by the element of the Galois field. That is, after error correction, the original information word can be obtained by performing division with the element of the multiplied Galois field.

4-4. Data format when multiplying RS code by Galois field FIG. 22 shows a data format when the original information of the Galois field to be multiplied is included. Dummy data is multiplexed at the beginning of the block that is converted by Galois field multiplication. As the dummy data, for example, an element α ⁰ (= 1) of Galois field can be used. An error correction code is generated by the RS encoder using the data after the dummy data multiplexing as an information word.

When this codeword is multiplied by the element of the Galois field, the information of the multiplied Galois field exists in the dummy data part. For example, when the dummy data is the Galois field element α ⁰ (= 1), the multiplied Galois field element α ⁱ exists in the dummy data part. The information in the dummy data section is incorporated as data in the codeword. At the time of decoding, for the information word output from the RS decoder, the Galois field at the beginning of the data block,
The original information word is obtained by dividing the subsequent 1-block data in units of m bits.

4-5. Tenth Embodiment Input data is input from the input terminal 70 in units of m bits which are 1 byte of the error correction code, and first, the dummy data multiplexer 71 outputs these m-bit data. For each block that is a group, 1-byte (m-bit) dummy data is multiplexed at the beginning thereof. Here, one block means a data string composed of a certain predetermined number of byte data (m bits), which is a unit of | DSV | comparison.

An error correction code is calculated by the RS encoder 72 for one block of data to which dummy data has been added, and the error correction code is added.

The data output from the RS encoder 72 is
The j-type Galois field multiplier 73a forms a block in 1-byte (m-bit) units, and each element of the Galois field α
multiplied by ⁱ . It is also possible to perform error correction on a codeword converted by multiplying the entire data of one block including the error correction code by the Galois field element α ⁱ , as described above.

Therefore, unlike the seventh and eighth embodiments, after the data conversion for converting the j kinds of description systems,
The j kinds of error correction circuits that respectively perform error correction are unnecessary. That is, before multiplication by the Galois field element α ⁱ , one R
It is sufficient if the S encoder 72 corrects the error. Also, since the dummy data multiplexed in the dummy data multiplexer 71 is known, the receiving side can identify the element α ⁱ of the multiplied Galois field by looking at the dummy data part. In particular, when the Galois field element α ⁰ (= 1) is used as dummy data, the data in the dummy data portion is the value of the multiplied Galois field element α ⁱ .

The block data multiplied by the j types of Galois field α ⁱ are stored in the 1-block memory 74a, respectively, and are input to the j types | DSV | calculator / comparator 75. In the j type | DSV | operation / comparator 75, the j type block data multiplied by the j type Galois field is | D
SV | is compared with each other, and block data having the smallest absolute value is selected. Here, the absolute value to be compared may be, for example, the value in the last bit of the data block multiplied by the Galois field, or the absolute value of the maximum amplitude in the data block multiplied by the Galois field. This point has been described in detail in the above-described first embodiment and the like, and thus the description thereof will be omitted. Also, j type | DSV
The configuration of the arithmetic / comparator 75 has also been described in detail in the above-described first embodiment and the like, so the description thereof will be omitted.

When the block data (block data multiplied by the Galois field α ⁱ ) that minimizes | DSV | is selected, information indicating the selection result is sent to the selector 76. The selector 76 stores the block data (after the Galois field multiplication |
Read the block data with the smallest DSV |
Input to the L modulator 77. As a result, the RLL modulator 77
The RLL modulation is performed in NRZI modulation, and then the NRZI modulator 78 performs NRZI modulation. RLL modulator 77 and NRZ
The configuration and function of the I modulator 78 have been described in detail in the above-described first embodiment and the like, and thus the description thereof will be omitted.

4-6. Eleventh Embodiment (Modulator Embodiment: FIG. 2)
4) The eleventh embodiment is a circuit configured to reduce the number of block memories. That is, in the tenth embodiment described above, since the data blocks multiplied by j types of Galois fields are stored in the 1-block memory 74a, the block memory 74a as a whole needs a capacity of j blocks. In view of this, in the eleventh embodiment, RS
By storing the data after adding the code in the one block memory 74b, the required capacity of the one block memory 74b is set to one block. In the following description, the description of the same parts as those in the tenth embodiment will be simplified.

Dummy data multiplexer 71 and RS encoder 72
Is similar to the tenth embodiment. The j-type Galois field multiplier 73a multiplies the data after the addition of the RS code by the j-type Galois field multipliers to generate j-type block data. These j types of block data are j types | DS
V | Comparison with the operation / comparator 75, | DSV |
The block data that minimizes is detected. That is, the Galois field (= Galois field to be multiplied) corresponding to this block data is selected. This selection result is Galois field multiplier 73
sent to b.

When the selection result is input, the Galois field multiplier 73b multiplies the Galois field having the minimum | DSV | by the data read from the one-block memory 74b (= data after the addition of the RS code). . After that, RLL modulation is performed by the RLL modulator 77, and then NRZ is performed by the NRZI modulator 78.
It is ZI-modulated and output.

4-7. Twelfth Embodiment (Embodiment of Demodulator: FIG. 2)
5) FIG. 25 is a circuit that demodulates data configured as shown in the lower part of FIG. 22 by being modulated by the modulator of FIG. 23 or 24.

The data input to this demodulator is first N
The RZI demodulator 81 performs NRZI demodulation, and then the RLL demodulator 82 performs RLL demodulation. The RS decoder 83 performs error correction on the RLL-demodulated data.

Next, from the error-corrected data, the Galois field detector 84 detects the Galois field multiplied by the modulator shown in FIG. 23 or 24, and the detected Galois field is
It is sent to the Galois field divider 85.

The Galois field divider 85 divides the data input from the RS decoder 83 by the Galois field input from the Galois field detector 84. As a result, the data is returned to the original description method data (data having the configuration shown in the upper part of FIG. 22).

[0134]

According to the present invention, R is used as the error correction code.
When the S code is used, by multiplying the element of the Galois field instead of converting the data by the modulation table, even if the modulation circuit has only one error correction circuit, the same error correction as the original data is performed. The ability can be given to the multiplication Galois field information. Therefore, highly reliable data transmission can be realized with small hardware.

[Brief description of drawings]

FIG. 1 is a block diagram of a digital modulation circuit that is a first embodiment of the present invention.

FIG. 2 is a block diagram of a digital modulation circuit that is a second embodiment of the present invention.

FIG. 3 is a block diagram of a digital demodulation circuit that is a third embodiment of the present invention.

FIG. 4 is a block diagram showing a first modulation principle of the present invention.

FIG. 5 is a block diagram of a digital modulation circuit that is a fourth embodiment of the present invention.

FIG. 6 is a data configuration diagram showing a sequence of modulation scheme number data used in the fourth and fifth embodiments of the present invention for d = 1.

FIG. 7 is a block diagram of a digital modulation circuit that is a fifth embodiment of the present invention.

FIG. 8 is a data configuration diagram showing an arrangement of modulation scheme number data used in the fourth and fifth embodiments of the present invention for d = 2.

FIG. 9 shows a generator polynomial G of an error correction code and a parity check matrix H used in the fourth, fifth and sixth embodiments of the present invention.
(A) shows the case of d = 1, and (b) shows the case of d = 2.

FIG. 10 is a block diagram of a digital demodulation circuit that is a sixth embodiment of the present invention.

FIG. 11 is a block diagram showing a second modulation principle of the present invention.

FIG. 12 is an explanatory view showing a data format of the present invention, the upper part shows the data format in the first to sixth embodiments, and the lower part shows the data format in the seventh to ninth embodiments.

FIG. 13 is a block diagram of a digital modulation circuit that is a seventh embodiment of the present invention.

FIG. 14 is a block diagram of a digital modulation circuit that is an eighth embodiment of the present invention.

FIG. 15 is a block diagram of a digital demodulation circuit that is a ninth embodiment of the present invention.

FIG. 16 is an explanatory diagram showing an example of a Galois field GF (2 ³ ).

FIG. 17 is an explanatory diagram of multiplication and division of Galois field.

FIG. 18 is an explanatory diagram of a Reed-Solomon code.

FIG. 19 is an explanatory diagram showing a receiving polynomial of Reed-Solomon code.

FIG. 20 is an explanatory diagram showing a reception polynomial when an RS code and a Galois field element are multiplied.

FIG. 21 is a block diagram of a digital demodulation circuit that is a ninth embodiment of the present invention when multiplied by a Galois field.

FIG. 22 is an explanatory diagram showing a data format of the present invention, the upper part shows a data format before multiplication by a Galois field, and the lower part shows a data format after the Galois field multiplication in the tenth to eleventh embodiments. .

FIG. 23 is a block diagram of a digital modulation circuit that is a tenth embodiment of the present invention.

FIG. 24 is a block diagram of a digital modulation circuit that is an eleventh embodiment of the present invention.

FIG. 25 is a block diagram of a digital demodulation circuit that is a twelfth embodiment of the present invention.

Claims (10)

[Claims] 1. An m-type which converts an arbitrary n-bit (where n> m) array into an arbitrary m-bit array in a one-to-one correspondence.
Depending on the n modulation method, each m of the input digital data
In a digital modulation method in which m bits are code-modulated units and each m-bit is mn modulated into n-bit modulated data, a Galois field GF is added to the beginning of input block data composed of a predetermined number of code-modulated units. The non-zero arbitrary element of (2 ^m ) is multiplexed as dummy data, and the Reed-Solomon code calculated on the block data after the dummy data multiplexing is added to the block data to form an RS code added block. Multiple types of Galois field GF in the coded block
A plurality of types of block data are generated by multiplying the element of (2 ^m ), and the DC components of the respective modulated block data obtained by m-n modulating the plurality of types of block data are compared with each other; It is obtained by selecting the element of the Galois field GF (2 ^m ) corresponding to the modulation block data in which the absolute value of the DC component is small, and multiplying the element of the selected Galois field GF (2 ^m ) by the RS code added block. A digital modulation method in which modulated block data is generated by performing mn modulation on the generated block data. 2. The digital modulation according to claim 1, wherein the selection is based on specifying a modulation block data having a minimum absolute value of a cumulative value of a DC component at a final bit of the modulation block data. Method. 3. The digital modulation method according to claim 1, wherein the selection is based on specifying a modulation block data having a minimum absolute value of the maximum amplitude of the modulation block data. 4. An m-converting an arbitrary n-bit (where n> m) array is associated with the arbitrary m-bit array in a one-to-one correspondence.
Depending on the n modulation method, each m of the input digital data
In a digital modulation circuit that performs m-n modulation of m bits into n bits of modulation data with bits as code modulation units, a Galois field GF is placed at the beginning of input block data composed of a predetermined number of code modulation units. A multiplexing circuit that multiplexes an arbitrary non-zero element of (2 ^m ) as dummy data, and RS by calculating a Reed-Solomon code for the block data in which the dummy data is multiplexed by the multiplexing circuit and adding it to the block data. An RS encoding circuit forming a code addition block, and a plurality of types of Galois field GF in the RS code addition block
A Galois field multiplication circuit that generates a plurality of types of block data by multiplying an element of (2 ^m ), and a DC component of each modulated block data obtained by m-n modulating each of the plurality of types of block data. The calculating means for obtaining, the comparing means for mutually comparing the magnitudes of the absolute values of the DC components, and the Galois field GF corresponding to the modulation block data having the small absolute value of the DC component based on the comparison result by the comparing means. (2 ^m) and selecting means for selecting the original, said selected Galois field GF (2 ^m) of the basis of the RS code adding block data obtained by multiplying the block m-n modulation on modulation block data And a digital modulation circuit having: 5. The Galois field GF (2 ^m ) according to claim 4, wherein the selecting means corresponds to the modulation block data having the minimum absolute value of the cumulative value of the DC component at the final bit of the modulation block data. A digital modulation circuit that selects the source of. 6. The digital device according to claim 4, wherein the selection unit selects an element of a Galois field GF (2 ^m ) corresponding to the modulation block data having the smallest absolute value of the maximum amplitude of the modulation block data. Modulation circuit. 7. The modulating device according to claim 4, further comprising a memory that stores each of the plurality of types of block data obtained by the original multiplication of the plurality of types of Galois fields GF (2 ^m ). Is a digital modulation circuit for reading block data corresponding to an element of the Galois field GF (2 ^m ) selected by the selection means from the memory and performing mn modulation. 8. The Galois field GF according to claim 4, further comprising: a memory storing the RS code addition block; and RS code addition block data read from the memory, and selected by the selecting means.
A second Galois field multiplication circuit that generates a plurality of types of block data by multiplying by an element of (2 ^m ) and outputs the block data to the modulation means. 9. Demodulation corresponding to a predetermined number of code demodulation units by performing n−m demodulation on m bits (where n> m) of demodulation data using n bits of input digital data as a code demodulation unit. The block data is sequentially generated, the demodulation block data is error-corrected using the Reed-Solomon code added to the sequentially-generated demodulation block data, and the block is added to the head of the demodulation block data after the error correction. Galois field GF multiplied by the data
Detects (2 ^m) of the original, the demodulated block data after error correction, and generates the original block data by dividing by the original detected Galois GF (2 ^m), a digital demodulation method. 10. Each of n bits of input digital data is m bits as a code demodulation unit (where n> m).
A demodulation circuit that sequentially demodulates the demodulation data of n-m to generate demodulation block data corresponding to a predetermined number of code demodulation units; and Reed-Solomon added to the demodulation block data sequentially generated by the demodulation circuit. An RS circuit for error-correcting the demodulation block data using a code, and a Galois field GF obtained by multiplying the block data added to the head of the demodulation block data after error correction
Digital demodulation circuit having a detection circuit for detecting the original (2 ^m), the demodulation block data after error correction, and a divider circuit for dividing the original detected Galois field GF (2 ^m) by the detection circuit.