JPS58138143A - Error correcting device - Google Patents

Abstract

PURPOSE:To correct simply burst error under the error correction limit, by providing an error location detector for an error correcting device, detecting the error location from the state of a digital signal of frequency modulation directly and producing an error location designating signal. CONSTITUTION:A frequency-modulated signal is picked up at a magnetic head and applied to a demodulation circuit 31 from a signal input terminal 2a, a digital signal, e.g., (010010), representing the code vector as an output of the circuit 31 is applied to a signal storage circuit 32 and a syndrome generating circuit 1, and a signal readout pulse is applied to a signal error location detecting circuit 33 from the circuit 31. The circuit 33 retrieves the disturbance of the state of signal readout pulse (e.g., fig. C) by using a clock pulse and detects the location having signal error caused due to dropout of signals caused by adhesion of dusts and jitter of the running system.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an error correction device suitable for correcting burst errors in a frequency-modulated signal, for example, and particularly for efficiently correcting burst errors of a predetermined length or less with a simple configuration. I made it possible.

In general, the encoding method and decoding method related to an error correction device for correcting signal errors in a received signal whose error correction code is composed of a cyclic code are as follows.

The coding method divides a series of information bits into bits, assigns the first component of an n-bit code vector as the information bit, uses the remaining n- components as test points, and places higher-order coefficients ahead in time. and process them sequentially. That is, the polynomial representation of the information point is expressed as X''-kfo(K) (where fo
(X3 is a polynomial of degree 1 or lower, and each coefficient is the We number of each information point), and the polynomial representation of the inspection point r(a)(
However, when r(X) is a polynomial of degree -1 or less in n-, and each coefficient is the symbol of each inspection point), then the sign of the remainder when Xrfo(a) is divided by the generator polynomial go( is changed to r(a) so that an error correction code, which is a redundant bit, is sent following the information waste.

This coding method is a simple one in which an error correction code is calculated by a division circuit that divides information bits by a generator polynomial goO and is added as redundant bits.

Next, in the decoding method, the transmission sequence U(a) is transmitted, and u(xH
-E(3) (E(X) is the error sequence) is the received sequence ■(3)
Consider the case where it is obtained as If the transmission sequence U(3) is received without reliability, it is divisible by the generator polynomial GOO because redundant bits are added as described above. While it is a trench,
If the received sequence V(a), ■(a) - U(x) + E(3) with error polynomial E(l) is used as the received signal, then the received sequence ■(3) is generated by the generating polynomial G( When dividing by 3), a remainder I(z(a) is obtained.And Re(a) of and corresponds to the syndrome S(a) of the received sequence, so it is possible to detect an error by determining syndrome 5(3), or to detect the syndrome. It is known that it is possible to correct errors by finding an erroneous sequence E(a) corresponding to S(a).

Conventionally, for example, CRCC (
The cyclic redundancy check code) is a binary cyclic code that uses a primitive polynomial as the generator polynomial in the Galois field GF (2m), and is the most frequently used cyclic code, and single errors can be corrected. It is known. An example of error correction is a CRC with code length n = 7 and information bit length k = 4 derived from a third-order irreducible polynomial, G(X) = X" + X + 1.
Consider C. Transmission sequence by generator polynomial QOO (J(a) is u(x)-(X"+X)・G(X),-X'+X"+X
2 + This shows that an error has occurred in the term X4, and it becomes possible to correct one bit. That is, Ward 0) =
If the syndrome S(a) is simply added to the received sequence (7 sections) as V(a) + In a Galois field (a field with a finite number of elements), assertions using cyclic groups and vector representations are often used, but for example, the correspondence between the representation using cyclic groups and the vector representation of mod (X" +X+ 1 ) 't' is ' For reference, the following table is shown in Table 1.

-\5, Table 1 Such simple error correction is performed by dividing the received sequence (2) by a predetermined generator polynomial, e.g. This is done via a syndrome generating circuit (1) such as the following. In this syndrome generation circuit (1), the signal from the received signal input terminal (2a) is supplied to one input terminal of the exclusive OR circuit (2), and the output signal of the exclusive OR circuit (2) is is supplied to the D input terminal of the D-free lag frog circuit (3), and the signal from the Q output terminal of the D-free lag frog circuit (3) is supplied to the - input terminal of the exclusive OR circuit (4). , the signal of the output terminal of the exclusive OR circuit (4) is
Supplied to the D input terminal of the flip-flop circuit (5),
The signal at the Q output terminal of the flip-flop circuit (5) is supplied to the D input terminal of the D flip-flop circuit (6), and the signal at the Q output terminal of the D flip-flop circuit (6) is supplied to the output terminal (7). It is also supplied to the other input terminal of the exclusive OR circuit (2+ (4) to apply feedback. Also, the clock/2 pulse input terminal (
The clock pulse signal obtained in 8) is supplied to the clock/9 pulse input terminals Cp of the D flip-flop circuits (3), (5), and (61).

For example, in this syndrome generation circuit (1), reception (
'ii No. L Te U(x)-X3(x3+x2+1)
, if (1101000) is input in vector representation, at the first time O, I
) Flip-flop circuit (33(5) Assuming that the content of (6) is 0'', compare the process of division by the Ken arithmetic shown in Figure 2 with the process of content change of the D Frituno-Florano circuit after time 3 shown in Table 2. However, the left digit in Figure 2 corresponds to the D flip-flop circuit located on the right in Table 2, which corresponds to a higher order coefficient. The coefficient corresponds to the first non-zero output, and that output also corresponds to the coefficient of the highest order X3 of the quotient.A3 in the division table.
．． A4. The polynomials marked with ... are at times 3, 4, and so on.・・・
D flip-flow 21 circuits (3) (5) (6
In addition to the contents of 1, B3. B4. The polynomials marked with . . . correspond to Z and feedback at times 3, 4, . . . and correspond to subtraction when the quotient is set.

Also, C3 * C4, . . . are times 3, 4, . ..., the coefficients of quotient X3, X2゜X, 1 are at times 4 and 5.
, 6.7. The contents of the D flip Flora 1 circuits (3), (5), and (6) at time 7 correspond to the remainder of this division, that is, the syndrome. In this way, division of any n-dimensional polynomial by the r-dimensional polynomial 'fjj2〇(X) is performed using a one-stage linear feedback shift register (G
(with feedback corresponding to the coefficient of X)) is known to be easily executed by shifting n times.

In the above example, we have described a division circuit for division by a low-order polynomial, but if necessary, we can use another example, for example, when using G(a)-X16+X15+X2+1 as the generator polynomial GOO, we can easily solve the simple error problem in the same way. This makes it possible to realize an error correction device.

Also, if an OR circuit is provided as a discrimination circuit, this CRCC
It is well known that 100 burst errors (concentrated errors) of a given code length can be detected with a simple configuration using There is a false detection device. In FIG. 3, parts corresponding to those in FIG. 1 are denoted by the same reference numerals (17), and detailed explanation thereof will be omitted.

In FIG. 3, (9) indicates an input terminal for a check word enable signal to which only bits in a predetermined interval are input. In addition, (+o), (II), ..., (two indicate the D flip-flop circuit 1 circuit as a register provided corresponding to the higher-order coefficients, respectively, and the shift and exclusion at a predetermined position. Shivor circuit (2G) (27) (28)
operates as a linear feedback shift register and inputs the input signal to the irreducible generator polynomial q) -X16+X15+
Make sure to divide by X2+1. Further, (2gl is an AND circuit which inputs the output signal of the exclusive OR circuit (2) and the check word enable signal, and outputs the r-) signal of the linear feedback shift register. In this example as well, it is possible to obtain the coefficient "1# or 0# for each order of syndrome 5 (3) from the Q output terminal of each D frig float circuit at a predetermined time, so the OR circuit (
If there is a remainder Re(a), i.e., syndrome 8) at the end of the division, the output terminal (30
Since 1# is obtained in a), error detection becomes the turning point.

However, for burst errors, 7 is 1%, - even if you use CRCC to generate syndromes in the same way as error correction, 11 will still be parsed! I know that it is difficult to correct mistakes. 1.11 For example, in the example of the simple correction mentioned above and the code length n-7 derived from the cubic irreducible polynomial formula given above, the CRC of = 4 for the information bits.
Consider the case where C is used. With transmission sequence UoC) and 1~,
Although UOO=Xb×X3+X2+X was transmitted, the 2-bit VC of the X4 term and the X term
If the received sequence is (A) = X6 + X4 + X3 + X2, then the syndrome S (I) becomes 5 ( ) does not match the error polynomial E(a) and its t
This is because it is not possible to correct errors by adding them.

Although it is known that arithmetic processing can be performed using CRCC with a simple device, there are many devices that can correct general errors using CFtCC alone, but other methods such as crossword code, cross interleaving, etc. Since codes and the like were combined with CRCC to form a device, two types of codes had to be used, making the structure of the error correction device complicated and the correction efficiency poor.

SUMMARY OF THE INVENTION In view of this, it is an object of the present invention to provide an error correction device that can efficiently correct first-to-first errors of a predetermined length or less with a simple configuration.

An embodiment of the present invention will be described below with reference to FIG. In FIG. 4, parts corresponding to those in FIGS. 1 to 3 are designated by the same reference numerals, and detailed explanation thereof will be omitted.

This embodiment concerns a case where a digital signal using CRCC, which means a code vector, is frequency modulated and recorded on a recording medium, and then signal errors are corrected in the reproduction system. This recording signal is a type of unipolar/IP pulse in a recording system, and is made so that it maintains a value of, for example, "1" throughout the bit digit interval and does not return to "0" within that interval. Non-return to zero (NR')
Z ) Faith! (Figure 5A), the bit cell width is T
0'' is represented by the width T and B is represented by the width, and the signal is recorded by frequency modulation 1~ (Fig. 5B). This frequency modulated signal is picked up by a magnetic head and sent to the signal input terminal ( 2a) is supplied to the demodulation circuit/31), and a digital signal, for example (010010) representing a code vector as the output of the demodulation circuit c31) is supplied to the signal storage circuit (3) and is also supplied to the syndrome generation circuit (1). Then, the /4ip1 circuit C31) supplies the signal read/cells to the signal error position detection circuit (c).

This signal error position detection circuit (G) uses the clock and bus pulses to read out the signal and searches for disturbances in the signal state of the 1,000 pulses (for example, C in Figure 5), and detects, for example, signal dropouts caused by the build-up of wires. It is assumed that the position where a signal error occurs due to jitter in the running system is detected. In the case of the signal shown in FIG. 5C, the readout/9th pulse signal is not obtained at a predetermined interval and contains irregular sections, so the error is slightly wider within the error correction limit. The section a is taken, and an error position designation signal is generated that designates the error position by bit position. Here, even if the error position is specified a little wider as the interval a where there is a possibility of an error, the coefficient of the corresponding error polynomial E(X) is O for the bits in this interval where the signal is correctly received. Therefore, there is no problem. In addition, this syndrome generation circuit (1) is a linear feedback shift register that sequentially divides a code vector by a predetermined irreducible polynomial and leaves the remainder in a register, so it extracts the output signal of each shift register at a predetermined time. In this way, syndrome S(a) is caused to occur.

Note that when it is defined to represent a syndromic remainder, it can be defined as S(a)=Be[:te[], where EOO is the error polynomial and G(X) is the generator polynomial. This syndrome generation circuit (
The syndrome S (a) generated in step 1) and the error position designation signal obtained by the error position detection circuit (to) are supplied to the error pattern generation circuit G4). This error pattern generation circuit (1
In step 34), an error pattern for canceling signal errors is generally generated as follows.

The polynomial Ei (X
) and the polynomial Bp(a) generated at the inspection point. First, E
In the case of (3) = EpcPO, therefore, burst errors can be solved by simply adding syndrome 5 (3) to the received sequence ■ (a), leaving the bit position of syndrome S (a) unchanged and converting it to the corresponding digital signal. By adding it to , the burst error will be canceled out and corrected.

Next, the error is detected by the error position designation signal E 00 = 1'
If it is specified that the i-bit cyclic shift is performed toward a higher order instead of 3p(3), the error polynomial E' ward) is
Since it can be expressed as E'(3)=XiE(X), the syndrome for E(X) is S(a). Then, 8 wards) ■= Re [- pieces] (However, Q(a) is the quotient ) and the syndrome S'(3) of tB F) and E'(3)=xiE(a) can be expressed as G(a). Here, X1S(3) is the syndrome SOO of F4) cyclically shifted by i bits.

Therefore, the syndrome S obtained by the syndrome generation circuit (1) and supplied to the error pattern generation circuit 04)
All you have to do is shift the flash to the left. That is, when the error position designation signal specifies that the burst error starts from the first-order term, the error pattern is generated by shifting once.

Here, the generating polynomial 〇@) = X3+ Let's explain the generation of.

First, the syndrome S(a) is , and it is known that the error starts from the third-order term due to the erroneous position designation signal, so we can convert this syndrome S(a) to a lower-order term modulo q(3). If the data is shifted three times, the contents of the corresponding D flip-flop circuit as a register will be shifted as shown in Table 3 for each shift. Therefore, after shifting three times, the content of the syndrome becomes (111), and the error polynomial F3(X) is required to be E(3)=X3(X2+X+1).

Table 3 The false turn generated in this way is stored in the signal storage circuit (
The transmission sequence U〆) which is supplied to the corresponding bit position of the digital signal stored in three locations is calculated as: After correcting the error in the received sequence U〆), the signal is supplied to the digital information signal output terminal (32a).

Since the present embodiment is configured in this manner, a signal in which the error correction code is composed of a cyclic code CACC and such digital information is frequency-modulated and recorded is picked up by the magnetic head and supplied to the signal input terminal (2a). Then, the signal is supplied to the signal storage circuit (three) via the demodulation circuit (61) and stored therein, and the signal is also supplied to the syndrome generation circuit (
1) and is divided by a predetermined irreducible generator polynomial to obtain the syndrome S(a) as the remainder. Also,
The digital information represented by the readout signal from the demodulation circuit (31) is supplied to the erroneous position detection circuit (c), and the incorrect υ position is detected due to the omission or disturbance of the readout signal and the error is slightly wider. An error position designation signal having interval a is output, and this error position designation signal is supplied to the error shift/main turn generation circuit G4). In addition, the syndrome S (a) generated in the -casindrome generation circuit (1) is also supplied to this error/mother turn generation circuit (34), and the lowest order of the tab specified by the error position designation signal -tqt is If is the i-th order, the syndrome 5 is generated by the number of bits i.
(K) is shifted and an error pattern A digital signal is supplied to the

As described above, according to this embodiment, unlike the conventional method, an error position detection device (c) is provided in the error correction device, and the error position is directly detected from the state of the received frequency-modulated digital signal. Since a designated signal is generated, a CRCC which can be easily constructed can be used as an error correction code for burst errors, and burst errors below the error correction limit can be easily corrected. If the degree of the generator polynomial is increased, the correction ability can be greatly increased, and if an irreducible generator polynomial is used, burst errors up to bits equal to the degree can be corrected. That is, for example, if we use () (a) -X16-1-
Burst errors of up to 6 bits can be easily corrected. Therefore, according to the invention, burst i! below a predetermined error correction limit! (It has the advantage of being able to efficiently correct errors with a simple configuration.

Further, in the above embodiment, a read pulse is used as a signal used for detecting an error position, but even if the signal is bias recorded, as shown in Figure 5, it is possible to detect signal omissions and deviations in the same way. , it can be easily understood that the same effects as in the above-mentioned embodiments can be obtained.

In addition, in the above embodiment, a configuration is adopted in which the signal error position is directly detected from the state of the signal recorded by frequency modulation. It would also be easy to be able to perform good error correction.

In addition, if the data transfer rate is slow, the microcomputer will generate a syndrome generation circuit (1), error #).
It is also easy to understand that a pattern generation circuit and a signal storage circuit can be configured.

It goes without saying that the present invention is not limited to the above-described embodiments, and that various other configurations can be taken without departing from the gist of the present invention.

[Brief explanation of drawings]

Fig. 1 is a system diagram of a conventional single error correction device, Fig. 2 is a diagram for explaining the correspondence between the operation of the division circuit of the conventional error correction device and the progress of division, and Fig. 3 is a diagram showing the correspondence between the operation of the division circuit of the conventional error correction device and the progress FIG. 4 is a system diagram showing an example of an error detection device using conventional CRCC.
FIG. 5 is a block diagram showing one embodiment of the 4-shi correction device, and is a diagram showing the station of the present invention. (1) is a syndrome generation circuit, 01) is a demodulation circuit, (
3 is a signal storage circuit, (C) is an error position detection circuit, G4
) is an error no. 2 turn generation circuit. JP-A-58-138143 (7)

Claims (1)

[Claims] means for storing a received signal whose error correction code is composed of a cyclic code; means for detecting the position of an error in the received signal; means for generating a syndrome related to the received signal; and correcting the error in the received signal. Error correction characterized by comprising means for generating an error pattern within a correction code length range from the error position of the received signal detected by the detection means and the syndrome for errors below a limit. Device.