JPH0923350A - Vertical synchronization detecting circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To correctly perform synchronous detection even for compressed data and user data. SOLUTION: Horizontal synchronization is detected by a horizontal synchronization detection pulse generation part 2 to count up an H counter 5, and a data killer and a horizontal synchronizing signal are generated. A vertical synchronization detection pulse is generated by a vertical synchronization detection pulse generation part 3; and when this pulse is detected twice in one horizontal period H and the low level and the high level are obtained in order by latching of the data killer, a clock is supplied to a vertical synchronization detecting counter 16 by the horizontal synchronizing signal. When the horizontal synchronizing signal is outputted in the period of the low level as the result of latching of the data killer, a reset signal is supplied by the horizontal synchronizing signal, and the vertical synchronizing signal is generated by a V counter counted up synchronously with the vertical synchronization detecting counter 16.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vertical sync detection circuit, and more particularly to an NTSC (National Television System Com).
vertical sync detection circuit for composite signals.

[0002]

2. Description of the Related Art FIG. 4 shows a conventional configuration for generating a vertical synchronizing signal from an NTSC composite signal (digital signal). 5 and 6 show the timing charts.

The detection of the synchronizing portion of the NTSC composite signal is generally carried out by detecting that the sync slice level or lower continues. Here, as the sync slice level value, in the case of the D2 format, since the pedestal level is h3C (h indicates hexadecimal display) and the sync chip level is h04, a value between them, particularly an intermediate value h20, etc., is used. It is also used.

During the video period, the color phase is superimposed in four cycle cycles (one cycle in four fields; the relationship between the horizontal synchronizing signal HD and the color subcarrier is called "SCH (SubCarier to Horizontal)"). It is unlikely that the sync slice level and below will continue continuously, and this is used to detect the synchronization part.

Here, when the data is regarded as horizontal synchronization when the sync slice level is 8 clocks or less, pulse output of 1 clock is performed, and this pulse output is used as a load signal of the H counter 5 (counter for counting one horizontal period). Via the load mask unit 4 using a half H killer signal (a signal for masking horizontal synchronization detected in 1 / 2H (H is one horizontal period) in the horizontal synchronization detection pulse generation unit 2) as a mask control signal. Supplied.

In the vertical synchronization, it is assumed that pulse output of 1 clock is performed at 120 clock continuous sync slice level or less.

Here, the value of 120 clocks will be described. In the case of D2 format, the horizontal synchronizing section is 67 clocks from addresses 785 to 851. Therefore, the number must be at least this higher.

At this time, how to distinguish between the ODD (odd number) field and the EVEN (even number) field becomes a problem. In ODD and EVEN, the vertical synchronization period is phased by half H (= 1 / 2H). The ODD and EVEN can be distinguished by using this.

The fact that the phase is shifted by half H means that the phase relationship of the half H killer signal is also shifted, and therefore the half H killer signal is generated by the vertical synchronization generation pulse output from the vertical synchronization detection pulse generator 3. Can also detect the phase relationship. However, to latch, half H
The killer signal requires both "H" and "L" phases.

The half H killer is applied during the entire data period when compressed data or user data is superimposed on the NTSC composite signal.

The addresses in the data period are 0 to 767, and
If the half H killer signal is "H" during that period and "L" during the other periods, the vertical synchronization generation pulse signal from the vertical synchronization detection pulse generation unit 3 is "H" or "L" of the half H killer signal. To latch ", the address 785
The vertical sync generation pulse must be output during the period from to (address past the color burst position) to address 909.

The address has 910 cycles from 0 to 909. Here, the phase of the vertical synchronization generation pulse output from the vertical synchronization detection time pulse generation section 3 is 905 immediately before the address 909.

As a result, the vertical sync generation pulse is output when the level of 120 consecutive sync slice levels from the address 785 to 905 continues.

Then, as shown in FIG. 4, the latch circuit 8 consisting of a D-type flip-flop latches the half H killer signal with the vertical synchronization generation pulse.

While the output of the latch circuit 8 is "H",
In the ODD field, the horizontal sync signal is applied (overlapped), but in the EVEN field, it is output in a phase not applied to the horizontal sync signal.

Therefore, if the horizontal synchronizing signal is output during the "L" period of the output of the latch circuit 8, the vertical synchronizing detection counter 16 is reset (RST) and is output during the "H" period of the output of the latch circuit 8. Vertical sync detection counter 16
By supplying as the clock signal (CLK) of
The vertical synchronization detection counter 16 is constantly reset in the EVEN field and becomes the ODD field to count up. In this case, since the count value of the vertical synchronization detection counter 16 need only be known at the time when the counter operates, the counter output "1" may be decoded and stopped at "2".

That is, the "1" detector 17 decodes the count value "1" of the vertical synchronization detection counter 16 and outputs the "1" detection result to the V counter 19, and the V counter 19 receives the decoded value "1". It becomes possible to output the vertical synchronizing signal output 21 to an arbitrary position by operating the. The vertical synchronizing signal output 21 is output once in one frame (= 2 fields).

FIG. 5 shows the EVEN field to the ODD.
The timing to get to the field is shown,
In the EVEN field, the vertical sync detection counter is reset to 0, the half H killer signal of 4H in the ODD field is latched by the vertical sync generation pulse, and the vertical sync detection counter 16 when the latch output is active is horizontal sync. When the signal is counted as a clock signal and "1" is output at 5H, the V counter load signal becomes active, and the output of the V counter starts counting up from "6" H. Then, the vertical synchronization detection counter 16
Inputs "2" after inputting horizontal sync signal at 5H
The output is held and the count operation is stopped. In FIG.
The timing diagram from the DD field to the EVEN field (265H) is shown.

[0019]

It can be said that the above-mentioned conventional vertical synchronizing circuit does not cause any problem with the normal NTSC composite signal. However,
For example, as shown in FIGS. 7 and 8, recently, NTSC
In addition to the video data, the compressed data, user data, etc. are often placed during the video data period.

In such a case, referring to FIG. 7, the EVE
EVEN from N field to ODD field
In m + 1H, which is the video data period of the field,
The half sync killer signal is activated by the compressed data and the user data, the output of the latch circuit 8 is set to "H" by the vertical sync generation pulse, and then the vertical sync is held at the "H" level up to 3H of the ODD field. The detection counter 16 counts the horizontal synchronizing signal as a clock signal, and outputs “1” at m + 2H,
The V counter load signal becomes "L" level, and the output of the V counter 19 starts counting up from "6" H. The vertical synchronization detection counter 16 clocks in the horizontal synchronization signal at m + 3H, outputs "2", and stops the counting operation. That is, referring to FIG. 7, when a predetermined number of data equal to or less than the sync detection level continuously appear in the video data, the load signal of the V counter becomes active and the count operation is erroneously started. The timing diagram of FIG. 8 is a continuation of FIG.
It is illustrated from the ODD field to the EVEN field.

In such a case, there is a problem in that there is a pattern that is detected as being synchronized even during the video data period, and synchronization error detection frequently occurs.

[0022]

To achieve the above object, the present invention provides a means for generating a horizontal sync detection pulse signal at the time of detecting horizontal sync with respect to an input NTSC composite signal, and a vertical sync at the time of vertical sync detection. A unit for generating a detection pulse signal, a unit for masking the horizontal synchronization detection pulse signal with an input killer signal, and an H counter for counting the horizontal synchronization detection pulse signal obtained without being masked by the masking unit as a load signal. Means and
Killer generation means for generating the killer signal from the output of the H counter, horizontal synchronization signal generation means for generating a horizontal synchronization signal from the output of the H counter, and the killer signal sampled with the vertical synchronization detection pulse signal 2 The phases of two consecutive outputs are in a predetermined relationship, and when the vertical synchronization detection pulse signal is generated twice within one horizontal period, the horizontal synchronization signal output from the horizontal synchronization signal generating means causes vertical And a means for controlling the synchronization detection counter so as to supply a clock thereto, and a vertical synchronization signal is generated through a V counter by the count output of the vertical synchronization detection counter. .

The present invention is preferably input NTS
A means for generating a horizontal sync detection pulse signal at the time of horizontal sync detection for the C composite signal, a means for generating a vertical sync detection pulse signal at the time of vertical sync detection, and a data killer for masking the horizontal sync detection pulse signal during a data period. Means for masking with a signal, H counter means for counting a horizontal sync detection pulse signal obtained without masking from the mask means as a load signal, and each means for generating a data killer signal and a horizontal sync signal from the H counter A first detecting means for detecting that the vertical synchronization detection pulse signal is generated twice within one horizontal period (referred to as “condition 1”); and the data killer signal is latched by the vertical synchronization detection pulse signal. And a first latching means for latching and shifting the first latching means with the vertical synchronization detection pulse. A second latch means that, the first,
Based on the second detection means for detecting that the output of the second latch means is logic "1" and logic "0" (referred to as "condition 2") and the outputs of the first and second detection means. Under the conditions 1 and 2, means for supplying a clock to the vertical synchronization detection counter with a horizontal synchronization signal, and the horizontal synchronization signal for detecting the vertical synchronization signal while the output of the first latch means is a logical "0" period. Means for supplying to the reset of the counter, and V is provided by the count output of the vertical synchronization detection counter.
Provided is a vertical synchronization detection circuit characterized by generating a vertical synchronization signal via a counter.

According to the present invention, it is possible to correctly output the vertical synchronizing signal in any case where the compressed data, the user data and the like are superimposed in the video data period of the NTSC composite signal.

[0025]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows the configuration of a vertical sync detection circuit according to an embodiment of the present invention.

The NTSC composite input 1 is supplied to a horizontal sync detection pulse generator 2 and a vertical sync detection pulse generator 3.

The pulse output generated by the horizontal sync detection pulse generator 2 at the time of horizontal sync detection is supplied as a load signal for the H counter 5 through the load mask unit 4 for masking the load signal.

The output of the H counter 5 is input to the data killer generator 6, and the data killer generator 6 is a data killer for masking the load signal of the H counter 5 during the data period (for example, addresses 0 to 767). A signal is output, and the data killer signal is supplied as a mask control signal by the load mask unit 4 to mask the load signal in the data phase input to the load terminal of the H counter 5. Then, the output of the H counter 5 is input to the horizontal synchronization generator 7 and the horizontal synchronization signal is generated.

The data killer signal output from the data killer generation unit 6 is firstly output by the pulse (also referred to as "vertical synchronization generation pulse output") output during vertical synchronization detection by the vertical synchronization detection pulse generation unit 3. Register 8 and the output of the first register 8 is latched and shifted by the second register 9.

The output of the first register 8 and the inverted output of the second register 9 are input to the AND circuit 10 and AN
D (logical product) is obtained, and it is detected that the outputs of the first and second registers 8 and 9 are "H" and "L" level outputs (that is, the output of the AND circuit 10 is "H"). This occurs when the outputs of the first and second registers 8 and 9 are "H" and "L" levels, respectively.

The pulse output of the vertical sync detection pulse generator 3 is the second vertical sync pulse output unit 1 in 1H.
The horizontal sync signal supplied to the second horizontal sync generator 7 is also supplied to the second vertical sync generator pulse output unit 12 in 1H as a reset (RST).

Second time vertical sync generation pulse output section 1 within 1H
2 is reset to "0" by the horizontal synchronization signal and performs an operation of counting up to "1" or "2" by the output of the vertical synchronization generation pulse.

Second vertical sync generation pulse output unit 1 within 1H
The output of 2 is input to the J input terminal of the JK flip-flop 14, and the horizontal synchronizing signal is inverted via the inverter 13 and input to the K input terminal. When the output of the second vertical synchronization generation pulse output unit 12 within 1H becomes "2", "H" is input to the J input terminal of the JK flip-flop 14, and the JK flip-flop 14 detects the second vertical synchronization within 1H. "H" is output during the period from the detection of the time generation pulse to the next horizontal synchronizing signal.

The output of the JK flip-flop 14 and AN
The output of the D circuit 10 and the inverted output of the horizontal synchronization signal from the inverter 13 are input to the 3-input AND circuit 15, and the output of the 3-input AND circuit 15 is the vertical synchronization detection counter 16.
Is supplied as a clock signal (CLK).

Further, the output of the first register 8 and the horizontal synchronization signal output from the horizontal synchronization generator 7 are connected to the OR circuit 1
1 and the logical sum output of these is supplied to the vertical synchronization detection counter 16 as a reset (RST).

The output of the vertical sync detection counter 16 is
The respective values are detected by the “1” detector 17 and the “2” detector 18.

When it is detected that the output of the vertical sync detection counter 16 is "2", the "2" detector 1
8 is an enable signal EN of the vertical synchronization detection counter 16.
Is made inactive, and the vertical synchronization detection counter 16 stops its operation until reset is entered.

The output of the vertical sync detection counter 16 is "1".
Is detected, the output of the "1" detector 17 becomes the load signal of the V counter 19, and thereafter the V counter 1
9 is operated, the vertical synchronization signal is generated in the vertical synchronization generator 20 at an arbitrary position, and the vertical synchronization signal output 21 is output.

The specific operation of this embodiment will be described below with reference to FIGS. 2 and 3.

The vertical sync portion of the NTSC composite signal is detected at 120 here, as shown in the above-mentioned conventional example.
It is performed below the clock continuous sync slice level.

The problem in the above-mentioned conventional example is that the vertical synchronization detection counter 1 is activated when synchronization is erroneously detected during the data period.
This is the case where the clock is supplied to 6.

In the present embodiment, the supply of the clock to the vertical sync detection counter 16 is permitted because the vertical sync detection pulse output section 3 outputs two vertical sync generation pulse outputs within 1H. This is only when "L" is output at the first time and "H" is output at the second time when the data killer signal is latched by the synchronization detection pulse signal.

The present embodiment has a circuit configuration that detects these two conditions and controls the clock supply to the vertical synchronization detection counter 16. As a result, no matter what signal is superimposed on the video data period of the NTSC composite signal, the vertical sync signal can be correctly separated in the same manner as the NTSC signal itself.

First, the first register 8 that latches the data killer signal with the vertical sync detection pulse signal, the second register 9 that shifts the first register 8, the output of the first register 8 and the second register. AND circuit 10 for ANDing with the inverted output of 9 is further provided, and the vertical synchronization detection generation pulse is detected twice within 1H to generate a gate signal indicating the period from the second time to the next horizontal synchronization signal. It has a circuit configuration.

By combining these two circuit configurations with the conventional circuit configuration and supplying the clock to the vertical synchronization detection counter 16 only when the above condition is satisfied, the vertical synchronization detection pulse signal is erroneously output during the video data period. However, even if this is masked, it is not supplied to the clock of the vertical synchronization detection counter 16 and the vertical synchronization signal synchronized with the input can be output.

Referring to FIG. 2, the timing from the EVEN field to the ODD field is shown, and when the data killer signal is made "L" and "H" at 4H of the ODD field, the AND circuit 10 is shown. Becomes "H", the JK flip-flop 14 becomes "H" level when the vertical sync generation pulse is output twice within 1H, the clock is supplied from the 3-input AND circuit 15, and the vertical sync detection counter 16 becomes When the horizontal synchronizing signal is counted as a clock signal and "1" is output at 5H, the V counter load signal becomes "L" level, and the output of the V counter starts counting up from "6" H and operates correctly. To do. Then, the vertical synchronization detection counter 16 is 5
At H, the horizontal synchronizing signal is clocked in and the output of "2" is held and the counting operation is stopped. In Figure 3, ODD
A timing diagram from field to EVEN field (265H) is shown.

Further, according to the present embodiment, even when the data equal to or lower than the sync detection level continues due to the data superposed in n + 1H of the EVEN field and the like, within the data period, unlike the conventional example, V The problem that the load signal of the counter becomes active, the count-up operation is performed, the normal phase relationship is broken, and the vertical synchronization is disturbed is completely solved.

[0049]

As described above, according to the present invention,
The vertical sync detection signal can be correctly output in any case where compressed data, user data, or the like is superimposed on the video data period of the NTSC composite signal.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a timing diagram illustrating an operation of the exemplary embodiment of the present invention.

FIG. 3 is a timing diagram illustrating an operation of the exemplary embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a conventional vertical synchronizing circuit.

FIG. 5 is a first timing diagram showing a conventional positive operation.

FIG. 6 is a second timing diagram showing a conventional positive operation.

FIG. 7 is a first timing diagram showing a conventional malfunction.

FIG. 8 is a second timing chart showing a conventional malfunction.

[Explanation of symbols]

 1 NTSC composite input section 2 Horizontal sync detection pulse generation section 3 Vertical sync detection pulse generation section 4 Load mask section 5 H counter section 6 Data killer generation section 7 Horizontal synchronization generation section 8 Register (latch circuit) 9 register (latch circuit) ) 10 AND circuit 11 OR circuit 12 1H second-time vertical sync generation pulse output section 13 Inverter section 14 JK flip-flop 15 3 input AND circuit 16 Vertical sync detection counter section 17 “1” detector (decode section) 18 “2” Detector (decoding section) 19 V counter section 20 Vertical synchronization generation section 21 Vertical synchronization signal output section

Claims (3)

[Claims] 1. A means for generating a horizontal sync detection pulse signal at the time of detecting horizontal sync with respect to an input NTSC composite signal, a means for generating a vertical sync detection pulse signal at the time of vertical sync detection, and the horizontal sync detection pulse signal. For masking with the input killer signal, H counter means for counting the horizontal synchronization detection pulse signal obtained without being masked by the mask means as a load signal, and generating the killer signal from the output of the H counter. Killer generating means, horizontal synchronizing signal generating means for generating a horizontal synchronizing signal from the output of the H counter, and phases of two consecutive outputs obtained by sampling the killer signal with the vertical synchronizing detection pulse signal have a predetermined relationship. Yes, when the vertical synchronization detection pulse signal is generated twice within one horizontal period, the water Means for controlling the vertical synchronization detection counter to supply a clock with the horizontal synchronization signal output from the synchronization signal generation means, and the vertical synchronization signal is output via the V counter by the count output of the vertical synchronization detection counter. A vertical synchronization detection circuit characterized by generating. 2. The killer signal is supplied to a reset signal of the vertical synchronization detection counter when the horizontal synchronization signal is input when the sampling signal of the vertical synchronization detection pulse signal is in the inactive state. 2. The vertical sync detection circuit according to claim 1, wherein 3. A means for generating a horizontal sync detection pulse signal at the time of detecting horizontal sync with respect to an input NTSC composite signal, a means for generating a vertical sync detection pulse signal at the time of vertical sync detection, and the horizontal sync detection pulse signal. A data killer signal for masking during the data period, an H counter means for counting a horizontal synchronization detection pulse signal obtained without masking from the masking means as a load signal, a data killer signal from the H counter, Each means for generating a horizontal synchronization signal, first detection means for detecting that the vertical synchronization detection pulse signal is generated twice within one horizontal period (referred to as "condition 1"), and the vertical synchronization detection pulse A first latching means for latching the data killer signal by a signal; Second latch means for latching and shifting with a sync detection pulse, and detecting that outputs of the first and second latch means are logic "1" and logic "0" (referred to as "condition 2") Second
And the condition 1 based on the outputs of the first and second detecting means.
And condition 2, the means for supplying a clock to the vertical synchronization detection counter by the horizontal synchronization signal, and the horizontal synchronization signal for resetting the vertical synchronization detection counter while the output of the first latch means is a logical "0" period. A vertical synchronization detection circuit comprising: a means for supplying; and a vertical synchronization signal generated via a V counter by the count output of the vertical synchronization detection counter.