JPH09148379A - Formation of salient electrode - Google Patents
Formation of salient electrodeInfo
- Publication number
- JPH09148379A JPH09148379A JP7329546A JP32954695A JPH09148379A JP H09148379 A JPH09148379 A JP H09148379A JP 7329546 A JP7329546 A JP 7329546A JP 32954695 A JP32954695 A JP 32954695A JP H09148379 A JPH09148379 A JP H09148379A
- Authority
- JP
- Japan
- Prior art keywords
- paste film
- conductor
- metal paste
- forming
- metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体素子又は回路基
板等の基体上に突起電極即ちバンプ電極を形成する方法
に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a bump electrode or a bump electrode on a substrate such as a semiconductor element or a circuit board.
【０００２】[0002]
【従来の技術】フェイスダウンボンディングするための
フリップチップのバンプ電極即ち突起電極の代表的な形
成方法として次の２つが知られている。 （１） 半導体基板の電極層の上に半田又は金を蒸着又
はメッキすることに依ってバンプ電極を形成する。 （２） ワイヤボンディング装置を使用してワイヤの先
端にボールを形成し、このボールを半導体基板の電極層
の上に押し当て、しかる後、ボールを残してワイヤを切
断し、ボールに基づいてバンプ電極を得る。2. Description of the Related Art The following two methods are known as typical methods for forming flip-chip bump electrodes, that is, bump electrodes for face-down bonding. (1) A bump electrode is formed by vapor-depositing or plating solder or gold on the electrode layer of the semiconductor substrate. (2) A ball is formed at the tip of the wire using a wire bonding device, the ball is pressed against the electrode layer of the semiconductor substrate, and then the wire is cut while leaving the ball, and bumps are formed based on the ball. Get the electrodes.
【０００３】[0003]
【発明が解決しようとする課題】ところで、上記（１）
の蒸着またはメッキにてバンプ電極を形成する方法は、
蒸着装置またはメッキ装置等の付帯設備が必要になり、
少量多品種のフリップチップの生産時には必然的にコス
ト高になった。また、上記（２）のワイヤボンディング
装置を使用してバンプ電極を形成する方法は、今迄多用
されていた既存のワイヤボンディング装置を使用してバ
ンプ電極を形成することができるので、付帯設備に要す
る費用を低減することができるという特長を有する反
面、１チップ当りのバンプ電極の数が少ない場合には、
典型的なワイヤボンディング方法で半導体素子を回路基
板に実装する方法に比べて実装まで含めた生産コストの
低減を図ることが困難又は不可能であるという問題点、
及びワイヤの太さによってバンプ電極の径が決定される
ので任意の径のバンプ電極を正確に得ることが困難であ
るという問題点を有する。However, the above (1)
The method of forming bump electrodes by vapor deposition or plating of
Additional equipment such as vapor deposition equipment or plating equipment is required,
The cost was inevitably high when producing a large number of small quantities of flip chips. In addition, the method (2) of forming a bump electrode by using the wire bonding apparatus can form the bump electrode by using an existing wire bonding apparatus that has been widely used until now. On the other hand, it has the feature that the cost required can be reduced, but when the number of bump electrodes per chip is small,
The problem that it is difficult or impossible to reduce the production cost including mounting as compared with the method of mounting a semiconductor element on a circuit board by a typical wire bonding method,
Also, since the diameter of the bump electrode is determined by the thickness of the wire, it is difficult to accurately obtain a bump electrode having an arbitrary diameter.
【０００４】そこで、本発明の目的は突起電極を高精度
且つ容易に得ることができる方法を提供することにあ
る。Therefore, an object of the present invention is to provide a method by which a protruding electrode can be easily obtained with high accuracy.
【０００５】[0005]
【課題を解決するための手段】上記目的を達成するため
の本発明は、基体の表面に導体層を形成する工程と、導
体粉末（金属単体の粉末又は合金粉末又は金属を主成分
とする粉末）と有機バインダーとを含む導体ペーストを
前記導体層の上に付着させて導体ペースト膜を形成する
工程と、前記導体ペ−スト膜又はこの前記導体ペースト
膜を乾燥させたものの選択された領域にレーザ光を投射
して前記有機バインダ−を燃焼飛散させ且つ前記導体粉
末を溶融凝集させる工程と、前記導体ペースト膜又はこ
の導体ペースト膜を乾燥させたものにおけるレーザ光が
投射されなかった領域を除去して前記導体層の上に前記
溶融凝集に基づく突起電極を生じさせる工程とから成る
突起電極形成方法に係わるものである。なお、請求項２
に示すように、基体を回路基板とすることができる。ま
た、請求項３に示すように基体を半導体基板とすること
ができる。The present invention for achieving the above object comprises a step of forming a conductor layer on the surface of a substrate, a conductor powder (a powder of a metal simple substance or an alloy powder or a powder containing a metal as a main component). ) And an organic binder are applied onto the conductor layer to form a conductor paste film, and the conductor paste film or a selected region of the conductor paste film dried. A step of projecting a laser beam to burn and scatter the organic binder and melt and agglomerate the conductor powder, and to remove a region where the laser beam is not projected in the conductor paste film or the conductor paste film dried. And forming a protruding electrode based on the melt aggregation on the conductor layer. Claim 2
The substrate may be a circuit board, as shown in FIG. Further, as described in claim 3, the base body can be a semiconductor substrate.
【０００６】[0006]
【発明の作用及び効果】各請求項の発明によればレーザ
光の選択的投射によって突起電極を形成するので、微細
な突起電極を高精度且つ容易に作ることができる。ま
た、レーザ光の投射面積の変更によって突起電極の大き
さを容易に変えることができる。請求項２の発明によれ
ば、回路基板側に突起電極を形成するので、突起電極を
持たない一般的な電子回路素子をフェイスダウンボンデ
ィングすることが可能になり、電子回路装置のコストの
低減を図ることができる。請求項３の発明によればフリ
ップチップを容易に得ることができる。According to the invention of each of the claims, since the projection electrode is formed by selectively projecting the laser beam, a fine projection electrode can be easily manufactured with high accuracy. Further, the size of the protruding electrode can be easily changed by changing the projected area of the laser beam. According to the second aspect of the present invention, since the protruding electrode is formed on the circuit board side, it is possible to perform face-down bonding of a general electronic circuit element having no protruding electrode, thereby reducing the cost of the electronic circuit device. Can be planned. According to the invention of claim 3, a flip chip can be easily obtained.
【０００７】[0007]
【第１の実施例】図１〜図４を参照して第１の実施例の
混成集積回路構成の電子回路装置の製造方法を説明す
る。フェイスダウンボンディングによって混成集積回路
装置を製作するために、まず、図１に示すようにセラミ
ックから成る回路基板１の上に接続導体層２を設けたも
のを用意する。この接続導体層２は、厚膜導体ペースト
を印刷して焼成すること、又は金属を蒸着又はメッキす
ること等によって形成する。次に、突起電極（バンプ電
極）の形成予定領域を含むように接続導体層２の上に導
電ペ−ストとして金属ペ−ストを塗布して金属ペースト
膜３を形成する。この金属ペーストは金（Ａｕ）、又は
銀（Ａｇ）、又は白金（Ｐｔ）、又は銅（Ｃｕ）等の金
属単体粉末、又はＡｕ−Ｓｎ合金粉末やＰｂ−Ｓｎ合金
粉末のような合金粉末、又はＡｕ−Ｓｉ、Ａｕ−Ｇｅの
ような金属を主成分とする金属−半導体混合物粉末と有
機バインダと溶剤とから成る。なお、金属ペースト膜３
は、印刷又は転写法によって形成する。First Embodiment A method of manufacturing an electronic circuit device having a hybrid integrated circuit configuration according to the first embodiment will be described with reference to FIGS. In order to manufacture a hybrid integrated circuit device by face-down bonding, first, as shown in FIG. 1, a circuit board 1 made of ceramics and provided with a connection conductor layer 2 is prepared. The connection conductor layer 2 is formed by printing a thick film conductor paste and firing it, or vapor-depositing or plating a metal. Next, a metal paste is applied as a conductive paste onto the connection conductor layer 2 so as to include a region where the bump electrode (bump electrode) is to be formed, to form a metal paste film 3. This metal paste is a powder of a simple metal such as gold (Au), silver (Ag), platinum (Pt), or copper (Cu), or an alloy powder such as Au-Sn alloy powder or Pb-Sn alloy powder, Alternatively, it is composed of a metal-semiconductor mixture powder containing a metal such as Au-Si or Au-Ge as a main component, an organic binder and a solvent. The metal paste film 3
Are formed by a printing or transfer method.
【０００８】次に、金属粉末の溶融凝集が起こる温度よ
りも低い温度に金属ペースト膜３を加熱することによっ
てこれを乾燥させ、溶剤を飛散即ち蒸発させる。Next, the metal paste film 3 is dried by heating it to a temperature lower than the temperature at which the melting and agglomeration of the metal powder occurs, and the solvent is scattered or evaporated.
【０００９】次に、図２に示すようにレーザ装置４から
レーザ光５を放射させ、このレーザ光５を金属ペースト
膜３の突起形成予定領域６に投射する。このレーザ光５
の強さは、この投射によって金属ペースト膜３のバイン
ダを燃焼飛散させ且つ金属粉末の溶融凝集を生じさせ且
つ接続導体層２に金属ペースト膜３の金属を溶融結合さ
せることができるレベルに設定する。Next, as shown in FIG. 2, a laser beam 5 is emitted from the laser device 4, and the laser beam 5 is projected onto the projection forming region 6 of the metal paste film 3. This laser light 5
Is set to such a level that this projection causes the binder of the metal paste film 3 to be burnt and scattered, the metal powder to be melted and agglomerated, and the metal of the metal paste film 3 to be melt-bonded to the connection conductor layer 2. .
【００１０】次に、金属ペースト膜３のレーザ光が投射
されなかった領域を溶剤を使用した超音波洗浄によって
除去し、図３に示す突起電極７のみを接続導体層２の上
に残存させる。この突起電極７は全体として卵形であっ
て、レーザ光５の投射による溶融凝集で形成されたもの
であり、下の接続導体層２に電気的及び機械的に結合さ
れている。なお、突起電極７の径は溶融凝集に基づいて
レーザ光５の投射領域の径よりも幾らか小さくなる。Next, the region of the metal paste film 3 where the laser beam is not projected is removed by ultrasonic cleaning using a solvent, and only the protruding electrode 7 shown in FIG. 3 remains on the connection conductor layer 2. The protruding electrode 7 has an oval shape as a whole, is formed by melting and agglomeration by the projection of the laser beam 5, and is electrically and mechanically coupled to the lower connecting conductor layer 2. The diameter of the bump electrode 7 is somewhat smaller than the diameter of the projection area of the laser beam 5 due to the melt aggregation.
【００１１】次に、図４に示すようにトランジスタ、ダ
イオード、ＩＣ等の半導体チップ８をフェイスダウン方
法で回路基板１の上に配置する。半導体チップ８はバン
プ電極を有するフリップチップではなく、主としてワイ
ヤボンディング実装のために作られた一般にベアチップ
と呼ばれているものであり、半導体基板９の一方の主面
にボンディングパッド即ち金属端子１０を設けたもので
ある。半導体チップ８はこの端子１０を回路基板１側の
突起電極７に当接させるように位置決めされる。しかる
後、熱圧着又は超音波ボンディング等によって半導体チ
ップ８の端子１０を突起電極７に接合させる。Next, as shown in FIG. 4, semiconductor chips 8 such as transistors, diodes and ICs are arranged on the circuit board 1 by a face down method. The semiconductor chip 8 is not a flip chip having bump electrodes, but is generally called a bare chip made mainly for wire bonding mounting, and a bonding pad, that is, a metal terminal 10 is provided on one main surface of the semiconductor substrate 9. It is provided. The semiconductor chip 8 is positioned so that the terminals 10 are brought into contact with the protruding electrodes 7 on the circuit board 1 side. Then, the terminals 10 of the semiconductor chip 8 are bonded to the protruding electrodes 7 by thermocompression bonding or ultrasonic bonding.
【００１２】この実施例は次の利点を有する。 （１） 金属ペースト膜３にレーザ光５を投射してバイ
ンダを飛散させ且つ金属粉末の溶融凝集を生じさせて突
起電極７を形成するので、所望の大きさの突起電極を正
確且つ容易に得ることができる。 （２） 回路基板１側に突起電極７を設けるので、突起
電極を有さない安価な半導体チップ８をフェイスダウン
ボンディングすることが可能になり、電子回路装置のコ
ストの低減が達成される。This embodiment has the following advantages: (1) Since the projection electrode 7 is formed by projecting the laser beam 5 onto the metal paste film 3 to scatter the binder and cause the metal powder to melt and agglomerate, a projection electrode having a desired size can be obtained accurately and easily. be able to. (2) Since the projecting electrodes 7 are provided on the circuit board 1 side, it is possible to face-down bond an inexpensive semiconductor chip 8 having no projecting electrodes, and the cost of the electronic circuit device can be reduced.
【００１３】[0013]
【第２の実施例】次に、図５〜図９に示す第２の実施例
の電子回路装置の製造方法を説明する。第２の実施例で
は突起電極を有する半導体素子即ちフリップチップを作
り、これを回路基板に実装することによって電子回路装
置を形成している。トランジスタ、ダイオード、ＩＣ等
のフリップチップを作るために、所定の半導体領域が形
成された半導体基体又は半導体基板としての半導体ウエ
ハ１１の一方の主面に図５及び図６に示すように金属導
体層１２を設け、更にこの導体層１２の上に金属ペース
トを印刷又は転写して金属ペースト膜１３を設ける。な
お、金属ペースト膜１３は図１の金属ペースト膜３と同
一のものである。[Second Embodiment] Next, a method of manufacturing an electronic circuit device according to a second embodiment shown in FIGS. In the second embodiment, a semiconductor element having a protruding electrode, that is, a flip chip is manufactured and mounted on a circuit board to form an electronic circuit device. As shown in FIGS. 5 and 6, a metal conductor layer is formed on one main surface of a semiconductor wafer 11 as a semiconductor substrate or a semiconductor substrate on which a predetermined semiconductor region is formed in order to form a flip chip such as a transistor, a diode, an IC. 12 is provided, and a metal paste film 13 is provided by printing or transferring a metal paste on the conductor layer 12. The metal paste film 13 is the same as the metal paste film 3 in FIG.
【００１４】次に、金属ペースト膜１３の溶剤を第１の
実施例と同様に乾燥によって蒸発させた後に、図７に示
すようにレーザ光１４を金属ペースト膜１３の突起形成
予定領域１５に選択的に投射する。このレーザ光１４の
強さは第１の実施例と同様に設定する。Next, after the solvent of the metal paste film 13 is evaporated by drying in the same manner as in the first embodiment, the laser beam 14 is selected on the projection forming region 15 of the metal paste film 13 as shown in FIG. To project. The intensity of the laser light 14 is set in the same manner as in the first embodiment.
【００１５】次に、金属ペースト膜１３のレーザ光１４
の非投射領域を溶剤を使用した超音波洗浄によって除去
し、図８に示す突起電極１６を導体層１２の上に残存さ
せる。突起電極１６は金属粉末の溶融凝集によって生じ
たものであり、導体層１２に対して溶融結合されてい
る。Next, the laser light 14 of the metal paste film 13 is formed.
The non-projection area of is removed by ultrasonic cleaning using a solvent, and the protruding electrode 16 shown in FIG. 8 remains on the conductor layer 12. The protruding electrode 16 is generated by melting and agglomeration of the metal powder, and is melt-bonded to the conductor layer 12.
【００１６】次に、図５〜図８で破線で示す分割線に沿
って半導体ウエハ１１を切断し、図９に示す半導体基板
１１ａと導体層１２と突起電極１６とから成るフリップ
チップ１７を得、これを回路基板１８の接続導体層１９
にフェイスダウンボンディングする。フェイスダウンボ
ンディングは、熱圧着、超音波ボンディング、異方性導
電接着材による方法等によって行う。Next, the semiconductor wafer 11 is cut along a dividing line shown by broken lines in FIGS. 5 to 8 to obtain a flip chip 17 composed of the semiconductor substrate 11a, the conductor layer 12 and the protruding electrodes 16 shown in FIG. , The connection conductor layer 19 of the circuit board 18
Face down bonding to. Face down bonding is performed by thermocompression bonding, ultrasonic bonding, anisotropic conductive adhesive, or the like.
【００１７】本実施例によれば第１の実施例と同様に突
起電極１６を正確且つ容易に形成することができる。According to this embodiment, similarly to the first embodiment, the protruding electrode 16 can be formed accurately and easily.
【００１８】[0018]
【変形例】本発明は上述の実施例に限定されるものでな
く、例えば次の変形が可能なものである。 （１） 溶剤を蒸発させる乾燥工程を省いてレーザ光５
又は１４を金属ペースト膜３に投射し、レーザ光によっ
て溶剤を蒸発させることができる。 （２） 突起電極７を作るための金属ペースト即ち導体
ペ−ストにガラス等の無機バインダを混ぜることかでき
る。[Modifications] The present invention is not limited to the above-described embodiment, and for example, the following modifications are possible. (1) Laser light 5 without the drying step of evaporating the solvent
Alternatively, 14 can be projected onto the metal paste film 3, and the solvent can be evaporated by laser light. (2) An inorganic binder such as glass can be mixed with a metal paste, that is, a conductive paste for forming the protruding electrode 7.
【図１】第１の実施例において回路基板上に金属ペース
ト膜を設けたものを示す正面図である。FIG. 1 is a front view showing a circuit board provided with a metal paste film in a first embodiment.
【図２】金属ペースト膜にレーザ光を投射する状態を示
す正面図である。FIG. 2 is a front view showing a state in which a laser beam is projected onto a metal paste film.
【図３】突起電極を有する回路基板を示す正面図であ
る。FIG. 3 is a front view showing a circuit board having protruding electrodes.
【図４】回路基板に半導体チップを実装した電子回路装
置を示す正面図である。FIG. 4 is a front view showing an electronic circuit device in which a semiconductor chip is mounted on a circuit board.
【図５】第２の実施例の金属ペースト膜を有する半導体
ウエハを示す正面図である。FIG. 5 is a front view showing a semiconductor wafer having a metal paste film of a second embodiment.
【図６】図５の半導体ウエハの正面図である。6 is a front view of the semiconductor wafer of FIG.
【図７】金属ペースト膜にレーザ光を投射した状態を示
す正面図である。FIG. 7 is a front view showing a state where laser light is projected onto the metal paste film.
【図８】突起電極を有する半導体ウエハを示す正面図で
ある。FIG. 8 is a front view showing a semiconductor wafer having protruding electrodes.
【図９】フリップチップを回路基板に実装した電子回路
装置を示す正面図である。FIG. 9 is a front view showing an electronic circuit device in which a flip chip is mounted on a circuit board.
１ 回路基板 ２ 導体層 ３ 金属ペースト ５ レーザ光 ７ 突起電極 1 circuit board 2 conductor layer 3 metal paste 5 laser light 7 protruding electrode
Claims (3)
導体層の上に付着させて導体ペースト膜を形成する工程
と、 前記導体ペースト膜又はこの導体ぺ−スト膜を乾燥させ
たものの選択された領域にレーザ光を投射して前記有機
バインダ−を燃焼飛散させ且つ前記導体粉末を溶融凝集
させる工程と、 前記導体ペースト膜又はこの導体ペースト膜を乾燥させ
たものにおけるレーザ光が投射されなかった領域を除去
して前記導体層の上に前記溶融凝集に基づく突起電極を
生じさせる工程とから成る突起電極形成方法。1. A step of forming a conductor layer on the surface of a substrate, a step of forming a conductor paste film by depositing a conductor paste containing conductor powder and an organic binder on the conductor layer, and the conductor paste film. Alternatively, a step of projecting a laser beam onto a selected region of the dried conductor paste film to burn and scatter the organic binder and melt and agglomerate the conductor powder, the conductor paste film or the conductor paste A method for forming a bump electrode, comprising the step of removing a region of the dried film that is not projected by laser light to generate a bump electrode based on the melt aggregation on the conductor layer.
ることを特徴とする請求項１記載の突起電極形成方法。2. The method of forming a bump electrode according to claim 1, wherein the base is a circuit board of a hybrid integrated circuit.
半導体基板であることを特徴とする請求項１記載の突起
電極形成方法。3. The method according to claim 1, wherein the base body is a semiconductor substrate for forming a semiconductor element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7329546A JPH09148379A (en) | 1995-11-22 | 1995-11-22 | Formation of salient electrode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7329546A JPH09148379A (en) | 1995-11-22 | 1995-11-22 | Formation of salient electrode |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH09148379A true JPH09148379A (en) | 1997-06-06 |
Family
ID=18222573
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7329546A Withdrawn JPH09148379A (en) | 1995-11-22 | 1995-11-22 | Formation of salient electrode |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH09148379A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100788191B1 (en) * | 2007-04-25 | 2008-01-02 | 주식회사 고려반도체시스템 | Bump forming process of semiconductor element |
| JP2008078514A (en) * | 2006-09-25 | 2008-04-03 | Tokyo Institute Of Technology | Method of manufacturing semiconductor integrated circuit device |
| JP2015507367A (en) * | 2012-02-03 | 2015-03-05 | エーエスエムエル ネザーランズ ビー．ブイ． | Substrate holder and substrate holder manufacturing method |
| CN104485154A (en) * | 2014-12-24 | 2015-04-01 | 苏州晶讯科技股份有限公司 | Electronic copper-containing paste capable of forming copper circuit through laser radiation |
-
1995
- 1995-11-22 JP JP7329546A patent/JPH09148379A/en not_active Withdrawn
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008078514A (en) * | 2006-09-25 | 2008-04-03 | Tokyo Institute Of Technology | Method of manufacturing semiconductor integrated circuit device |
| KR100788191B1 (en) * | 2007-04-25 | 2008-01-02 | 주식회사 고려반도체시스템 | Bump forming process of semiconductor element |
| US10898955B2 (en) | 2012-02-03 | 2021-01-26 | Asme Netherlands B.V. | Substrate holder, lithographic apparatus, device manufacturing method, and method of manufacturing a substrate holder |
| US9442395B2 (en) | 2012-02-03 | 2016-09-13 | Asml Netherlands B.V. | Substrate holder, lithographic apparatus, device manufacturing method, and method of manufacturing a substrate holder |
| US9507274B2 (en) | 2012-02-03 | 2016-11-29 | Asml Netherlands B.V. | Substrate holder and method of manufacturing a substrate holder |
| US9737934B2 (en) | 2012-02-03 | 2017-08-22 | Asml Netherlands B.V. | Substrate holder and method of manufacturing a substrate holder |
| US10245641B2 (en) | 2012-02-03 | 2019-04-02 | Asml Netherlands B.V. | Substrate holder, lithographic apparatus, device manufacturing method, and method of manufacturing a substrate holder |
| US10875096B2 (en) | 2012-02-03 | 2020-12-29 | Asml Netherlands B.V. | Substrate holder and method of manufacturing a substrate holder |
| JP2015507367A (en) * | 2012-02-03 | 2015-03-05 | エーエスエムエル ネザーランズ ビー．ブイ． | Substrate holder and substrate holder manufacturing method |
| US11235388B2 (en) | 2012-02-03 | 2022-02-01 | Asml Netherlands B.V. | Substrate holder, lithographic apparatus, device manufacturing method, and method of manufacturing a substrate holder |
| US11376663B2 (en) | 2012-02-03 | 2022-07-05 | Asml Netherlands B.V. | Substrate holder and method of manufacturing a substrate holder |
| US11628498B2 (en) | 2012-02-03 | 2023-04-18 | Asml Netherlands B.V. | Substrate holder, lithographic apparatus, device manufacturing method, and method of manufacturing a substrate holder |
| US11754929B2 (en) | 2012-02-03 | 2023-09-12 | Asml Netherlands B.V. | Substrate holder and method of manufacturing a substrate holder |
| US11960213B2 (en) | 2012-02-03 | 2024-04-16 | Asml Netherlands B.V. | Substrate holder, lithographic apparatus, device manufacturing method, and method of manufacturing a substrate holder |
| CN104485154A (en) * | 2014-12-24 | 2015-04-01 | 苏州晶讯科技股份有限公司 | Electronic copper-containing paste capable of forming copper circuit through laser radiation |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6153940A (en) | Core metal soldering knob flip-chip technology | |
| JP3348528B2 (en) | Method for manufacturing semiconductor device, method for manufacturing semiconductor device and electronic circuit device, and electronic circuit device | |
| US20090289360A1 (en) | Workpiece contact pads with elevated ring for restricting horizontal movement of terminals of ic during pressing | |
| KR100737498B1 (en) | Method for mounting semiconductor device and structure thereof | |
| JPH09326416A (en) | Packaging of semiconductor device and product thereof | |
| JPH09148379A (en) | Formation of salient electrode | |
| JPH09162230A (en) | Electronic circuit device and its manufacturing method | |
| JPS62281435A (en) | Semiconductor device | |
| JPH04264731A (en) | Formation of electrical connection contact and mounting board using it | |
| JPH04263434A (en) | Formation of electric connection contact and manufacture of mounting board | |
| JPH0645402A (en) | Wiring board and method of connection thereof | |
| JPS6057944A (en) | Semiconductor device | |
| TWI220304B (en) | Flip-chip package substrate and flip-chip bonding process thereof | |
| JP3006957B2 (en) | Semiconductor device package | |
| JPH05136201A (en) | Electrode for semiconductor device and mounting body | |
| JPH05144821A (en) | Semiconductor device | |
| JPS63168028A (en) | Fine connection structure | |
| JP2633745B2 (en) | Semiconductor device package | |
| JPH02312240A (en) | Formation of bump | |
| JPH0695468B2 (en) | Method of forming electrical connection contact | |
| TW516142B (en) | Forming method for solder bump by self-alignment | |
| JPH04356935A (en) | Bump-electrode formation and mounting structure of semiconductor device | |
| JP2000332060A (en) | Semiconductor device and manufacture thereof | |
| JPH11204573A (en) | Manufacture of semiconductor device and the semiconductor device | |
| JPH04169001A (en) | Method of mounting conductive paste and semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 20030204 |