JP2633745B2 - Semiconductor device package - Google Patents

Semiconductor device package

Info

Publication number
JP2633745B2
JP2633745B2 JP3105476A JP10547691A JP2633745B2 JP 2633745 B2 JP2633745 B2 JP 2633745B2 JP 3105476 A JP3105476 A JP 3105476A JP 10547691 A JP10547691 A JP 10547691A JP 2633745 B2 JP2633745 B2 JP 2633745B2
Authority
JP
Japan
Prior art keywords
semiconductor device
protrusion
electrode
solder
bonding layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP3105476A
Other languages
Japanese (ja)
Other versions
JPH04335542A (en
Inventor
芳宏 別所
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP3105476A priority Critical patent/JP2633745B2/en
Publication of JPH04335542A publication Critical patent/JPH04335542A/en
Application granted granted Critical
Publication of JP2633745B2 publication Critical patent/JP2633745B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods

Landscapes

  • Wire Bonding (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は、半導体装置を回路基板
に実装する際の電極構造に関するものであり、特にフェ
ースダウンで実装してなる半導体装置用電極と実装体に
関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrode structure for mounting a semiconductor device on a circuit board, and more particularly to a semiconductor device electrode and a mounting body mounted face-down.

【0002】[0002]

【従来の技術】従来、半導体装置の回路基板上への実装
には半田付けがよく利用されていたが、近年、半導体装
置のパッケージの小型化と接続端子数の増加により、接
続端子間隔が狭くなり、従来の半田付け技術で対処する
ことが次第に困難になってきた。
2. Description of the Related Art Conventionally, soldering has often been used for mounting a semiconductor device on a circuit board. However, in recent years, the spacing between connection terminals has been reduced due to the miniaturization of the package of the semiconductor device and the increase in the number of connection terminals. It has become increasingly difficult to deal with the conventional soldering technology.

【0003】そこで、最近では裸の半導体装置を回路基
板上に直付けして実装面積の小型化と効率的使用を図ろ
うとする方法が考案されてきた。
Therefore, recently, a method has been devised in which a bare semiconductor device is directly mounted on a circuit board in order to reduce the mounting area and use the device efficiently.

【0004】なかでも、半導体装置を回路基板に接続す
るに際し、あらかじめ半導体装置のアルミ電極パッド上
に密着金属や拡散防止金属の蒸着膜とこの上にメッキに
より形成した半田層とからなる電極構造を有する半導体
装置を下向き(フェースダウン)にして、高温に加熱し
て半田を回路基板の端子電極に融着する実装構造が、接
続後の機械的強度が強く、接続が一括にできることなど
から有効な方法であるとされている。(例えば、工業調
査会、1980年1月15日発行、日本マイクロエレク
トロニクス協会編、『IC化実装技術』)以下図面を参
照しながら、上述した従来の半導体装置の電極構造と実
装構造の一例について説明する。
In particular, when connecting a semiconductor device to a circuit board, an electrode structure composed of a deposited film of an adhesion metal or a diffusion preventing metal on an aluminum electrode pad of the semiconductor device in advance and a solder layer formed thereon by plating is used. A mounting structure in which the semiconductor device is turned downward (face down) and heated to a high temperature to fuse the solder to the terminal electrodes of the circuit board is effective because the mechanical strength after connection is strong and the connection can be made at once. It is said to be the way. (For example, Industrial Research Council, published on January 15, 1980, edited by the Japan Microelectronics Association, "IC mounting technology") An example of the above-described electrode structure and mounting structure of the conventional semiconductor device will be described with reference to the drawings. explain.

【0005】(図3)は従来の半田バンプ電極を有する
半導体装置の電極構造の概略説明図であり、(図4)は
上記半導体装置の実装構造の概略説明図である。
FIG. 3 is a schematic explanatory view of an electrode structure of a conventional semiconductor device having solder bump electrodes, and FIG. 4 is a schematic explanatory view of a mounting structure of the semiconductor device.

【0006】(図3)において、8は半導体装置のIC
基板であり、9はアルミ電極パッドである。10は密着
金属膜であり、11は拡散防止金属膜である。12は半
田突起であり、13はパッシベーション膜である。(図
4)において、14は回路基板であり、15は端子電極
である。
In FIG. 3, reference numeral 8 denotes an IC of a semiconductor device.
A substrate 9 is an aluminum electrode pad. Reference numeral 10 denotes an adhesion metal film, and reference numeral 11 denotes a diffusion prevention metal film. Reference numeral 12 denotes a solder protrusion, and reference numeral 13 denotes a passivation film. In FIG. 4, 14 is a circuit board, and 15 is a terminal electrode.

【0007】以上のように構成された従来の半田バンプ
電極を有する半導体装置の電極構造と実装構造につい
て、以下その概略を説明する。
[0007] The electrode structure and mounting structure of a conventional semiconductor device having a solder bump electrode configured as described above will be outlined below.

【0008】まず、半導体装置のIC基板8のアルミ電
極パッド9上にCuなどの密着金属膜10およびCrな
どの拡散防止金属膜11を蒸着により形成する。その
後、電極部以外をフォトレジストで覆い、メッキ法によ
り半田を拡散防止金属膜11上に析出させて半田リフロ
ーを行うことにより、半田突起12を形成して(図3)
の半田バンプ電極を得る。
First, an adhesion metal film 10 such as Cu and a diffusion prevention metal film 11 such as Cr are formed on an aluminum electrode pad 9 of an IC substrate 8 of a semiconductor device by vapor deposition. Thereafter, the portions other than the electrode portions are covered with a photoresist, and solder is deposited on the diffusion preventing metal film 11 by a plating method and solder reflow is performed to form solder protrusions 12 (FIG. 3).
Is obtained.

【0009】さらに、以上のようにして得た半田バンプ
電極を有する半導体装置を、回路基板14の所定の位置
に位置合わせを行ってフェースダウンで積載した後、2
00〜300℃の高温に加熱して半田突起12を溶融
し、端子電極15に融着することによって半導体装置の
実装を行うものである。
Further, the semiconductor device having the solder bump electrodes obtained as described above is aligned face-to-face with a predetermined position on the circuit board 14, and is loaded face-down.
The semiconductor device is mounted by heating to a high temperature of 00 to 300 ° C. to melt the solder protrusions 12 and fuse them to the terminal electrodes 15.

【0010】[0010]

【発明が解決しようとする課題】しかしながら上記のよ
うな半田バンプ電極を有する半導体装置の電極構造や実
装構造においては、 1.半導体装置のアルミ電極パッド上に密着金属膜や拡
散防止金属膜が必要で、電極構造が複雑となり、汎用性
に欠ける。
However, in the electrode structure and mounting structure of a semiconductor device having the above-mentioned solder bump electrodes, there are the following problems. The adhesion metal film and the diffusion prevention metal film are required on the aluminum electrode pad of the semiconductor device, which complicates the electrode structure and lacks versatility.

【0011】2.高温に加熱して半田を溶融して端子電
極と接続する際に、IC基板と回路基板とのギャップを
維持することが出来ないため、半田が広がって隣接とシ
ョートする危険がある。などといった課題を有してい
た。
2. When heating to a high temperature to melt the solder and connect it to the terminal electrodes, it is not possible to maintain the gap between the IC substrate and the circuit board. And so on.

【0012】本発明は上記の課題に鑑みてなされたもの
であり、その目的とするところは、半導体装置と回路基
板とを容易に信頼性良く接続することのできる半導体装
置の電極構造と実装構造を提供することにある。
SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to provide an electrode structure and a mounting structure of a semiconductor device which can easily and reliably connect the semiconductor device and a circuit board. Is to provide.

【0013】[0013]

【課題を解決するための手段】本発明は上記の課題を解
決するため、フェースダウンで回路基板に実装する半導
体装置において、半導体装置のアルミ電極パッド部上に
台座部と頂上部の2段突起状のバンプ電極を備え、上記
2段突起状のバンプ電極の頂上部にのみ無機接合層を形
成した電極構造を有し、かつ、半導体装置のアルミ電極
パッド部上の2段突起状のバンプ電極を無機接合層を介
して回路基板上の端子電極に電気的に接続する実装構造
を有することを特徴として、信頼性の高い半導体装置の
回路基板への実装を実現しようとするものである。
SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides a semiconductor device mounted face down on a circuit board. Having an electrode structure in which an inorganic bonding layer is formed only on the top of the above-mentioned two-stage bump electrode, and a two-stage bump electrode on an aluminum electrode pad portion of a semiconductor device. Has a mounting structure for electrically connecting the semiconductor device to a terminal electrode on a circuit board via an inorganic bonding layer, thereby realizing mounting of a highly reliable semiconductor device on the circuit board.

【0014】[0014]

【作用】本発明は、半導体装置のアルミ電極パッド部上
に直接形成した2段突起形状のバンプ電極の頂上部にの
み無機接合層を形成した電極構造を有することにより、
半導体装置を回路基板の端子電極に接合する際に接合層
が隣接とショートすることなく微細ピッチでの接合が可
能となり、かつ、信頼性の高い半導体装置の実装構造が
実現できる。
The present invention has an electrode structure in which an inorganic bonding layer is formed only on the top of a two-step projection-shaped bump electrode formed directly on an aluminum electrode pad portion of a semiconductor device.
When a semiconductor device is bonded to a terminal electrode of a circuit board, bonding can be performed at a fine pitch without a short circuit between adjacent bonding layers, and a highly reliable semiconductor device mounting structure can be realized.

【0015】[0015]

【実施例】以下、本発明の一実施例の半導体装置用電極
と実装体について、図面を参照しながら説明する。
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is an exploded perspective view of a semiconductor device according to an embodiment of the present invention;

【0016】(図1)は、本発明の一実施例における半
導体装置の電極構造の概略説明図であり、(図2)は、
上記実施例の電極構造を有する半導体装置の実装構造の
概略説明図である。
FIG. 1 is a schematic explanatory view of an electrode structure of a semiconductor device according to one embodiment of the present invention, and FIG.
FIG. 3 is a schematic explanatory view of a mounting structure of the semiconductor device having the electrode structure of the embodiment.

【0017】(図1)において、1は半導体装置のIC
基板であり、2はアルミ電極パッドである。3は台座部
と頂上部からなる2段突起状のバンプ電極であり、4は
2段突起形状のバンプ電極の頂上部にのみ形成した半田
接合層である。5はパッシベーション膜である。(図
2)において、6は回路基板であり、7は端子電極であ
る。
In FIG. 1, reference numeral 1 denotes an IC of a semiconductor device.
A substrate 2 is an aluminum electrode pad. Numeral 3 denotes a bump electrode having a two-stage protrusion composed of a pedestal portion and a top portion, and numeral 4 denotes a solder bonding layer formed only on the top portion of the bump electrode having a two-stage protrusion shape. 5 is a passivation film. In FIG. 2, 6 is a circuit board, and 7 is a terminal electrode.

【0018】以上のように構成された半導体装置の電極
構造と実装構造について、以下図面を用いて説明する。
The electrode structure and the mounting structure of the semiconductor device configured as described above will be described below with reference to the drawings.

【0019】まず、半導体装置のIC基板1のアルミ電
極パッド2上に通常のワイヤボンディング技術と同様に
Auワイヤの先端のAuボールを固着した後、Auワイ
ヤを切断することにより台座部と頂上部を有する2段突
起状のバンプ電極3を形成する。
First, an Au ball at the tip of an Au wire is fixed on an aluminum electrode pad 2 of an IC substrate 1 of a semiconductor device in the same manner as in a normal wire bonding technique, and then the Au wire is cut to obtain a pedestal portion and a top portion. To form a bump electrode 3 having a two-step protrusion shape.

【0020】その後、2段突起状のバンプ電極3の頂上
部にのみ、半田接合層4を転写法や印刷法によって形成
する。この時、必要に応じて半田リフローを行う。
Thereafter, the solder bonding layer 4 is formed only on the top of the bump electrode 3 having a two-step projection by a transfer method or a printing method. At this time, solder reflow is performed as needed.

【0021】上記により、汎用の半導体装置のアルミ電
極パッド2上に2段突起状のバンプ電極3と半田接合層
4からなる電極構造が容易に得られる。
As described above, an electrode structure including the bump electrode 3 having a two-step projection and the solder bonding layer 4 can be easily obtained on the aluminum electrode pad 2 of a general-purpose semiconductor device.

【0022】本発明の半導体装置の電極構造は、上記し
た方法により、通常のワイヤボンディング装置で2段突
起形状のバンプ電極を得ることが出来るため、通常のア
ルミ電極パッドを有する汎用の半導体装置を用いること
が可能となり、極めて汎用性が高い。
According to the electrode structure of the semiconductor device of the present invention, a bump electrode having a two-step projection can be obtained by a normal wire bonding apparatus by the above-described method. It can be used and is extremely versatile.

【0023】さらに、以上のようにして得た電極構造を
有する半導体装置を、回路基板6の所定の位置に位置合
わせを行ってフェースダウンで積載した後、200〜3
00℃の高温に加熱して半田接合層4を溶融し、端子電
極7に融着することによって半導体装置の実装を行う。
Further, the semiconductor device having the electrode structure obtained as described above is aligned face-to-face at a predetermined position on the circuit board 6 and mounted face-down.
The semiconductor device is mounted by heating to a high temperature of 00 ° C. to melt the solder bonding layer 4 and fuse it to the terminal electrode 7.

【0024】この高温に加熱して半田接合層4を溶融し
て端子電極7と接続する際に、IC基板1と回路基板6
とのギャップを2段突起状のバンプ電極3により維持す
ることが出来、かつ、頂上部にのみ半田接合層4を形成
しているすることが出来るため、半田の広がりを規制す
ることが可能となって隣接とショートする危険がなく、
微細ピッチでの接続が可能な半導体装置の実装構造が得
られる。
When the soldering layer 4 is melted by heating to a high temperature and connected to the terminal electrodes 7, the IC board 1 and the circuit board 6
Can be maintained by the bump electrode 3 having a two-step projection, and the solder bonding layer 4 can be formed only on the top, so that the spread of solder can be restricted. There is no danger of short circuit with the neighbor,
A mounting structure of a semiconductor device which can be connected at a fine pitch is obtained.

【0025】本発明の半導体装置の実装構造は、上記し
た方法により、従来の半田バンプ電極による実装構造で
は不可能であった半田の広がりの規制が2段突起状のバ
ンプ電極を用いることで可能となり、極めて安定で信頼
性良く、かつ、高密度に半導体装置を実装できる。
According to the mounting structure of the semiconductor device of the present invention, the spread of the solder, which was impossible with the conventional mounting structure using the solder bump electrodes, can be controlled by using the bump electrodes having a two-step projection. Thus, the semiconductor device can be mounted very stably, with high reliability and with high density.

【0026】なお、本実施例では2段突起状のバンプ電
極をワイヤボンディング装置を用いて形成するとした
が、その形状が2段突起状であればメッキなど他の方法
で形成しても良い。
In the present embodiment, the bump electrode having a two-step projection is formed by using a wire bonding apparatus. However, if the shape of the bump electrode is a two-step projection, it may be formed by another method such as plating.

【0027】また、バンプ電極をAuからなるものとし
たが、その材質はAuに限られる物でなく、例えば、C
uなど他の金属から形成しても良い。
Although the bump electrode is made of Au, the material is not limited to Au.
It may be formed from other metals such as u.

【0028】さらに、2段突起状のバンプ電極の頂上部
に形成する半田接合層は、半田ペーストを転写や印刷に
よって形成しても良い。
Further, the solder bonding layer formed on the top of the two-step projecting bump electrode may be formed by transferring or printing a solder paste.

【0029】[0029]

【発明の効果】以上に説明したように、本発明の半導体
装置用電極と実装体によれば、通常のワイヤボンディン
グ装置で半導体装置のアルミ電極パッド部上に直接形成
することができるため、汎用の半導体装置を用いること
が可能となり、極めて汎用性が高い。
As described above, according to the semiconductor device electrode and the package of the present invention, since it can be formed directly on the aluminum electrode pad portion of the semiconductor device by a normal wire bonding apparatus, it can be used for general purpose. Semiconductor device can be used, and the versatility is extremely high.

【0030】さらに、2段突起形状のバンプ電極の頂上
部にのみ無機接合層を形成した電極構造を有することに
より、半導体装置を回路基板の端子電極に接合する際に
無機接合層の広がりの規制が可能となり、無機接合層が
隣接とショートすることなく微細ピッチでの接合が可能
な実装構造となり、極めて安定で信頼性良く、かつ、高
密度に半導体装置を実装できる。
Further, by having an electrode structure in which the inorganic bonding layer is formed only on the top of the bump electrode having a two-step projection, the spread of the inorganic bonding layer when the semiconductor device is bonded to the terminal electrode of the circuit board is restricted. This makes it possible to achieve a mounting structure that enables bonding at a fine pitch without short-circuiting the inorganic bonding layer to the adjacent layer, and enables extremely stable, highly reliable, and high-density mounting of the semiconductor device.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施例における半導体装置の電極の
概略説明図である。
FIG. 1 is a schematic explanatory view of an electrode of a semiconductor device according to an embodiment of the present invention.

【図2】本発明の一実施例の電極構造を有する半導体装
置の実装体の概略説明図である。
FIG. 2 is a schematic explanatory view of a package of a semiconductor device having an electrode structure according to one embodiment of the present invention.

【図3】従来の半田バンプ電極を有する半導体装置の電
極の概略説明図である。
FIG. 3 is a schematic explanatory view of an electrode of a conventional semiconductor device having solder bump electrodes.

【図4】従来の半田バンプ電極を有する半導体装置の実
装体の概略説明図である。
FIG. 4 is a schematic explanatory view of a conventional mounting body of a semiconductor device having solder bump electrodes.

【符号の説明】[Explanation of symbols]

1 半導体装置のIC基板 2 アルミ電極パッド 3 2段突起状のバンプ電極 4 半田接合層 5 パッシベーション膜 6 回路基板 7 端子電極 8 半導体装置のIC基板 9 アルミ電極パッド 10 密着金属膜 11 拡散防止金属膜 12 半田突起 13 パッシベーション膜 14 回路基板 15 端子電極 REFERENCE SIGNS LIST 1 IC substrate of semiconductor device 2 aluminum electrode pad 3 two-step protruding bump electrode 4 solder bonding layer 5 passivation film 6 circuit board 7 terminal electrode 8 IC substrate of semiconductor device 9 aluminum electrode pad 10 adhesion metal film 11 diffusion preventing metal film 12 solder protrusion 13 passivation film 14 circuit board 15 terminal electrode

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】半導体装置を基板上の端子電極部にフェー
スダウンで実装した構成であって、 前記半導体装置の電極パッド部上にワイヤボンディング
法により直接形成された第1の突起部および前記第1の
突起部の上に形成され、かつ前記第1の突起部の前記電
極パッド部と平行な断面積より小さな前記電極パッド部
と平行な断面積を有する第2の突起部とからなる2段突
起状のAuからなるバンプ電極と、 前記基板上の前記端子電極部とは、半田 接合層を介して電気的に接続されており、 前記半田接合層は、前記第1の突起部を中心に2段突起
状のバンプ電極上のみに形成されていることを特徴とす
る半導体装置の実装体。
1. A semiconductor device having a structure in which a semiconductor device is mounted face-down on a terminal electrode portion on a substrate, and wire bonding is performed on an electrode pad portion of the semiconductor device.
A first protrusion directly formed by a method and a first protrusion formed on the first protrusion and having a cross-sectional area smaller than a cross-sectional area of the first protrusion parallel to the electrode pad. A bump electrode made of a two-step protrusion made of Au having a second protrusion having a cross-sectional area, and the terminal electrode portion on the substrate are electrically connected via a solder bonding layer; The semiconductor device package according to claim 1, wherein the solder bonding layer is formed only on the bump electrode having a two-step protrusion shape centering on the first protrusion.
【請求項2】第1の突起部と第2の突起部と半田接合層
よりなる電極構造であって、 前記第1および前記第2の突起部は、ワイヤボンディン
グ法により形成され、前記第2の突起部の水平面の断面
積が前記第1の突起部の水平面の断面積より小さく、か
つ前記第2の突起部が前記第1の突起部の上に形成され
て2段突起状のAuからなるバンプ電極を構成し、 前記半田接合層は、前記第1の突起部を中心に2段突起
状のバンプ電極上のみに形成されていることを特徴とす
る電極構造。
2. An electrode structure comprising a first protrusion, a second protrusion, and a solder bonding layer, wherein the first and second protrusions are wire bonding.
The second protrusion is formed on the first protrusion by a cross-sectional area of a horizontal plane smaller than that of the first protrusion, and the second protrusion is formed on the first protrusion. Thus, a bump electrode made of Au having a two-step protrusion is formed, and the solder bonding layer is formed only on the bump electrode having a two-step protrusion centering on the first protrusion. Electrode structure.
JP3105476A 1991-05-10 1991-05-10 Semiconductor device package Expired - Fee Related JP2633745B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3105476A JP2633745B2 (en) 1991-05-10 1991-05-10 Semiconductor device package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3105476A JP2633745B2 (en) 1991-05-10 1991-05-10 Semiconductor device package

Publications (2)

Publication Number Publication Date
JPH04335542A JPH04335542A (en) 1992-11-24
JP2633745B2 true JP2633745B2 (en) 1997-07-23

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4738971B2 (en) * 2005-10-14 2011-08-03 Okiセミコンダクタ株式会社 Semiconductor device and manufacturing method thereof
US8483523B2 (en) 2009-09-14 2013-07-09 Ricoh Company, Ltd. Optical waveguide electro-optic device and process of manufacturing optical waveguide electro-optic device

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0666355B2 (en) * 1988-12-16 1994-08-24 松下電器産業株式会社 Semiconductor device mounting body and mounting method thereof
JPH045844A (en) * 1990-04-23 1992-01-09 Nippon Mektron Ltd Multilayer circuit board for mounting ic and manufacture thereof

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