JPH09135426A - Indentification control signal processing circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide high-accuracy reference timing for decoding a reinforcing signal in simple configuration without causing any trouble such as the reference timing is changed by noise, ghost or a little deviation in adjustment. SOLUTION: A gate signal generating circuit 12 generates a gate signal for extracting an identification control signal near the 50% fall of a 1st bit and a gate signal for extracting a confirm signal section in the identification control signal. A BPF 14 extracts the confirm signal section in the identification control signal. A code extracting circuit 15 extracts the code of a signal extracted by the BPF 14. An edge detection circuit 16 detects the rising (falling) edge of the code. A timing signal generating circuit 17 generates the reference timing by gating an EDTV 2 signal and the edge signal corresponding to the gate signals.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a second-generation EDTV (hereinafter referred to as "the second-generation EDTV", which is compatible with the current NTSC color television transmission system and is transmitted in a letterbox format by providing a non-image portion above and below a wide aspect image. , EDTV2
(Hereinafter referred to as)), the identification control signal processing circuit for processing the television identification control signal.

[0002]

2. Description of the Related Art The NTSC color television transmission system, which is the current television broadcasting, has an aspect ratio of 4: 3. As a next-generation color television transmission system, a scanning line in the central portion of a screen having an aspect ratio of 4: 3 is used. Wide aspect image with 16: 9 aspect ratio (main picture part) on 360 lines
EDTV2 of the letter box system in which about 120 scanning lines remaining above and below are assigned as the masking area (non-image area)
Has been put to practical use.

In this EDTV 2, the components lost when the wide aspect image signal which is the original image is converted into the image signal of the main picture portion are various reinforcement signals (horizontal reinforcement signal, vertical reinforcement signal) in the main picture portion and the non-picture portion. Signal, time vertical reinforcement signal)
Is transmitted as In addition, the identification control signal required for determining whether the signal is a television signal of the EDTV 2 or for controlling various reinforcement signals has one horizontal scanning line period for each field and the 22nd line (22H) that is the uppermost portion on the screen. And the 285th
It is transmitted on the line (285H).

This identification control signal is shown in FIG. As shown in FIG. 4, the identification control signal has a configuration in which one horizontal scanning line period is divided into 27 bits and signals of three different formats are superimposed. The first bit B1 to the fifth bit B5 are identification signals in the NRZ format, the sixth bits B6 to the 23rd bit B23 are the identification signals in the carrier wave format of the frequency fsc, and the 25th bit B25 to the 27th bit B27 are the frequency 4
The confirmation signal is a carrier wave format of fsc / 7 (2.04 MHz). Here, fsc is a color subcarrier frequency (3.58 MHz). The identification control signal includes an identification function of transmitting a command by using each bit, a confirmation function of indicating that the signal itself is an identification control signal, and a control function of generating a timing signal necessary for decoding the reinforcement signal. There are two functions.

In the EDTV2 decoder, a non-picture portion is stretched in accordance with the main picture portion or a horizontal reinforcement signal (HH) is demodulated in phase with the main picture portion as processing of the reinforcement signal. is required. On the other hand, the EDTV2 signal is a normal NTS signal in the broadcasting station.
It is often processed in the same way as the C signal. At this time, the position of the image with respect to the horizontal synchronizing signal may shift during the process of editing or the like. When a horizontal synchronizing signal is used as the reference timing, this shift causes the reinforcing signal to be out of phase with the main picture portion on the decoder side and cannot be correctly reproduced.

[0006] Such signal processing in the broadcasting station is EDTV.
In order to prevent the influence on the decoding processing of the two signals, the position of the identification control signal is to be shifted like the image.
The EDTV2 decoder performs a decoding process using the reference timing generated from the received identification control signal. In the identification control signal, the 50% falling point of the first bit B1, the bit switching point, and the zero-cross point of a signal other than the NRZ format are set as reference timings.

FIG. 3 is a block diagram showing an example of a conventional identification control signal processing circuit. In this example, the 50% falling point of the first bit B1 of the identification control signal is used as the reference timing. The incoming composite signal of EDTV2 is composed of a sync separation circuit 1, a comparator 3, and an EDT.
It is input to the V2 decoder 5. The sync separation circuit 1 separates the horizontal and vertical sync signals from the composite signal and outputs it. The gate signal generating circuit 2 is based on the input horizontal and vertical synchronizing signals and outputs 22H and 285H of composite signals.
A gate signal indicating the vicinity of the 50% falling point of the first bit B1 of the identification control signal superimposed on is generated. This gate signal is input to the comparator 3.

The comparator 3 has a preset NRZ
Part 50% level (20IRE) and input EDT
By comparing the signal gated with the gate signal in the V2 signal, the first bit B1 of the identification control signal
The 50% falling point of is detected. The timing signal generation circuit 4 uses the 50% falling point detected by the comparator 3 as a reference timing to generate a timing signal necessary for decoding the EDTV2 signal. The carrier required for HH demodulation and the time vertical reinforcement signal (V
T), vertical reinforcement signal (VH) multiple timing signal, and the like. The EDTV2 decoder 5 decodes the EDTV2 signal using these timing signals.

When the switching point of each bit is used as the reference timing, the generation timing of the gate signal by the gate signal generating circuit 2 in FIG. 3 is set near the switching point of the bit to be detected. Also,
When the bit to be detected is in the carrier wave format, a process for demodulating the composite signal at the carrier wave frequency is necessary before the comparator 3. Furthermore, as the reference timing,
The circuit configuration is the same as in FIG. 3 when detecting a zero-cross point where the carrier wave portion crosses 0IRE (black level), and the gate signal generation timing of the gate signal generation circuit 2 is set near an appropriate point to be detected. , The reference level of the comparator 3 is set to 0IRE.

[0010]

By the way, in the above-described conventional identification control signal processing circuit, when the configuration is based on the 50% fall of the first bit B1 of the identification control signal, a slight noise or level fluctuation is generated. , The timing of the 50% falling point becomes unstable due to the influence of ghost, etc. As a countermeasure against this, a method of filtering an input signal for the purpose of removing noise can be considered, but it is difficult to determine the timing because the waveform is blunted, and the influence of the ghost cannot be removed eventually.

Also, the method of detecting the bit switching point has the same problem when the NRZ part is used, and when the carrier type part is used,
There is a problem that the EDTV2 signal must be demodulated. Further, even when a zero-cross point at which the confirmation signal portion crosses 0IRE is detected, there is a problem that the timing changes due to the influence of ghost and a slight deviation of the direct current component due to the adjustment of the circuit.

The present invention has been made in view of the above problems, and does not cause a problem that the reference timing changes due to noise, ghost, and slight deviation of adjustment, and has a simple structure and high accuracy. An object of the present invention is to provide an identification control signal processing circuit that can obtain a reference timing for decoding a reinforcement signal.

[0013]

In order to solve the above-mentioned problems of the prior art, the present invention is compatible with the NTSC color television transmission system and uses a wide aspect image as the main image portion, and In a discrimination control signal processing circuit for processing the discrimination control signal in a letterbox type EDTV signal in which a reinforcement signal and a discrimination control signal are transmitted to the non-picture portion or the main picture portion by providing a non-picture portion above and below , 50% of the first bit in the identification control signal
A gate signal generation circuit for generating a first gate signal for extracting the vicinity of a falling edge and a second gate signal for extracting a confirmation signal portion of the identification control signal, and extracting a confirmation signal portion of the identification control signal. A filter, a code extraction circuit for extracting the code of the signal extracted by the filter, an edge detection circuit for detecting the rising or falling edge of the code extracted by the code extraction circuit, the EDTV signal and the edge detection An edge signal detected by a circuit is inputted, and a timing signal generating circuit for generating a reference timing by gated these signals by the first and second gate signals is provided. A signal processing circuit is provided.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An identification control signal processing circuit of the present invention will be described below with reference to the accompanying drawings. 1 is a block diagram showing an embodiment of an identification control signal processing circuit of the present invention, and FIG. 2 is a block diagram showing a specific configuration of the timing signal generating circuit 17 in FIG.

In FIG. 1, the incoming composite signal of the EDTV 2 is a sync separation circuit 11 and an A / D converter 1.
3 is input. The sync separation circuit 11 separates the horizontal and vertical sync signals from the composite signal and outputs them. The gate signal generation circuit 12, based on the input horizontal and vertical synchronization signals, a gate signal indicating the vicinity of the 50% falling point of the first bit B1 of the identification control signal superimposed on 22H and 285H of the composite signal, A gate signal indicating the confirmation signal portion (portion of the 2.04 MHz sine wave from the 25th bit B25 to the 27th bit B27) is generated. These two gate signals are input to the timing signal generation circuit 17.

The A / D converter 13 A / D converts the incoming EDTV2 signal, and a band pass filter (BPF) 14
To enter. The BPF 14 extracts a component near 2.04 MHz corresponding to the confirmation signal portion in a narrow band by using, for example, a cyclic filter. The output of the BPF 14 is input to the code extraction circuit 15. The code extraction circuit 15 extracts the code of the input signal. In the case of this configuration, since the input signal is digitized, the most significant bit of the signal becomes the code as it is. Therefore, the code extraction circuit 15 need only select the most significant bit of the input signal.

Attention is paid to the sign bit. Since the DC component of the input signal to the code extraction circuit 15 is removed by the BPF 14, the numerical offset generated by the level setting of the A / D conversion is removed, and the change point of the code, that is, the rising edge of the code bit, The falling edge becomes the zero-cross point as it is. In addition, since the BPF 14 extracts the 2.04 MHz component in a narrow band, not only the DC component but also the noise component that causes the malfunction is removed. Further, the DC component of the ghost in the NRZ part and the ghost in the fsc part are removed by the BPF 14, and the ghost of the 2.04 MHz component included in the edge of the NRZ part is strong because the confirmation signal part is temporally separated from the NRZ part. Ghosts are less likely to exist, so they are less susceptible to ghosts.

The edge detection circuit 16 includes a code extraction circuit 15
The rising or falling edge of the input code bit is detected. The edge detection circuit 6 can be configured by a simple circuit that ANDs or ORs a sign bit that is an input signal and a signal that is delayed by a predetermined time by delaying the sign bit by one clock in a flip-flop.

Then, the timing signal generation circuit 17 decodes the EDTV2 signal by using the rising edge (or the falling edge) detected by the edge detection circuit 16 as a reference timing within the period of the gate signal input from the gate signal generation circuit 12. Generates the timing signals needed for. The EDTV2 decoder 18 uses the timing signal input from the timing signal generation circuit 17 to E
Decode the DTV2 signal.

Here, an example of a specific configuration of the timing signal generating circuit 17 is shown in FIG. 2, and its configuration and operation will be described. In FIG. 2, the input EDTV2 signal is input to the switch 171, and the edge signal output from the edge detection circuit 16 is input to the switch 173.
The gate signal indicating the vicinity of the 50% falling point of the first bit B1 of the identification control signal output from the gate signal generation circuit 12 controls the switch 171 to turn on / off, and the identification control signal output from the gate signal generation circuit 12 is output. The gate signal which indicates the part of the sine wave of 2.04 MHz from the 25th bit B25 to the 27th bit B27 which is the confirmation signal part of FIG.

The EDTV2 signal gated by the gate signal indicating the vicinity of the 50% falling point of the first bit B1 is input to the comparator 172. Comparator 1
Reference numeral 72 compares the input signal with the 50% level (20IRE) of the first bit B1 to detect the 50% falling edge. The detected edge is input to the flip-flop 175.

On the other hand, the edge signal gated by the gate signal indicating the 25th bit B25 to the 27th bit B27 is input to the 7-clock counter 174. By the way, the edge signal output from the edge detection circuit 16 is a rectangular wave having a fundamental frequency of 4 fsc / 7. 4 fs A / D conversion by A / D converter 13 at input
When performed at a rate of c (1.41818 MHz), the edge signal has 7 clock cycles. Therefore, if the 7-clock counter 174 is reset by the edge signal gated by the switch 173, the 7-clock counter 174 continuously obtains a rectangular wave having a fundamental frequency of 4 fsc / 7. That is, the 7-clock counter 174 continuously reproduces one cycle of the confirmation signal of the identification control signal with reference to the input edge signal.
This signal is input to the flip-flop 175 as a clock.

Then, the flip-flop 175 latches the 50% falling edge detected by the comparator 172 by using the signal of 7 clock cycles from the 7 clock counter 174, and uses this as the reference timing. The timing signal generator 176 generates a timing signal necessary for decoding the EDTV2 signal based on the reference timing input from the flip-flop 175.

As described above, the discrimination control signal processing circuit of the present invention does not cause a problem that the reference timing is changed by noise, ghost and slight deviation of adjustment, and has a simple structure and high-accuracy reinforcement signal decoding. It is possible to obtain a reference timing for.

[0025]

As described above in detail, the discrimination control signal processing circuit of the present invention includes the first gate signal for extracting the vicinity of the 50% fall of the first bit in the discrimination control signal and the discrimination control signal. The second to extract the confirmation signal part
A gate signal generation circuit for generating a gate signal of, a filter for extracting a confirmation signal portion in the identification control signal,
A code extraction circuit for extracting the code of the signal extracted by the filter, an edge detection circuit for detecting the rising or falling edge of the code extracted by the code extraction circuit, and an edge detected by the EDTV signal and the edge detection circuit. Since a signal is input, and a timing signal generating circuit that generates a reference timing by gated these signals by the first and second gate signals is provided,
It does not cause a problem that the reference timing changes due to slight deviation of noise and ghost, and furthermore,
It is possible to obtain a highly accurate reference timing for decoding the reinforcement signal with a simple configuration. Therefore, the EDTV2 signal can be stably decoded.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a block diagram showing a specific configuration of a timing signal generation circuit 17 in FIG.

FIG. 3 is a block diagram showing a conventional example.

FIG. 4 is a diagram showing an identification control signal in the EDTV 2.

[Explanation of symbols]

 11 Sync Separation Circuit 12 Gate Signal Generation Circuit 13 A / D Converter 14 Bandpass Filter 15 Code Extraction Circuit 16 Edge Detection Circuit 17 Timing Signal Generation Circuit 18 EDTV2 Decoder 171, 173 Switch 172 Comparator 174 7 Clock Counter 175 Flip-Flop 176 Timing Signal generator

Claims (2)

[Claims] 1. A compatible with NTSC color television transmission system, a wide aspect image is used as a main picture portion, and non-picture portions are provided above and below the main picture portion, and a reinforcement signal is provided in the non-picture portion or the main picture portion. And a discrimination control signal processing circuit for processing the discrimination control signal in an EDTV signal of a letterbox format in which the discrimination control signal is transmitted. A gate signal generating circuit for generating a gate signal of the identification control signal and a second gate signal for extracting a confirmation signal portion of the identification control signal; a filter for extracting a confirmation signal portion of the identification control signal; And a rising edge or falling edge of the code extracted by the code extracting circuit. Edge detection circuit for detecting the edge, and the EDTV signal and the edge signal detected by the edge detection circuit are input, and these signals are input to the first and second signals.
An identification control signal processing circuit, comprising: a timing signal generation circuit that gates with a second gate signal to generate a reference timing. 2. The timing signal generating circuit, a counter for continuously generating a confirmation signal in the identification control signal with reference to the edge signal output from the edge detection circuit, and a first bit in the identification control signal. 2. The discrimination control signal processing circuit according to claim 1, further comprising: a comparator that detects the vicinity of the fall of 50% of the above, and a flip-flop that latches the output of the comparator using the output of the counter as a clock.