JPH0746440A - Synchronization detection circuit - Google Patents

Abstract

PURPOSE:To surely detect a synchronizing signal so as not to fail in the detection of a first synchronizing signal when the synchronization of an input video signal is switched because malfunction prevention due to noise is operated and synchronization locking slows down when a receiver side fails in the detection of the first synchronizing signal. CONSTITUTION:The circuit is provided with newly a means 9 detecting a frame synchronizing signal FP from an analog video signal. A timing signal to predict an arrival position of the FP is generated based on the detected FP. When a digital frame synchronization detection circuit 4 detects the FP, the circuit 4 receives a prediction timing signal and detects the FP based on the prediction timing to make sure and quick FP detection.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sync detecting circuit in a television receiver, and in particular, after converting an analog signal transmitted by the MUSE transmission method using a positive polarity synchronizing signal into a digital signal. The present invention relates to an improvement of a sync detection circuit which digitally detects a sync signal.

[0002]

2. Description of the Related Art There is a MUSE transmission system as a system for band-compressing and transmitting a wide band high-definition signal. In this MUSE transmission method, the high-definition signal is subjected to analog band transmission as a digital band-compressed sample value. For this reason, it is necessary for the receiver side to accurately perform resampling at the time of reproduction, and therefore the sampling clock must be stably reproduced.

Further, in order to effectively use the transmission frequency band, a positive sync signal is used as the sync signal so that the amplitude of the sync signal is also within the amplitude range of the video signal. In order to reproduce the accurate resampling clock based on this positive sync signal, the receiver does not need to input (receive)
After converting the analog signal to be converted into a digital signal, a method of digitally detecting the synchronizing signal is used.

As a specific example of this prior art, Japanese Patent Laid-Open No. 59-59
There is a synchronization detection method of a television receiver for receiving a dot interlaced video signal described in Japanese Patent Publication No. 221091. Hereinafter, a synchronization detection circuit as this conventional example will be described.

FIG. 6 is a block diagram showing an example of a conventional synchronization detecting circuit in the above meaning. As can be seen in the figure, such a conventional sync detection circuit has an input analog MU.
An analog-to-digital conversion circuit (hereinafter, may be abbreviated as ADC) 3 for converting the SE signal into a digital MUSE signal, and a frame synchronization signal (hereinafter, F in the meaning of a frame pulse) from the converted digital MUSE signal.
And a digital frame synchronization detection circuit 4 for detecting P).

A horizontal synchronization detection circuit 5 for extracting a horizontal synchronization signal (hereinafter sometimes abbreviated as HD) portion and the FP detected by the digital frame synchronization detection circuit 4.
An internal sync signal generation circuit 6 for generating an internal HD whose timing is set by a phase comparator 7 for comparing the phase difference between the internal HD and the HD of the incoming MUSE signal detected by the horizontal sync detection circuit 5. , And a clock generation circuit 8 for generating a clock whose phase is controlled by the comparison output of the phase comparator 7.

That is, a characteristic FP pattern is detected by the digital frame synchronization detection circuit 4 from the digital MUSE signal converted by the ADC 3, and the HD generation position is determined by the internal synchronization generation circuit 6 based on this.
On the other hand, the horizontal sync detection circuit 5 extracts the HD of the incoming MUSE signal. The phase comparator 7 compares the phase of the extracted HD of the incoming MUSE signal with the internal HD generated by the internal sync generation circuit 6, and the clock generator 8
, And an accurate resampling clock is guided from the clock generator 8 to the ADC 3.

[0008]

In the above-described conventional sync detection method, when capturing a sync signal, the FP is first detected by the digital frame sync detection circuit 4, and the position of the HD is calculated by this to detect the horizontal sync. The internal H generated by the internal sync signal generation circuit 6 after the HD detection is performed by the circuit 5.
A phase comparator 7 performs a phase comparison between D and the calculated HD to form a PLL (face locked loop circuit).

In this system, once the synchronization is lost for some reason, the FP in the digital frame synchronization detection circuit 4
Since it will be redone from detection, wait for a while as protection against malfunction due to noise (if noise temporarily loses synchronization, wait for a while, if noise stops, the synchronization will be restored, so wait a while) As a result, when several frames of FP are not detected in succession, it is determined that the synchronization is lost (it is not temporarily lost due to noise, but is actually lost for some reason), and the PLL
The re-pull-in operation is started.

However, in this method, for example, the broadcasting signal is switched on the broadcasting station side or the input signal is switched on the receiving side, and the first FP detection is performed in an attempt to synchronize with the signal after switching. If an error is made, the protection against the malfunction caused by the noise is activated, the internal synchronization signal generating means 6 operates with the wrong FP for several frames, and then it is determined that it is necessary to newly detect the FP.
It takes several frames of time. Therefore, it takes time to pull in the synchronization.

An object of the present invention is to switch the broadcast signal on the broadcast station side, or to switch the input signal on the receiving side, and when the signal to be switched to is to be synchronized, the first FP detection is performed. An object of the present invention is to provide a synchronization detection circuit that can perform synchronization detection quickly without making mistakes.

[0012]

The above object is to provide an analog frame sync detecting means for detecting an FP (frame sync signal) having a characteristic pattern from an incoming analog video signal, and to detect by the analog frame sync detecting means. When the FP detection is performed by the digital frame synchronization detection circuit in the video signal converted into the digital signal by the analog-to-digital converter ADC, the detection period is predicted based on the prediction. It is achieved by controlling.

[0013]

The analog frame synchronization detecting means detects the FP by detecting the frequency component of the FP having a characteristic pattern and its power. The detected FP generates a prediction signal that predicts a period in which the FP in the video signal arrives, and guides it to a digital frame synchronization detection circuit that detects the FP from the digital signal converted by the analog-digital converter ADC. The digital frame synchronization detection circuit performs FP detection during this predicted period.

As a result, when there is a broadcast signal switching on the broadcasting station side, an input signal switching on the receiving side, etc., and when trying to synchronize with the signal of the switched destination, the first F
It is possible to prevent the P detection from being erroneous, and it is not necessary to take a long time of several frames to synchronously pull in the signal of the switched destination as in the conventional case. It is possible to speed up the pulling of synchronization.

[0015]

1 is a block diagram showing a first embodiment of the present invention. In the figure, 1 is an input terminal for an analog MUSE signal, 2 is an AGC and clamp control means for controlling the amplitude of the analog MUSE signal and clamping the signal level, and 3 is a digital MU for the analog MUSE signal.
Analog-to-digital conversion circuit (A
DC), 4 is a digital frame sync detecting circuit for digitally detecting FP (frame sync signal) from the digital MUSE signal, 5 is a horizontal sync detecting circuit, 6 is an internal sync generator, and 7 is a phase comparator of the horizontal sync signal. , 8 is a clock generator, and 9 is an analog frame synchronization detection circuit for detecting the FP from the analog MUSE signal.

The block SS takes in the digital video signal converted by the ADC 3, digitally detects the synchronizing signal multiplexed therein, and generates an internal synchronizing signal phase-locked with the detected synchronizing signal. The sync signal generating means outputs the clock signal to the clock generator 8 and includes a digital frame sync detecting circuit 4, a horizontal sync detecting circuit 5, an internal sync generator 6, and a phase comparator 7.

The circuit operation of the embodiment shown in FIG. 1 will be described below. An analog MUSE signal guided from an unillustrated tuner or the like to the input terminal 1 is adjusted by the AGC and clamp control means 2 to the ADC 3 in the subsequent stage so that its signal amplitude and DC voltage are adjusted within a predetermined range. To be done. The ADC 3 resamples the analog MUSE signal and converts it into a digital MUSE signal.

This resampled digital MU
The SE signal is guided to the digital frame sync detection circuit 4 and the horizontal sync detection circuit 5. The digital frame sync detection circuit 4 detects the FP (frame sync signal) in the digital MUSE signal and guides the FP timing signal to the internal sync generator 6.

The internal synchronization generator 6 generates various synchronization signals which are phase-synchronized with the guided FP timing signal. Of these various sync signals, the horizontal sync signal is guided to the horizontal sync detection circuit 5 as an HD extraction signal. The horizontal sync detection circuit 5 uses the digital signal MUSE based on this HD extraction signal.
HD (horizontal synchronization signal) is detected from the signal. The detected HD in the detected incoming MUSE signal and the internal HD generated by the internal synchronization generator 6 are guided to the phase comparator 7.

The phase comparator 7 detects the phase difference between the detected HD and the internal HD and guides it to the clock generator 8. The clock generator 8 controls the frequency of the generated clock so that the introduced phase difference becomes a certain constant value, and finally generates the clock synchronized with the detection HD. In this way, the clock generator 8
A PLL (phase locked loop circuit) that is synchronized with HD in the incoming MUSE signal is configured with the phase comparator 7 and the like, and the resampling clock guided from this clock generator 8 to the ADC 3 has an accurate resampling phase. Can be kept. The above circuit operation is the same as that of the conventional example.

In the present embodiment, the frequency of the FP (frame synchronization signal) having the characteristic pattern is further detected in the analog frame synchronization detection circuit 9 from the analog MUSE signal guided to the analog frame synchronization detection circuit 9. The FP is detected from the power, and based on the detected FP,
A gate signal (timing prediction gate signal) that predicts the timing at which the FP in the digital MUSE signal converted by the ADC 3 is guided is created in the digital frame synchronization detection circuit 4 and output to the digital frame synchronization detection circuit 4. .

The digital frame sync detection circuit 4 receives the timing prediction gate signal from the analog frame sync detection circuit 9 and outputs F in the digital MUSE signal.
FP detection can be performed only during a certain period when P arrives. The analog frame synchronization detection circuit 9 is frequency band limited in order to detect the FP from its frequency and power. In particular, this frequency band limitation is
It is possible to limit the narrow band so that it is limited to only the specific frequency component originally possessed by this, and most of the noise over the entire band in the MUSE signal is suppressed by this, and analog frame synchronization detection is not affected by noise or the like. Circuit 9 is F
P can be detected.

Next, FIG. 2 is a block diagram showing a concrete configuration example of the analog frame synchronization detection circuit 9 in the embodiment of FIG. In FIG. 2, 201 is an analog MUS
E signal input terminal, 202 is a bandpass filter for extracting only a specific frequency component of FP (frame synchronization signal), 203 is a level detector for extracting only FP having a specific power among signals extracted by the bandpass filter 202, 204 Is a timing prediction pulse generator that generates a timing prediction pulse indicating the timing at which the digital frame synchronization signal detection should be performed from the detected FP.

The FP signal format of the MUSE signal is shown in FIG. 3 and the signal component of the MUSE signal is shown in FIG. 4, and the operation of the analog frame synchronization detection circuit 9 of FIG. 2 will be described.

The frame pulse (FP) is applied to the first line and the second line of the 1125 lines constituting the MUSE signal of one frame, and Line 1 and Line in FIG.
It is inserted as shown as 2 and its signal format is
As can be seen in Figure 3, with a 2.025MHz square wave,
Moreover, it has the same signal amplitude as 100% (white-black) of the video signal amplitude. Then, FP appears as a signal including repetition of low, high, low, and high of 140 clocks (ck) of 1 line (480 clocks) and 1 clock (c).
It will be seen that k) is at a rate of 16.2 MHz.

Therefore, the frequency component of the MUSE signal is
As shown in FIG. 4, the MUSE video signal 401 is 8.1.
There are frequency components in the entire band up to around MHz, but most of the FP frequency components 402 are 2.025 MHz.
Exists in. Further, the noise 403 exists in all bands.
For this reason, the bandpass filter 202 of FIG. 2 performs band limitation 404 that allows a component centered at 2.025 MHz, which is a specific frequency component of the FP, to pass.

The 2.025 MHz rectangular wave signal extracted by the band pass filter 202 is guided to the level detector 203. The level detector 203 extracts a signal whose signal level has an amplitude equal to or higher than a certain fixed value from the extracted signal having the 2.025 MHz component, and further,
The case where the signal continues for two lines is detected as FP. As a constant value, the 100% (white-black) amplitude is 0.4V when the MUSE signal is FM-transmitted, and 0.8V which is twice the standard value when AM-transmitted.
An appropriate value that can extract this value may be used.

As a result, even if the video signal includes a 2.025 MHz component confusing with FP, the video signal (2.025 MHz component confusing with FP) has a maximum amplitude of 100% (white-black). It is extremely rare to have an amplitude, and in the case of a video signal, it is extremely rare that such a signal exists in only two lines, so that the FP can be detected well.

The timing prediction pulse generator 204 predicts the timing for detecting the FP of the digital MUSE signal guided to the digital frame synchronization detection circuit 4 from the detected FP and generates the timing prediction pulse for detecting the FP. As described above, in the present configuration example shown in FIG. 2, since the bandpass filter 202 performs the band limitation 404, most of the noise components 403 over the entire band of the MUSE signal are suppressed in the first stage as shown in FIG. Therefore, since the signal used for the signal processing in the subsequent stage contains almost no noise component, the analog FP detection in the analog frame synchronization detection circuit 9 can be performed without being affected by noise.

As described above, in the present embodiment shown in FIG.
Using the analog frame synchronization detection circuit 9, a timing prediction gate signal for predicting the timing at which the FP arrives at the digital frame synchronization detection circuit 4 is created and supplied to the digital frame synchronization detection circuit 4, and the digital frame synchronization detection circuit is supplied. In No. 4, by opening the gate at this timing and performing digital FP detection, it is possible to prevent erroneous FP detection due to noise or the like.
An internal HD from the internal synchronization generator 6 generated on the basis of
Detection H by the horizontal sync detection circuit 5 in the incoming MUSE signal
It is possible to reduce an erroneous operation that attempts to synchronize D and D, and it is possible to perform synchronization pull-in based on the FP detected more accurately.

This makes it possible to speed up the synchronization pull-in during MUSE reception. In the present embodiment, the method of detecting the FP from the frequency component and the amplitude of the analog frame synchronization detection circuit 9 has been described, but the present invention is not limited to this, and the characteristic of the FP is detected and detected. Any operation principle may be used as long as it is an analog frame synchronization detection circuit.

FIG. 5 is a block diagram showing a second embodiment of the present invention. The present embodiment is different from the embodiment of FIG. 1 in that a frame synchronization non-detection protection circuit 10 is provided after the digital frame synchronization detection circuit 4, and the FP detection signal from the analog frame synchronization detection circuit 9 is not synchronized with the frame. The other points are the same as those of the embodiment of FIG. 1 in that they are also led to the detection protection circuit 10, and the effect of suppressing the influence of noise and accelerating the synchronization pull-in by using the analog frame synchronization detection circuit 9 is the same. is there. Hereinafter, differences from the embodiment of FIG. 1 will be described.

When synchronization is established, the frame synchronization undetection protection circuit 10 counts whether or not FP undetection continues for a certain number of times, even if the FP is not detected by the digital frame synchronization detection circuit 4, Only when it is continuously undetected, a detection FP for performing new synchronization pull-in is guided to the internal synchronization generator 6 to start a new synchronization pull-in operation (if it is not continuously detected, until then) To keep the sync pull-in state).

Further, the frame synchronization non-detection protection circuit 10
Guides the detection FP for pulling in the synchronization to the internal synchronization generator 6 when the synchronization is not established. Even if the digital frame synchronization detection circuit 4 temporarily erroneously detects the FP due to noise or the like, the frame synchronization non-detection protection circuit 10 can disturb the internal synchronization up to that point if it is a one-time occurrence. Without it, the video signal can be received and displayed satisfactorily.

Further, in the present embodiment, the analog detection FP detected by the analog frame sync detection circuit 9 is also led to the frame sync undetected protection circuit 10 at the same time. In the frame synchronization non-detection protection circuit 10, if the detection FP led from the digital frame synchronization detection circuit 4 is interrupted for some reason, and there is an analog detection FP led from the analog frame synchronization detection circuit 9 even if FP is not detected. Does not count the number of times the FP has not been detected.

As a result, the analog frame synchronization detection circuit 9 which is resistant to noise even when FP undetection is likely to occur in the digital frame synchronization detection circuit 4 due to a lot of noise and the like.
By using together, it is possible to reduce the case where the continuous FP is not detected, to easily determine the case where the continuous FP is not detected when the synchronization of the MUSE signal is switched, and to perform the FP non-detection protection well. It becomes possible. Therefore, even if there is noise or the like, out-of-synchronization due to noise is not frequently caused to disturb the image, and a good image can be obtained.

As described above, also in the present embodiment, the analog frame synchronization detection circuit 9 is used for the digital frame synchronization detection circuit 4 for detecting the FP which is the reference for detecting the HD in the incoming MUSE signal. By predicting the timing at which the FP arrives and opening the gate in the digital frame synchronization detection circuit 4 at this timing to perform digital FP detection, it is possible to prevent erroneous detection of a different signal as noise due to noise or the like. It is possible to reduce a malfunction that attempts to synchronize the internal HD generated based on the FP with the detected HD in the incoming MUSE signal, and it is possible to perform the synchronization pull-in based on the more accurately detected FP.

This makes it possible to speed up the synchronization pull-in during MUSE reception. Further, in the present embodiment, when the analog detection FP detected by the analog frame synchronization detection circuit 9 is guided to the frame synchronization non-detection protection circuit 10 and the FP is not detected by the digital frame synchronization detection circuit 4 due to noise or the like, Also, by not counting the counter that counts the number of undetected consecutive FPs, it is possible to prevent erroneous determination as out-of-synchronization, prevent frequent out-of-synchronization due to noise, and disturb the image. It becomes possible to obtain.

[0039]

According to the present invention, a television of a system in which a received analog video signal is converted into a digital video signal, and a synchronizing signal multiplexed therein is digitally detected from the converted video signal and used. In John receiver,
The timing at which the sync signal is present is detected from the analog video signal, and the timing at which the sync signal is detected from the digital video signal converted by the analog-to-digital conversion means is predicted at this detected timing, and the sync signal is digitalized based on the predicted timing. Since it is detected automatically, there is an advantage that the influence of noise and the like can be suppressed and a correct synchronization signal can be detected quickly.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration example of an analog frame synchronization detection circuit in FIG.

FIG. 3 is an explanatory diagram showing a MUSE frame synchronization signal waveform.

FIG. 4 is a frequency characteristic diagram showing frequency components of a MUSE signal.

FIG. 5 is a block diagram showing a second embodiment of the present invention.

FIG. 6 is a block diagram showing an example of a conventional synchronization detection circuit.

[Explanation of symbols]

2 ... AGC and clamp control means, 3 ... Analog-digital conversion circuit (ADC), 4 ... Digital frame sync detection circuit, 5 ... Horizontal sync detection circuit, 6 ... Internal sync generator, 7 ... Phase comparator, 8 ... Clock Generator, 9 ... Analog frame sync detection circuit, 10 ... Analog frame sync non-detection protection circuit, 202 ... Band pass filter, 203
... Level detector, 204 ... Timing prediction pulse generator

Front page continuation (72) Inventor Tatsuo Nagata 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Inside the Hitachi Media Visual Media Laboratory (72) Inventor Yasutaka Tsuru 292, Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa Hitachi, Ltd. Visual Media Research Laboratories (72) Inventor Masaaki Matsukawa 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Hitachi Imaging Information Systems Co., Ltd. (72) Inventor Toru Hasegawa 2-2-1 Jinnan, Shibuya-ku, Japan Japan (72) Inventor Atsushi Yamakita, 2-2-1, Jinnan, Shibuya-ku, Tokyo Inside the Technical Development Center, Technology Bureau, Japan Broadcasting Association (72) Takashi Iwamoto, Jinnan, Shibuya-ku, Tokyo 2-1-1 Japan Broadcasting Corporation Technical Bureau Technology Development Center

Claims (2)

[Claims] 1. A television receiver of a system in which a received analog video signal is converted into a digital video signal, and a sync signal multiplexed therein is digitally detected from the converted video signal and used. An analog-to-digital converting means for converting an analog video signal into a digital video signal and outputting the digital video signal, and taking in the converted digital video signal, digitally detecting a sync signal multiplexed therein, and detecting the sync signal A synchronizing signal generating means for generating and outputting an internal synchronizing signal phase-locked with the above, and a clock used for sampling an analog signal in the analog-to-digital converting means on the basis of the generated synchronizing signal. A clock generating means and an analog signal for synchronizing the received analog video signal with the sync signal multiplexed therein. Analog sync signal detection means for generating a timing prediction pulse for predicting the timing position of sync signal detection in the sync signal generation means based on this, and the sync signal generation means A synchronization detection circuit, comprising: a synchronization signal generation means including a control means for controlling the detection period by the timing prediction pulse when detecting a synchronization signal multiplexed therein from a video signal. 2. A television receiver of a system in which a received analog video signal is converted into a digital video signal, and a sync signal multiplexed therein is digitally detected from the converted video signal and used. An analog-to-digital converting means for converting an analog video signal into a digital video signal and outputting the digital video signal, and taking in the converted digital video signal, digitally detecting a sync signal multiplexed therein, and detecting the sync signal Sync signal generating means for generating and outputting an internal sync signal phase-locked with the sync signal generating means, and when the sync signal generating means detects the sync signal multiplexed in the digital video signal, the presence or absence of the detection is judged by the judging means. If there is no detection, it is not judged as non-detection unless it continues and the internal synchronization signal with the phase synchronization is Synchronization protection means for not affecting the generation and output of the signal, and a clock used for sampling the analog signal in the analog / digital conversion means based on the synchronization signal generated in the synchronization signal generation means. , A clock generating means for generating and supplying, and a synchronous signal multiplexed therein from the received analog video signal are detected in an analog manner, and based on this, the timing position of the synchronous signal detection in the synchronous signal generating means is determined. Timing for predicting: An analog synchronizing signal detecting means for generating a predicting pulse; and the synchronizing signal generating means for detecting a synchronizing signal multiplexed therein from a captured digital video signal, the detection period thereof being the timing. The synchronization signal generation means including a control means for controlling by a prediction pulse; and the synchronization protection means The synchronization protection means receives the timing prediction pulse and detects one of the synchronization signal and the prediction pulse which is multiplexed when detecting the synchronization signal multiplexed in the digital video signal. And a synchronization detection circuit comprising: