JPH0360585A - Television receiver - Google Patents

Abstract

PURPOSE:To eliminate the need for the control by a synchronizing loop and to attain the discrimination of a television signal system at a high speed by utilizing the correlation of a frame pulse of a 1st television broadcast so as to extract the said frame pulse and using a counter circuit operated for the pulse period only so as to discriminate the system of the broadcast signal. CONSTITUTION:When a received signal is the MUSE system signal B and a frame pulse (a) of a 1st line is retarded by one line via a 1H delay circuit 11, the signal is inputted to a subtractor 12. In this case, a 2nd line frame pulse (b) is inputted to the subtractor 12, in which the arithmetic processing for preceding line vs. current line is implemented and a waveform of a frame pulse C is obtained by the correlation between the preceding line and the current line. The extracted frame pulse is inputted to a clock input terminal of a counter circuit 14 and pulses by 17-count are inputted to the said counter circuit 14. When the signal of the MUSE signal is inputted, the count of the counter circuit 14 overflows, and a pulse based on the overflow is outputted to a CPU 24.

Description

[Detailed Description of the Invention] [Industrial Application] The present invention relates to a television receiver capable of receiving two television broadcasts with different vertical synchronization signal formats.
In particular, the present invention relates to a television receiver capable of receiving both band-compressed high-resolution video signals and television standard system fs signals.

(Summary of the Invention) The present invention provides a first television broadcast including a predetermined number of consecutive and mutually inverted first and second frame pulses for vertical synchronization, and a first television broadcast that includes a vertical synchronization signal. In a television receiver capable of receiving a second television broadcast having a different format, a sampling means for extracting the frame pulse based on the vJ tangent line correlation of the received broadcast signal, and counting the start of the frame pulse, particularly counting the number of the pulses. and has a counter means that is reset at the end of the frame pulse, and the signal processing circuit of the television receiver is switched at high speed by determining the format of the received television broadcast by the count of the counter means. Furthermore, the manufacturing cost is kept low.

[Conventional technology]

Current standard television (for example, N
In the TSC system, the vertical frequency is 60 Hz, the number of scanning lines in one frame is 525, the video signal band is 4°2M1 (z, and the aspect ratio is 4:3).

In contrast to current television broadcasting, a new high-definition television system (hereinafter referred to as 1 (DTV)) has recently been introduced.
Development of a new method (referred to as a method) is underway. This HDTV
DTV system TSC system (7) 5 (Requires a video signal band of about fj. Therefore, due to the band limit when performing satellite broadcasting, the HD TV system is
E (llultiple Sub-Nyquist
Bandwidth compression called the -Sampletag Encoding method is performed.

By the way, in the MUSE method, a vertical synchronizing signal such as a vertical synchronizing pulse that appears together with an equivalent pulse during the vertical blanking period is not used as in the NTSC method, but a frame pulse is used. This frame pulse is inserted using two consecutive lines in every frame,
16.2M1 (17.5 inverted at 4 clock intervals of z
This is a square wave having a 100% level of a video signal consisting of a pair of patterns (see FIG. 6).

-4, in a receiver that receives a MUSE signal, synchronization detection is performed using the frame pulse. Its synchronous detection, for example! This is done using a synchronization detection block consisting of two LSIs, and the synchronization detection block is
It is connected to input the output of an A/D converter that digitizes the MUSE baseband signal.

As a technique for performing synchronization detection of such MLISE method, for example, Japanese Patent Laid-Open No. 61-261973 discloses an A/D
A frame sync separation circuit is shown for separating the frame sync pattern from the signal from the converter. This frame synchronization separation circuit has voltage II! A self-contained oscillator is used to create a synchronization loop for frame synchronization.

[Problem to be solved by the invention]

The television receiver, which is capable of receiving both standard television signals and HD TV system No. 13 as described above, uses the difference in vertical synchronization signals to determine which signal is being received and to determine which signal it is receiving. It is necessary to switch the signal processing circuit depending on the result.

However, in the technique described in the above publication, which extracts a signal after A/D conversion, separates a frame synchronization signal from it, and applies phase synchronization to it, it takes time to acquire phase synchronization. High-speed discrimination is not possible, and it takes time to switch the signal processing circuit. Also,
If phase synchronization is applied, the circuit becomes complicated, leading to high manufacturing costs.

SUMMARY OF THE INVENTION In view of these technical problems, it is an object of the present invention to provide an inexpensive television receiver that can quickly discriminate between two different television broadcast signals.

(!!Means for Solving K11l) The television receiver of the present invention for achieving the above-mentioned object has first and second pulses for vertical synchronization each consisting of a predetermined number of consecutive pulses and having opposite polarities. It is possible to receive a first television broadcast including two frame pulses and a second television broadcast having a vertical JIJLF format different from that of the first television broadcast. Here, the first television broadcast is a high-definition television signal, for example, a MUSE system broadcast, but other systems may also be used. The second television broadcasting may be of any type as long as it has the second frame pulse pattern; for example, the NTSC system may be used, but it may also be the I'AL system or the SECAM system.

Furthermore, the television receiver of the present invention includes a sampling means for extracting the frame pulses based on the correlation between adjacent lines of the received broadcast signal, and a sampling means that starts counting the number of pulses at the start of the frame pulse and at the end of the frame pulse. The system has a counter means which is reset at the time of the broadcast, and the system of the received televised broadcast is determined by the count of the counter means.

Here, the extraction means can be configured using, for example, a one-line delay circuit in order to utilize the correlation between adjacent lines, and the difference signal between the output of the delay circuit and the undelayed signal is A frame pulse serving as a vertical synchronization signal for the first televised broadcast can be extracted from the frame pulse. A bandpass filter may be added to this extracting means to allow only continuous frame pulses to pass.As a configuration for operating the counter means in conjunction with the pulses, for example, the output pulse width may be equal to or less than the frame. It is possible to use a mono multi-circuit for more than one pair of pulses, input the pulses into the mono multi-circuit, and input the output to the enable of the counter means.

[Effect]

In the television receiver of the present invention, the pulse obtained by correlating the frame pulse of the first telecast signal is directly input to the counter means and used for discrimination, so that the synchronization loop etc. This eliminates the need for high-speed switching of the signal processing circuit based on the signal from the counter means.

〔Example〕

Preferred embodiments of the present invention will be described with reference to the drawings.

(Example of Configuration of Television Receiver) First, the overall configuration of the television receiver of this embodiment will be described with reference to FIG. 5.

The television receiver of this embodiment is a receiver capable of receiving both MUSE system signals and NTSC system signals. Its configuration includes an antenna 21 that can receive radio waves from a broadcasting satellite, and a baseband signal is obtained by a chainer 22 to which the antenna 21 is connected. This baseband signal is LPF (low pass filter)
The signal is sent to the signal discrimination circuit 1 and the changeover switch 24 via 23.

Here, as described later, the signal discrimination circuit l is connected to the MUSE
This circuit distinguishes between NTSC system signals and NTSC system signals, and outputs signals for switching each signal processing circuit of the receiver. A signal that has not been A/D converted is input to the signal discrimination circuit 1, and its output is sent to the CPU 20.

In this CI'U 20, a signal for switching the changeover switch 24 is generated based on the output from the signal discrimination circuit 1, and a signal for controlling other parts of the signal processing circuit is also generated.

The changeover switch 24, which is switched by a signal from the CPU 20, selectively sends the received signal to the MUS Snake decoder 25 and the NTSC decoder 26. If the received signal is a MUSE system signal, demodulation is performed by the MUSE decoder 25, and the received signal is converted into NT
If it is an SC system signal, demodulation is performed by the NTSC decoder 26. These MUSE decoders 25. N.T.
The SC decoder 26 performs the necessary signal processing according to each method, and although not shown, it is possible to obtain the video and audio of either high-definition television or current standard television. It turns out.

In addition, MUSE decoder 25 and NTSC system: I-da 2
6 may be such that a part of the circuit overlaps,
The changeover switch 24 is not limited to being disposed at the input section of each decoder 25, 26, and the signal processing circuit to be switched in this way can be configured as in a specific example described later.

(MUSE system signal) Next, the MU demodulated by the television receiver of this embodiment
The frame pulse of the SE method will be explained with reference to FIGS. 6 and 7.

First, FIG. 7 is a diagram showing information of 1 frame of a MUSE system signal. In FIG. 7, the numbers on the vertical axis are line numbers, and the numbers on the horizontal axis are sample numbers. Line number is 1-
Sample numbers 1 to 480 are assigned up to 1125. The first two lines of R include V [T (ver
With the tical 1nterval tes0 signal,
Contains a hexaframe pulse signal extracted by the signal discrimination circuit 1, and this frame pulse signal causes the MUSE
It is determined whether it is a method or not. Horizontal synchronization signals are sent to the first 1 to 12 points of each line. In addition, the two Cs (color difference)
The signals are specially compressed, and the RY signal is multiplexed on the odd numbered lines and the BY signal is multiplexed on the even numbered lines in a line-sequential manner. The Y signal has a line delayed by 4 Tf from the C signal, and is assigned 374 points in the horizontal direction.

FIG. 6 shows the waveform of the frame pulse signal. A frame pulse is a signal that appears on the first line and the second line of one frame, respectively. The pattern consists of a square wave with a level of 100% of the video signal that is inverted at 4GK (clock) intervals of 16.2 MHz, and its pulses appear over 17.5 pairs (140 sample points). The waveforms of the frame pulses of the 11th line and the frame pulses of the second line have opposite polarities. In this way, the first. Since the frame pulses of the second line do not have a high correlation like normal lines, it is rare that the same waveform as the frame pulses of two lines occurs, and these frame pulses are used for frame synchronization. can be taken.

(Configuration Example of Signal Discrimination Circuit) The signal discrimination circuit I, as shown in FIG.
This circuit receives the output from the LPF 23 through the LPF 23 and determines whether it is a MUSE type signal or not. Specifically, it has the configuration shown in FIG. 1, and the ff number discrimination circuit 1 includes an IH (1 line) delay circuit 11. Subtractor 12. It has a configuration consisting of a mono-multi-times Jm13° counter circuit 14.

As shown in FIG. 1, the signal from the LPF 23 is sent to the IH delay circuit 11, and in particular to the subtracter 12.

The output of the delay circuit 11 of 11 is also input to this subtracter 12, so that the subtracter 12 performs subtraction processing between the current line and the previous line.

The output of the subtracter 12 is input to a monomulti circuit 13. This monomulti circuit 13 is a circuit that outputs a predetermined pulse width τ according to a pulse input, and as shown in FIG. , the output of pulse width τ1 (c), (C
), the output pulse width τ, is 8CK+α, and for a continuous square wave input of 4CK, the output (
b) and (C) will occur consecutively. Therefore,
When a signal that is inverted in consecutive 4CK units is input to the monomulti circuit 13, the high level state continues from the time the pulse input starts, and after the last pulse input, the output level falls after BCK+α has elapsed. .

The output of the subtracter 12 is not only input to the monomulti circuit 13 but also supplied to the clock input terminal of the counter circuit 14. The output signal of the monomulti circuit 13 is supplied to an enable terminal of the counter circuit 14. In this counter circuit 14, the number of pulses input to the clock input terminal is counted only when the signal from the mono multi circuit 13 is at a high level, and when the signal from the mono multi circuit 13 is at a low level, the counter circuit 14 is counted. be placed in a reset state. This counter circuit 14 can be, for example, a hexadecimal counter, and is configured to detect its overflow and output it to the signal discrimination circuit 1. In addition, as a modification example, as shown in FIG.
4 counting counting 2. All outputs of count 4 and count 8 are A
It is also possible to input the signal to the ND circuit 15 and use the output of the AND circuit 15 as the output of the signal discrimination port IYal.

The output of the counter circuit 14 (or AND circuit 15) is
It is supplied to the CPU 20 as the output of the signal discrimination circuit 1. The CPU 20 generates a signal for switching the selector switch 24 shown in FIG. 5, and further generates a signal for controlling the signal processing circuit to be switched in the television receiver of this embodiment.

(Example of Operation of Signal Discrimination Circuit) Next, an example of operation of the signal discrimination circuit 1 of the television receiver of this embodiment will be described with reference to FIG.

Assume that the received signal is a MUSE signal. When the frame pulse (a) of the first line is delayed by one line through 18 delay circuits 11, the subtracter 12
Enter. At this time, the frame pulse (b) of the second line is input to the subtracter I2, and the subtracter 12 performs arithmetic processing between the previous line and the current line, and due to the correlation between the previous line and the current line, (C ) is obtained.

The frame pulse waveform (C) is assumed to be the same amplified frame pulse as it is, and is 16,2M1l.
It is assumed to be a square wave that is inverted at 4CK intervals of z. Further, the frame pulse waveform (C) has 17.5 consecutive pairs.

The extracted frame pulse of waveform (C) is input to the monomulti circuit 13 and generates an enable signal (A) for activating the counter circuit 14. This enable signal (A) is a signal in which the next pulse is successively formed before a pulse with a pulse width τ falls in response to a frame pulse whose polarity is inverted in units of 4 CK. It rises at the start and falls at the end of the frame pulse. This enable signal (a) is input to the enable terminal of the counter circuit 14. When the enable signal (a) is at a high level, the counter circuit 14 is enabled to count, and when the enable signal (a) is at a low level, the counter circuit 14 is placed in a reset state.

The extracted frame pulse shown in waveform (C) is not only input to the monomulti circuit 13 but also input to the counter circuit 1.
4, and 17 pulses are input to the counter circuit 14. While the frame pulse is clocked in this way, the enable signal (B) is held at a high level, and the counter times 1m.
At 14, pulse counting is performed. Since the counter circuit 14 is a hexadecimal counter, when a MUSE method signal containing consecutive pulses for 17.5 bears is input, the count of the counter circuit 14 overflows, and a pulse (e) based on the overflow is sent to the CPU 20. Output.

As shown in FIG. 2, when 15 pulses are input through the AND circuit 15, A
The output of ND151115 becomes high level, and CP
Output to U20. After outputting such a pulse (e), the enable signal (d) falls and the counter circuit 1
4 is put into a reset state.

In the television receiver of this embodiment, the CPU 2
By the pulse (e) input to 0, selector switch 2
4 and other signal processing circuits are switched. M.U.
In the case of SE type signals, pulses from the counter circuit 14 are output to the CPU 20 every 1/30 seconds. Therefore, C
The PU 20 can also switch the circuit of the television receiver after receiving the pulse from the counter circuit 14 multiple times.

Next, when receiving an NTSC signal, the NTSC
In No. 13 of the C method, there is no part where the signal is emphasized by subtraction processing between adjacent lines, so even if the counter circuit 14 is activated, the probability of counting close to overflow is extremely small, and furthermore, The enable signal from the monomulti circuit 13 causes the counter circuit to immediately go to the counter circuit if the pulses are not continuous! 4 is reset.

Therefore, the output of the signal discrimination circuit 1 is highly reliable, and a pulse is output only when a MUSE type signal is input.

In the signal discrimination circuit 1 operating in this manner, discrimination is performed using the correlation of frame pulses in particular, and a PLL is not required, so that high-speed signal discrimination is possible. In addition, the circuit configuration can be simplified by not using a PLL, and the television receiver can be manufactured at low cost.

(Specific Example of Television Receiver) Next, with reference to FIG. 8, an example of a signal processing circuit to be used and switched in the television receiver of this embodiment will be described.

This signal processing circuit includes switches 31, 32, 33, and 34.
．． 35 is configured to be switched by a control signal from the CPU 20 described above, and the MUSE system signal and the NTSC system signal are selectively visualized by a common picture tube 47.

First, the terminal 41 is connected to a signal related to the MUSE method and a signal related to the NT
A signal related to the SC method is selectively supplied to this terminal 4.
A horizontal synchronization signal is extracted from the signal supplied to the horizontal synchronization separation circuit 51.

This horizontal synchronization separation circuit 51 itself is also enabled by the CPU 20 to handle different horizontal frequencies.

The horizontal synchronization signal separated by the horizontal synchronization separation circuit 51 is made into a burst gate signal via a delay circuit 52, and this burst gate signal is supplied to a burst gate circuit 53 to obtain a burst signal.

This burst (No. 8) is supplied to the NTSC decoder 42N and used for demodulating the color signal.

The horizontal synchronization signal separated by the horizontal synchronization separation circuit 51 is further supplied to a vertical synchronization separation circuit 71, and due to the vertical FJI signal of 607 from the vertical synchronization separation circuit 71, the horizontal synchronization signal is separated by 6° from the vertical oscillation circuit 72. A vertical oscillation output of 11t is obtained. This is supplied to the vertical output circuit 73 to obtain a vertical deflection output, which is supplied to the vertical deflection coil of the deflection device 48.

Switch 3 switched by output from CPU 20
The input terminals of the I(D TV decoder 42H and the NTSC decoder 42N are connected to the input terminal 1. The output of the HDTV decoder 42H is directly input to the switch 32. The signals input to these switches 32 are the Y signal, the RY signal, and the BY signal, and after one decoder is selected by the switch 32, the RGB signal, amplifier 46
It is sent to the electron gun of the picture tube 47 via R, 46G, and 46B.

Similarly, the switch 33, which is switched by the output from the CPU 20, has Y of each decoder 4211°42N.
fJ is supplied and selected by the switch 33. From the output of the switch 33, a synchronous separation circuit 60
A horizontal synchronizing signal is extracted and sent to the AFC circuit 68. This AFC circuit 68 includes a horizontal output circuit 66, horizontal oscillation circuits 61. Phase comparator 62. It is composed of a low-pass filter 63, and an oscillation frequency correction circuit 65 is connected to the horizontal oscillation circuit 61 via a switch 34.
A horizontal deflection width setting circuit 64 is connected to the horizontal output circuit 66 via a switch 35. These oscillation frequency correction circuits 6
5, the horizontal deflection width setting circuit 64, and switches 34 and 35, it is possible to cope with the difference in horizontal frequency and aspect ratio between the MUSE system and the NTSC system. The horizontal deflection output of the horizontal output circuit 66 is then sent to the horizontal deflection coil of the deflection device 48. Further, this horizontal deflection output is supplied to a high voltage generation circuit 6 which has a separate converter.
7, and the high pressure from this high pressure generating circuit 67 is supplied to the picture tube 47.

The signal processing circuit having such a configuration operates as follows.

First, if a MUSE signal is being received,
As mentioned above, the pulse from the signal discrimination circuit 1 is sent to the CPU 2.
The switches 31 to 35 are switched to the H side by the in signal from the CPLJ20. Then, the received signal is sent to the II D TV decoder 42.
H and is decoded via matrix 45.H. amplifier 4
Signals for displaying high-definition images are sent to the picture tube 47 from 6R, 46G, and 46B.

In addition, in the case of a MUSE method signal, the horizontal oscillation circuit 6
The oscillation frequency of 1 is set to 33.75 kHz, 33,
A horizontal deflection output of 75 k Ftz is obtained, and a horizontal deflection output having the required aspect ratio is obtained. This horizontal deflection output is supplied to a horizontal deflection coil.

Next, when an NTSC signal is received, no pulse is output from the signal discrimination circuit I, and all switches 31 to 35 are switched to the N side by control No. 13 from the CPU 20. When receiving this NTSC signal,
From the burst gate time 1s53, the burst signal is NT
The signal is sent to the SC decoder 42N. Also, by switching the switch 31, the NTSC decoder 42N
Composite signal is input.

In the NTSC decoder 42N, the required Y.

121g of the C signal is performed, and in the memory 43, according to the control signal from the clock pulse generation circuit 44, for example, N
The signal of one line of the output signal of the TSC decoder 42N is 1
It is converted into a 1DTV signal and extracted. This signal is matrix 45. The signals are sent from amplifiers 46R, 460, and 46B to a picture tube 47, where they are visualized.

Further, in the AFC circuit 68, the switches 34 and 3 are respectively
5 is switched to the N side, the horizontal oscillation frequency is doubled to 31.468 kllz, and a horizontal deflection output with an adjusted aspect ratio is output. This horizontal deflection output is sent to the horizontal deflection coil of deflection device 48. In addition, the vertical deflection output is also sent to the vertical deflection coil, resulting in a screen with twice the normal number of scanning lines.

〔Effect of the invention〕

The television receiver of the present invention makes use of the correlation between the frame pulses of the first television broadcast, extracts the frame pulses, and determines the format of the broadcast signal using a counter circuit that operates only during the period of the pulses. This eliminates the need for @ control using a synchronization loop, and enables high-speed discrimination of television signal formats. Further, the circuit configuration itself can be simplified compared to the conventional one, and the entire device can be manufactured at low cost.

[Brief explanation of drawings]

1st rj! J is a block diagram showing a signal discrimination circuit used in an example of the television receiver of the present invention, FIG. 2 is a circuit diagram showing another example of the counter means of the signal discrimination circuit according to the present invention, and FIG. 3 is a block diagram showing a signal discrimination circuit according to the present invention. FIG. 4 is a waveform diagram for explaining the operation of the monomulti circuit according to the present invention, FIG. 4 is a waveform diagram for explaining an example of the operation of the signal discrimination circuit according to the present invention, and FIG. 5 is an example of the television receiver of the present invention. 6 is a waveform diagram showing the frame pulse pattern of the MUSE method, FIG. 7 is a schematic diagram showing information for one frame of the MUSE method, and FIG. 8 is a diagram showing the frame pulse pattern of the MUSE method. 1 is a block diagram showing an example of a signal processing circuit used in a television receiver. FIG. l... Signal discriminator circuit 11... Delay circuit 12... N subtractor 13... Mono multi circuit 14... Counter circuit

Claims (1)

[Scope of Claims] A first television broadcast including first and second frame pulses for vertical synchronization each consisting of a predetermined number of consecutive pulses and having opposite polarities; is a television receiver capable of receiving a second television broadcast having a different form of vertical synchronization signal, and includes a sampling means for extracting the frame pulse based on the correlation between adjacent lines of the received broadcast signal; comprising counter means that starts counting the number of pulses at the start and is reset at the end of the frame pulse;
A television receiver characterized in that the system of the received television broadcast is determined by the count of the counter means.