JPH086681A - Power saving control system - Google Patents

Abstract

PURPOSE:To perform state transition control over respective CPUs and individual power saving control corresponding to the operation state so that the power consumption of a system in a stand-by state is suppressed without spoiling the consistency of the whole operation. CONSTITUTION:A multiprocessor system equipped with plural CPUs is provided with a processor bus monitor part 156 which detects the operation states of the individual CPUs by monitoring a processor bus and a system state monitor part 101 which monitors the load state of the system. Further, the system is provided with a system state control part 102 which controls the power consumption of the individual CPUs according to a report from the system state monitor part 101. If a state wherein the load on a specific CPU is small because of a key input waiting state continues, that is informed by the processor bus monitor part 156 to the system state control part 102, which sends a command to a clock switching part 153 to switch the clock supplied to the CPU to a low frequency.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power saving control system, and more particularly to a power saving control system applied to an information processing apparatus adopting a multiprocessor system.

[0002]

2. Description of the Related Art Conventionally, in an information processing device such as a notebook type small personal computer or a word processor, for example, as shown in FIG. A power control system is adopted.

FIG. 24 is a block diagram showing an example of a conventional power saving control system, which is disclosed in Japanese Patent Laid-Open No. 4-130510. In the figure, a system bus 11 includes a CPU 7, a keyboard 3, a key input waiting determination means 1, a ROM 8, a RAM 9, and an output device 1.
0 is connected to each, and the system always detects that the keyboard is waiting for input from the keyboard, and switches the clock supplied to the CPU1 to a clock with a lower frequency than during normal operation while in the input waiting state. , The power consumption of the system in the input waiting state is reduced.

That is, the key input waiting determination means 1 connected to the system bus 11 is operated when the CPU 7 executing the application program stored in the RAM 9 calls the key sense routine stored in the ROM 8. The input waiting signal 35 is activated. Further, while the key sense routine is continuously called, the key input waiting determination means 1 holds the key input signal 12 in the active state. Then, when the key input signal 12 is continuously in the active state for a predetermined time or longer, the control means 2 sends the clock switching signal 13 to the switching means 4. In response to this, the switching means 4 switches between the high clock 5 and the low clock 6 to switch to C
Send it to PU1. Thus, as one of the methods for reducing the power consumption, a method of detecting that the system is in a standby state and switching the operating clock frequency of the CPU to a lower frequency has been conventionally known. As a recent trend, the Nikkei Electronics magazine September 13, 1993 issue (No. 590:
As described in P103-123), even in general information processing equipment that operates on a commercial power source in the US Energy Star Program and the like, there is a demand for reducing power consumption in the standby state.

On the other hand, in the field of small information processing equipment, multiprocessor systems equipped with a plurality of CPUs are becoming popular. Generally, in these multiprocessor systems, since a plurality of CPUs having high computing performance and high power consumption are mounted, the power consumption of the entire system becomes large. Therefore, for the purpose of downsizing the power supply circuit, for example, a power supply system in a multiprocessor system as shown in FIG. 25 has been proposed.

FIG. 25 is a block diagram showing an example of a power supply system in a conventional multiprocessor system, which is disclosed in Japanese Patent Laid-Open No. 4-155512. In the figure, the main power supply unit 21 supplies the N processors 22 _{1 to} 22 _{N with} a DC voltage NV ₁ that is N times the rated voltage V ₁ to be supplied to each processor. The constant voltage circuit 23 is provided in each of the processors 22 _{1 to} 22 _N.
1 to 23 _N each supply the voltage V ₁ . That is, the configuration of the power supply device is simplified by changing only the number of constant voltage circuits and the voltage of the main power supply unit according to the number of processors to be mounted. As described above, in the multiprocessor system, since the power consumption differs depending on the number of processors forming the system, it is necessary to provide an appropriate power supply device according to the number of processors.

In addition to the above-mentioned conventional technique, a CPU equipped with a power saving function has been announced in recent years from the beginning of manufacture.
As a processor with a built-in power saving function, for example, the Pentium processor of Intel Corporation in the United States is widely used. For the power saving function, see the data sheet "Pentium TM Family User's Manual Volume" issued by Intel Corporation.
1: Data Book ”Order Number 241428-003, published in 1994, pages 30-1 to 30-11.

[0008]

However, the above conventional power saving control system is intended for application to a single processor type information processing apparatus having a single CPU, and is a multiprocessor type information processing apparatus. Is not considered at all. For example, in a multiprocessor system, when a certain CPU calls a key sense routine, the key input waiting discriminating means connected to the system bus determines which C
It is impossible to determine whether it has been called by the PU, so the CP that should be the target of power saving control
There was a problem that U could not be specified.

Further, the above conventional power saving control system is
The operating system (hereinafter abbreviated as OS) is configured to be transparent to software, and power saving control is performed by dedicated hardware. However, in a multiprocessor system, the OS side performs power saving control by software. It is also necessary to do it. For example, multiple CPUs
When performing state transition control (normal state ← → standby state) of a multiprocessor system including a CPU, it is determined which of a plurality of CPUs the state is to be transited to, and the start or stop processing of the CPU is performed. Along with
It is necessary to manage the connected hardware resources logically. However, the conventional OS compatible with the multiprocessor system has a problem that such power saving control cannot be performed.

On the other hand, in the power supply system in the conventional multiprocessor system described above, since the power is constantly supplied to all the mounted CPUs, the operation of any CPU is stopped, or There is a problem that it is impossible to perform the processing required for power saving control, such as stopping the power supply to the CPU.

Further, in recent years, the power consumption of the main body of small-sized information processing equipment has increased, and the power consumption of the entire system has also increased, so that the increase in the power consumption of the entire system is a serious problem. Became. Therefore, for example, as in the Energy Star Program defined by the US Environmental Protection Agency, it is required to reduce the power consumption to a certain value or less during the standby time when the system is not used. However, recently, CPUs capable of relatively easily configuring a multiprocessor system are being announced one after another, and a multiprocessor system including a plurality of such CPUs usually consumes a large amount of power. Performing power saving control has become a more important issue than ever before. Therefore, particularly in a multiprocessor system in which the power consumption of each processor is large, a CPU operated at a time when the system is in a standby state
A method has been proposed for reducing power consumption by reducing the number of power supply lines (described in Nikkei Electronics magazine September 13, 1993, p103 to p123).

Further, when using the power saving function built in the CPU such as the Pentium processor described above,
There is no particular problem if the CPU is used alone,
In a multiprocessor system in which a plurality of the CPUs are operated at one time, there is a problem that sufficient consideration must be taken so that inconvenience does not occur in the operation of the entire system.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to solve the above-mentioned problems, and in a multiprocessor system having a plurality of CPUs, the consumption when the system is in a standby state without impairing the consistency of the operation of the entire system. An object of the present invention is to provide a power saving control system capable of performing state transition control of each CPU and individual power saving control according to its operating state so that the power becomes a certain value or less.

[0014]

To achieve the above object, a power saving control system of the present invention is a multiprocessor system including at least two CPUs,
A state monitoring unit that constantly detects the operating state of the system, and a state transition control (CPU operating state) for the designated CPU when the operating state of the system detected by the state monitoring unit changes beyond a predetermined boundary condition. The power saving control for changing the normal state from the standby state to the standby state and the state control means for performing a return control for changing the operating state of the CPU from the standby state to the normal state) are provided.

The state control means sequentially performs the state transition control for each CPU, and particularly in the power saving control, until the power consumption of the entire system becomes smaller than a predetermined minimum power, or
The power saving control is repeatedly performed until only one CPU is in the normal state.

Further, when the state monitoring means detects the power saving control start condition as a condition in which the system operating condition is below the specified value of the boundary condition, the operating condition of the system is specified by the boundary condition. When the state monitoring means detects that the value is below a certain value continues for a certain period of time, when the state monitoring means detects that the designated input means is in the input waiting state, etc. In addition, when the state monitoring means detects a condition in which the operating condition of the system exceeds the specified value of the boundary condition, the operating condition of the system exceeds the specified value of the boundary condition. When the state monitoring means detects that the state has continued for a certain period of time or more, the state monitoring means detects that there is an input operation to the designated input means. It can, is intended to define as such.

Further, as a concrete state transition control by the state control means, in the power saving control, the operation of the CPU is suspended by using a clock stop means provided in the CPU, while in the return control, the CPU is stopped. In the power saving control, the clock frequency supplied to the CPU is switched to a power saving frequency lower than that in the normal state, while in the return control, the clock frequency is switched to the frequency for the normal state. In the control, the power supply to the CPU is cut off to stop the CPU, while in the return control, the power supply to the CPU is restarted to restart the CPU. .

Further, as a specific detection process by the state monitoring means, a bus (system bus or processor bus and I / O bus) for relaying the specified value of the boundary condition to a signal exchanged between the constituent elements of the system. Of at least one of the above)
Detecting the load status of the bus at the present time as the operating status of the system, the specified value of the boundary condition is a specific value indicating the load status of the application execution in the entire system, and the load status of the application execution at the present time is the operating status of the system. The boundary value of the boundary condition, which is detected as, controls the state of the task queue or job queue for distributing the task or job that realizes the function of the application to each CPU, and the execution order of the task or job. With a specific value that represents the scheduling state, which is the state of the scheduler,
It is configured to perform processing such as detecting the current scheduling state as the operating state of the system.

Further, the state monitoring means and the state control means are provided inside an operating system compatible with a multiprocessor for generating and distributing task threads necessary for executing an application using a plurality of CPUs and for controlling scheduling. With the provision
The system load reference table for registering the prescribed value of the boundary condition in advance is provided in the firmware,
When registering or updating the specified value of the boundary condition, the system load reference table is read from the firmware onto the memory, and various setting values registered in the table on the memory are read according to the operating state of the system. After updating, the newly obtained table is written in the firmware, and when the power saving control of the CPU by the state control unit is performed, an idle thread that does not affect the overall control of the system is set in the CPU. It is designed to be executed by.

[0020]

The operation based on the above configuration will be described.

In the power saving control system of the present invention, in a multiprocessor system having at least two CPUs, the state monitoring means for always detecting the operating state of the system and the operating state of the system detected by the state monitoring means are When the change exceeds a predetermined boundary condition, the state transition control for the designated CPU (power saving control for transitioning the operating state of the CPU from the normal state to the standby state, and the CPU
The number of CPUs operating simultaneously according to the operating status of the multiprocessor system While switching, it is possible to maintain operation with optimum power consumption.

The state control means sequentially performs the state transition control for each CPU, and particularly in the power saving control, until the power consumption of the entire system becomes smaller than a predetermined minimum power, or
By repeatedly performing the power saving control until only one CPU is in the normal state, the limit value of the power consumption by the multiprocessor system is set in advance to achieve more efficient power saving and minimize the power consumption. You can keep it to the limit.

Further, when the state monitoring means detects the condition for starting the power saving control that the operating state of the system is lower than the specified value of the boundary condition, the operating state of the system specifies the boundary condition. When the state monitoring means detects that the value is below a certain value continues for a certain period of time, when the state monitoring means detects that the designated input means is in the input waiting state, etc. In addition, when the state monitoring means detects a condition in which the operating condition of the system exceeds the specified value of the boundary condition, the operating condition of the system exceeds the specified value of the boundary condition. When the state monitoring means detects that the state has continued for a certain period of time or more, the state monitoring means detects that there is an input operation to the designated input means. Can, by defining as such, the load due to operation processing to identify the relatively small idling CPU, can be subjected to selective power saving control.

Further, as a concrete state transition control by the state control means, in the power saving control, the operation of the CPU is suspended by using a clock stopping means provided in the CPU, while in the return control, the CPU is stopped. In the power saving control, the clock frequency supplied to the CPU is switched to a power saving frequency lower than that in the normal state, while in the return control, the clock frequency is switched to the frequency for the normal state. In the control, the power supply to the CPU is cut off to stop the CPU, while in the return control, the power supply to the CPU is restarted to restart the CPU. The power consumption of the entire multiprocessor system can be reduced according to the number of CPUs operating simultaneously.

Further, as a specific detection processing by the state monitoring means, a bus (system bus or processor bus and I / O bus) for relaying the specified value of the boundary condition to a signal exchanged between constituent elements of the system. Of at least one of the above)
Detecting the load status of the bus at the present time as the operating status of the system, the specified value of the boundary condition is a specific value indicating the load status of the application execution in the entire system, and the load status of the application execution at the present time is the operating status of the system. The boundary value of the boundary condition, which is detected as, controls the state of the task queue or job queue for distributing the task or job that realizes the function of the application to each CPU, and the execution order of the task or job. With a specific value that represents the scheduling state, which is the state of the scheduler,
By performing processing such as detecting the current scheduling status as the operating status of the system, optimum power saving control can be performed according to the characteristics of each individual multiprocessor system that is actually operating. .

Furthermore, the state monitoring means and the state control means are provided inside a multiprocessor-compatible operating system for performing task thread generation and distribution required for application execution using a plurality of CPUs and scheduling control. With the provision
The system load reference table for registering the prescribed value of the boundary condition in advance is provided in the firmware,
When registering or updating the specified value of the boundary condition, the system load reference table is read from the firmware onto the memory, and various setting values registered in the table on the memory are read according to the operating state of the system. After updating, the newly obtained table is written in the firmware, and when the power saving control of the CPU by the state control unit is performed, an idle thread that does not affect the overall control of the system is set in the CPU. The power saving function of each CPU itself is utilized via the operating system to perform power saving control independent of the hardware configuration, and the idling state of the multiprocessor system is controlled by the system. The system structure is defined by defining it in the load reference table. It is possible to perform flexible power saving control accordingly even if changed.

[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the power saving control system of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing the overall configuration of an embodiment of the power saving control system of the present invention. In the figure, n
The individual processor units 103 to 105 are connected to the host bus 113, and the host bus 113 is connected to the I / O bus 114 through the I / O bus bridge 108.
The main memory 106 is connected to the host bus and the keyboard 10
9, file system 115, display control unit 112 and R
The OM 107 is connected to the I / O bus 114.

In FIG. 1, the system state monitoring unit 101
(Corresponding to "state monitoring means" in claims) is connected to the n processor units 103 to 1 through the host bus 101.
05 Each operating state and the presence or absence of input from the keyboard 109 are monitored, and it is detected that the system is in a state of waiting for input from the keyboard 109 or a low load state. Then, when a certain period of time elapses after the system enters the input waiting state or the low load state, the power saving control is started for the system state control unit 102 (corresponding to "state control means" in claims). To send the request signal. In response to this, the system state control unit sends the clock signal supplied to the processor unit in the input waiting state or the low load state to the low-speed clock signal (clock with a power saving frequency lower than usual). Signal) and a request signal for stopping the power supply to the processor, and a power supply switching signal for appropriately switching power supply devices with different capacities according to the power consumption of the system. Send to 110. In addition, power saving control of the entire system is performed by sending a hard disk drive motor stop request signal to the file system 115 and a CRT power supply stop request signal to the display control unit 112.

FIG. 2 is a block diagram showing the configuration of the processor unit shown in FIG. In FIG. 2, C in normal operation
The processor unit is configured to switch between a high clock (a high frequency clock signal for normal operation) supplied to the PU and a low clock (a low frequency clock signal for power saving) supplied during power saving control.

FIG. 3 is a diagram showing a processing flow of clock switching in the processor in FIG. Below, FIG.
An example of the power saving control operation in the processor unit will be described with reference to FIG. In FIG. 3, the processor bus monitoring unit 156 includes a processor 154 and a host bus 113.
Is connected to the processor bus 157 between and to determine the operating state of the processor. For example, when the processor 154 waits for input from the keyboard, a key sense routine (usually a program stored in the ROM 107 or the main memory 106 in FIG. 1) is executed. The processor bus monitoring unit 156 determines that this key sense routine is being executed (step 501 in FIG. 6), and sends a signal to the system status monitoring unit 101 indicating that the processor 154 is in a key input waiting state. Is output. When the system state monitoring unit 101 detects that the key input waiting state continues for a predetermined time or more (step 502), the system state monitoring unit 101 starts power saving control for the specific processor 154 in the key input waiting state. A power saving control request signal to that effect is output to the system state control unit 102 (step 503).
Then, the system state control unit 102 sends a request signal for requesting switching to a low clock to the clock switching unit 153 of the processor unit (step 504), and the clock switching unit responds to the low clock signal to the processor 154 accordingly. The supply of the clock 151 is started (step 50).
5). Generally, the lower the operating frequency is, the less power the processor consumes. Therefore, when high-speed computing performance is not required such as waiting for a key input, the power consumption of the multiprocessor system can be reduced by switching to a slower clock. can do.

FIG. 4 is a diagram showing a processing flow for stopping and powering off the processor in FIG. Hereinafter, FIG. 2 and FIG.
Another example of the power saving control operation in the processor unit will be described with reference to FIG. In FIG. 4, the processor bus monitoring unit 15 indicates that the processor 154 has entered the key input waiting state.
6 detects (step 541 in FIG. 4), a signal indicating that the processor 154 is in the key input waiting state is output to the system state monitoring unit 101. Then, the system state monitoring unit 101 detects that the key input waiting state is continuous for a certain time or more (step 54).
2) A processor stop request for stopping the processor 154 in the key input waiting state is sent to the system state control unit 102 (step 533). In response to this, the system state control unit 102 controls the operating system (hereinafter referred to as OS
Abbreviated) is requested to start the stop processing of the processor 154 (step 534). When the process of stopping the processor 154 by the OS is completed (step 53)
5), the system state control unit 102 sends a signal requesting stop of power supply to the power supply control unit 155 that supplies power to the processor 154 whose operation is stopped (step 536). In response to this, the power supply controller 155 stops the power supply to the processor 154 (step 5).
37). The detailed operation of the other OS will be described later.

Note that the above-described clock switching process or processor stop process is performed only for a single processor in the key input waiting state, but when one processor is in the key input waiting state, a plurality of The above-described power saving control may be performed on the processor. This is realized by adding the process for determining the CPU to be the target of clock switching immediately after step 503 in the process flow shown in FIG. In addition, step 53 in the processing flow shown in FIG.
Immediately after step 3, the process for determining the processor to be the target of the stop process is added, and it is realized by determining whether or not the stop process of all the processors targeted in the process 535 is completed.

Next, details of the processor stop processing will be described.

FIG. 5 is a diagram showing the details of the CPU stop processing, and shows the details of the processor stop processing performed at steps 534 and 535 in FIG. A coherency maintaining process (a process of matching the contents of the cache memory inside the processor and the external secondary cache memory with the contents of the main memory) is indispensable for the processor stop processing. That is, in FIG. 5, when the processor stop processing is performed, first, a cache flush signal is sent to the processor and the secondary cache memory (step 561). When the flash signal is accepted, the processor and the secondary cache memory will change the data stored in the memory to
The content that has been updated due to writing from the processor, etc., and that does not match the content held at the corresponding address in the main memory (this is called "dirty data") is the one in the main memory. The process of writing to the address (this is called "sweeping") is performed (step 56).
2). Then, when all the sweeping out of dirty data is completed (step 563), a stop instruction is issued to the processor (step 564), and the stop processing of the processor is completed.

As a processor having a flash function of the above-mentioned cache memory, for example, a microprocessor Pentium (TM) or the like is provided by Intel Corporation in the United States, and the flash function is described in a data sheet issued by Intel Corporation. Pentium (TM) Processor Use
r's Manual Volume1: It is described on page 5-31 in the Pentium Processor Data Book.

Next, the processor bus monitoring unit 15 in FIG.
6 and the operation of the key sense routine shown in FIG.
Will be explained.

FIG. 6 is a block diagram showing the configuration of the processor bus monitoring unit in FIG. An operation for clearing the contents of the counter 156e at the same time as the setting operation of the flag register 156a is added to the key sense routine. In FIG. 6, the counter 156e starts counting as soon as its contents are cleared, and when the count value exceeds the value preset in the register 156d, a signal for clearing the contents of the flag register 156a is output. Sent out. As a result, the content of the counter 156e is continuously cleared while the key sense routine is continuously executed, so that the flag register 156a is not cleared and a signal indicating that the processor is in the key input waiting state. Will continue to be output. In addition, when the key input waiting state is canceled within a fixed time after the execution of the key sense routine, the count value of the counter 156e becomes larger than the value set in the register 156d after a predetermined time. Since the contents of the flag register 156a are cleared, the signal indicating the key input waiting state is released.

Next, two other configuration examples of the processor unit in FIG. 1 will be shown.

FIG. 7 is a block diagram (No. 1) showing another configuration of the processor section in FIG. In the example shown in the figure, the system clock signal 159 of the host bus is used in place of the high clock 152, and the low clock generation means 151 generates a low clock by dividing the system clock signal 159, and separately from the ROM 107. A ROM 158 is provided on the processor bus 157 to store a program such as a shutdown routine for performing a processor stop process. This allows
The clock generator circuit is saved to reduce the manufacturing cost, and a different program for each processor is stored in the ROM1.
It is also possible to store the data in the processor 58 and execute the processing unique to each processor.

FIG. 8 is a block diagram (No. 2) showing another configuration of the processor section in FIG. In the example of the figure, the system state monitoring unit 101 and the system state control unit 10 are shown.
Instead of 2, the processor bus monitoring unit 156 and the power saving control unit 159 are connected to the processor bus 157.
Also, the power saving operation shown in FIG. 4 is performed in the power saving control unit 159. This allows the processor unit to independently execute power saving control without affecting the main body of the multiprocessor system including the host bus 113.

The return from the low clock operating state or the suspended state of the processor described above to the normal operating state is as follows.
This is triggered by an input from the keyboard or an interrupt from the communication port.

Next, an OS compatible with the multiprocessor system
A power saving control system mainly composed of will be described.

FIG. 9 is a diagram showing the overall configuration of an OS compatible with the multiprocessor system which operates in the system of FIG. In the figure, multiprocessor-capable OS201 operates on a multi-processor system 218 having m processors 154 ₁ to 154 _m. And OS201
Is a kernel 205 having a basic function as an OS,
An application interface 204 for inputting / outputting with application software, a user interface 203 for inputting / outputting with a user, a basic input / output software such as a processor boot-up routine 217, a BIOS 217, a kernel 205, a multiprocessor system 218, etc. The hardware virtualization layer 213 that virtualizes the above hardware. The kernel 205 manages _n virtual CPUs 212 _{1 to} 212 n, which are OS resources, and n task queues 211 ₁ that are queues of tasks processed by the virtual CPUs 212 _{1 to} 212 _n . ~ 211
and _n, it consists of the task allocation unit 206 for allocating the tasks for the task queue 211 ₁ ~211 _n. Further, the hardware virtualization layer 213 uses the n virtual Cs described above.
PU212 ₁ and CPU allocation unit 214 to correspond to the m CPU 154 ₁ to 154 _m in the -212 _n the actual multi-processor system 218 (corresponding to a multiprocessor system shown in FIG. 1), the power saving of the multi-processor system 218 Power saving control unit 215 for controlling
Consists of

Next, the power saving control by the multiprocessor OS 201 shown in FIG. 9 will be described with reference to FIGS. In the power saving control by the multiprocessor-compatible OS 201, the load monitoring unit 209 uses the task queues 211 _1-
211 _n and the task allocation unit 206 are monitored to determine the load status of the system, and the power saving control unit 215 inside the hardware virtualization layer 213 controls the system status monitoring unit 101 and the system status control unit 102 accordingly. It is realized by doing.

FIG. 10 is a diagram showing a processing flow of the clock switching operation of the processor by the OS of FIG. In the figure, the load monitoring unit 209 task queue 211 ₁ to 21
The state of 1 _n is monitored to detect that the system load is less than a certain value (step 511). Then, when it is detected that the system load is less than a certain value for a certain period of time or more (step 512), the power saving control unit 215 instructs the system state monitoring unit 101 to perform the system power saving control. Is set (step 513). Hereinafter, in steps 514 and 515,
Processing similar to steps 504 and 505 in FIG. 3 is performed.

FIG. 11 shows an arbitrary CPU based on the OS of FIG.
FIG. 7 is a diagram showing a processing flow of stopping and power-off of the. In the figure, steps 511 to 513 are the same as those in FIG. Then, the system state control unit 102 sets the OS
CP by generating an interrupt to 201
Request U stop processing (step 534). In response to this, the OS 201 executes the processor stop processing shown in FIG. 5, and when the stop processing is completed (step 53).
5) The power supply to the processor is stopped by the same processing as that shown in steps 536 and 537 in FIG.

FIG. 12 is a diagram showing the details of the stop processing of an arbitrary CPU. The hardware virtualization layer 2 of the OS 201 is shown in FIG.
13 shows the processing in 13. In the hardware virtualization layer, the virtual CPUs 212 _{1 to} 212 _n inside the OS 201 and the CPU 154 ₁ in the actual multiprocessor system
.About.154 _m , the CPU allocation unit 20
4 performs the following operation. That is, in FIG. 12, when the processor stop request is received, the CPU allocation unit 214 in the hardware virtualization layer 213 prohibits the allocation of the virtual CPU to the CPU that is the target of the stop request (step 591). Then, it is checked whether or not the task is currently being executed in the CPU (step 59).
2) If the task is being executed, the task is waited for (step 593), and the above-described cache memory coherency matching process is performed (step 594). After that, a stop command is issued to the processor (step 595), and the system state control unit 102 is notified that the stop processing of the processor is completed (step 596).

FIGS. 13 and 14 are flowcharts showing the operation of another power saving control by the OS of FIG. 9, and the power consumption of the entire multiprocessor system is always kept to a fixed value or less.

First, the process of stopping the plurality of processors of the system to reduce the power consumption will be described.
In FIG. 13, when the power saving control of the system is started,
The processor to be stopped is selected (step 60).
1), stop processing of the processor is performed (step 60)
2). Further, after the power supply to the processor is stopped (step 603), the power consumption of the entire multiprocessor system is measured (step 604). And
It is determined whether or not the power consumption of the system has become less than or equal to a preset set value (step 605), and if it is not less than the preset value, the processing from step 601 is repeated again,
Until the power consumption of the entire system becomes equal to or less than the set value, or until the number of processors in the operating state becomes one, the stop processing of the processors is sequentially performed.

Next, a description will be given of the process of sequentially returning and operating the processors from the state in which the plurality of processors of the system are stopped. In FIG. 14, when the return control is started, the processor to be restored is first selected (step 611), and the power supply to the processor is restarted (step 612). Further, after the recovery process of the processor is performed (step 613), the power consumption of the entire system is measured (step 614). Then, it is determined whether or not the power consumption of the system has exceeded a predetermined set value (step 615), and if it is below the set value, the recovery processing of other processors is performed again from step 611, and all the processors are processed. This return process is sequentially repeated until is in the normal operation state.

Of the processes described in FIGS. 13 and 14, the description thereof is omitted, and the same processes as the corresponding parts in FIGS. 1 to 12 are performed.

FIG. 15 is a block diagram showing an example of the configuration of the power supply unit in the power saving control system of the present invention. In the figure, the power supply units are a large capacity power supply unit 701 and a small capacity power supply unit 704.
And rectifying and smoothing circuits 702 and 705, respectively.
And constant voltage circuits 703 and 706.
The power source switching control unit 707 is a mode switching signal 7 sent from the system state control unit 102 in FIG.
08, the system power is supplied by switching one of the large-capacity power supply unit 701 and the small-capacity power supply unit 704, or by using both of them at the same time.

FIG. 16 is a block diagram showing another example of the configuration of the power supply unit in the power saving control system of the present invention. In the figure, the power supply device comprises n power supply units 710 _{1 to} 710 _n , and each power supply unit has a rectifying and smoothing circuit 714 ₁ to 710 _1.
714 _n and constant voltage circuits 715 _{1 to} 715 _n . The power supply capacity control unit 720 selects any of the power supply units 710 _{1 to} 710 _n according to the mode switching signal 708 sent by the system state control unit 102, or selects all power supplies. System power is supplied by operating the parts simultaneously.

FIG. 17 is a block diagram showing still another configuration example of the power supply unit in the power saving control system of the present invention. In the figure, CPU section a730 _{1 to} CPU section n730
_3, the power supply to the display control unit 123 and CRT124 is performed from the power supply 110. When the system state monitor circuit 733 detects that the system has entered the standby state, the system state monitor circuit 733 causes the system power source control circuit 732 to notify the power source control units 731 ₁ , 731 ₂ , ... 731 _n and the display control unit 132. Power supply control signals are sequentially transmitted. Upon receiving the power supply control signal, the power supply control units 731 ₁ , 731 ₂ , ... 731 _n correspond to the respective CPU units a.
After the stop processing of 730 _{1 to} CPU unit n730 ₃ is completed, the power supply to each of the CPU units a730 _{1 to} CPU unit n730 ₃ is stopped. Further, when the display control unit 123 receives the power supply control signal, the display control unit 123 controls the display data to the CRT 124, or further sends the power supply control signal to the CRT 124 to perform the power saving control of the CRT 124.

Next, another embodiment of the power saving control system of the present invention will be described with reference to FIGS.

FIG. 18 is a block diagram showing the overall construction of another embodiment of the power saving control system of the present invention. In the figure, CPU- ₁ (103), CPU- ₂ (10
4), ..., CPU- _n (105) n (n is a natural number) CPUs each have a function of stopping the clock operation inside the CPU, and via the system bus 801. It is connected to the I / O bus bridge 108, the system management unit 802, and the main memory 106. In this embodiment, the portion corresponding to the "state monitoring means" in the claims is the "state control means" in the system management unit 802.
It is assumed that the portions corresponding to are provided inside each CPU.

FIG. 19 is a diagram showing a processing flow of the power saving control operation in the system of FIG. Below, FIG.
The operation of each part of the system will be described with reference to FIG.

In FIG. 18, the system management unit 802 monitors the operating states of the system bus 801 and the I / O bus 114 described above (step 830), and operates both or one of these two buses. The bus load factor is calculated from the state (step 831), and based on the load state of the entire multiprocessor system in FIG. 18, it is determined whether the system has entered the idle state (step 832). When it is determined that the system has entered the idle state (step 8)
32 = YES), the system management unit 802 determines the above-mentioned n Cs according to the load state of the entire system.
For any CPU of the PU, the clock stop signal 801 _-1 to stopping the clock signal of the internal the CPU
_-n is transmitted (step 833).

Here, in order to detect the load state of the system, the system management unit 802 described above
Information such as the number of transactions per unit time on the system bus 801, the type of transaction on the system bus 801, and the access address range of the transaction is referred to. These system buses 801
I / O instead of information about the above transaction
Monitor the number of transactions on the bus 114, the number of accesses per unit time to the main memory 106 connected to the system bus 801, or the access status to a specific input / output device connected to the I / O bus 114. You may do it.

FIG. 20 is a diagram showing the overall structure of the OS compatible with the multiprocessor system operating in the system of FIG. 18, and the same components as those in FIG.
The description is omitted. In the figure, the operating system 201a operates as follows in combination with the multiprocessor system 218a having m CPUs.

That is, the operating system 20
The hardware virtualization layer 213 in 1a is a system management unit 80 in the multiprocessor system 218a.
A system control unit 215a for controlling the
System bus 8 via system management unit 802
The operating state of 01 is monitored. System control unit 215a
Compares the load state of the multiprocessor system 218a detected from the monitoring result of the system bus 801 with the value registered in advance in the system load reference table 803 (details will be described later) in the operating system 201a. Then, the system control unit 215a performs power saving control of the system according to the load state of the multiprocessor system 218a based on the comparison result. At this time, as a concrete power saving control of the system, a method of using the power saving function provided in each CPU shown in FIG.
The method of switching the clock frequency externally applied to each CPU as described with reference to FIG.
Any of the methods of stopping clock supply and power supply to PU may be adopted.

In the operating system 201a shown in FIG. 20, if the function of stopping the clock supply to the CPU is used as the power saving process for an arbitrary CPU, some trouble occurs in the overall operation of the operating system 201a. So that the CPUs whose clock supply is to be stopped are selected in advance so that the task allocation unit 206 and the task queues 211 ₁ to
211 _n via the operating system 201
It is advisable to execute the idle task 804, which is completely unrelated to the function of a. Hereinafter, this process will be described with reference to the flowchart of FIG.

FIG. 21 is a diagram showing a processing flow of the power saving control operation by the OS of FIG. In the figure, the system control unit 215a includes a system bus 801 via the system management unit 802 and the I / O bus 1 shown in FIG.
14 is monitored, and the detected operating states of the two buses are compared with the registered values in the system load reference table 803 (step 840). The system control unit 215a uses the comparison result as a basis for the multiprocessor system 218a.
Determines whether the idle state has been entered (step 8)
41). When it is determined that the multiprocessor system 218a has entered the idle state (step 84)
1 = YES), the multiprocessor system 218a.
A CPU to be stopped is selected from among the plurality of CPUs that make up the CPU, and an idle task is given so as not to cause a problem in the operation of the entire operating system 201a (step 842). Furthermore, the system management unit 802
To stop the CP selected in step 842 via
A signal (STPCLK # signal) for operating the power saving function inside the CPU is sent to U (step 84).
3).

Subsequently, the system load reference table 8 in the operating system 201a shown in FIG.
A specific example of No. 03 will be described.

FIG. 22 is a diagram showing an example of the system load reference table in FIG. In the figure, the system load reference table 803 described above is stored in the BIOS-ROM 107 in the multiprocessor system 218a,
BIOS-ROM address map 801, as shown in the BIOS
It comprises an area 811 and a firmware area 812 specific to the multiprocessor system 218a. FIG.
In the example, the capacity of the BIOS area 812 is 128KB, and
The case where the capacity of the firmware area 812 is 128 KB is shown. System load reference table 803
Is in the firmware area 812 described above, and is the system bus 8 in the multiprocessor system 218a.
01 or I / O bus 114, or main memory 10
Information such as the frequency of access from the CPU to 6 or a specific input / output device is stored. That is, FIG.
In the system load reference table 803 shown in FIG.
System bus 80 of the multiprocessor system 218a
Information on the number of memory reads per unit time (814), information on the number of memory writes per unit time (815), and the like are registered.

In addition, the multiprocessor system 218
Information on the upper limit of the memory address range when accessing the system bus 801 or the main memory 106 of a (816)
Similarly, the lower limit information (817) of the memory address range may be further registered. Further, as information for detecting the operating state of the I / O bus 114 in the multiprocessor system 218a, specific I / O address information (818) accessed by the transaction on the I / O bus 114 and per unit time. Information on the number of I / O reads (819) and information on the number of I / O writes per unit time (820) may be registered. Further, information (821) on the number of interrupt processing requests per unit time to the CPU may be registered from the peripheral device connected to the multiprocessor system 218a.

Finally, the system load reference table 803
The update will be described.

FIG. 23 is a diagram showing a process flow for updating the system load reference table by the OS of FIG. FIG.
8 and the multiprocessor system 21 shown in FIG.
8a, the system load reference table 803 indicates that the multiprocessor system 21
It is stored in the BIOS-ROM 107 as firmware unique to 8a. Therefore, the operating system 201a shown in FIG. 20 reads the system load reference table 803 from the BIOS-ROM 107 onto the main memory 106 when the multiprocessor system 218a is activated.

In FIG. 23, the load reference table 803.
18 is updated, the CRT 111 and the keyboard 109 shown in FIG. 18 are used to perform the update work in an interactive manner with the user of the multiprocessor system 218a.
That is, all the application programs (load programs) other than the operating system are stopped through the interactive process with the user (step 850). Then, after confirming that all the load programs have stopped and the multiprocessor system 218a has entered the idle state (step 851 = YES), the system management unit 802 allows the system bus 80 to operate for a certain period of time.
1 and the operating states of the I / O bus 114 are monitored (step 852). Further, the load state of each bus per unit time is calculated from the monitoring results of the two buses, and based on this, the registration parameter to the system load reference table 803 on the memory is created (step 853). . The system load reference table 803 thus obtained is written in the table in the firmware in the BIOS-ROM 107 (step 854). At this time, the firmware portion of the BIOS-ROM 107 may be composed of a rewritable device such as an EEPROM (electrically erasable ROM).

[0071]

As described in detail above, according to the power saving control system of the present invention, at least two CPUs are provided.
In a multiprocessor system including: a state monitoring unit that constantly detects the operating state of the system; and a state of a designated CPU when the operating state of the system detected by the state monitoring unit changes beyond a predetermined boundary condition. A configuration including a state control unit that performs transition control (either power saving control that transitions the operating state of the CPU from the normal state to the standby state or return control that transitions the operating state of the CPU from the standby state to the normal state) By doing so, it is possible to obtain the effect that it is possible to maintain operation with optimum power consumption while switching the number of CPUs that operate simultaneously according to the operating status of the multiprocessor system.

The state control means sequentially performs the state transition control for each CPU, and particularly in the power saving control, until the power consumption of the entire system becomes smaller than a predetermined minimum power, or
By repeatedly performing the power saving control until only one CPU is in the normal state, the limit value of the power consumption by the multiprocessor system is set in advance to achieve more efficient power saving and minimize the power consumption. The effect that it can be suppressed to the limit is obtained.

Further, when the state monitoring means detects the power saving control start condition as a condition that the system operating condition is below the specified value of the boundary condition, the operating condition of the system is specified by the boundary condition. When the state monitoring means detects that the value is below a certain value continues for a certain period of time, when the state monitoring means detects that the designated input means is in the input waiting state, etc. In addition, when the state monitoring means detects a condition in which the operating condition of the system exceeds the specified value of the boundary condition, the operating condition of the system exceeds the specified value of the boundary condition. When the state monitoring means detects that the state has continued for a certain period of time or more, the state monitoring means detects that there is an input operation to the designated input means. Can, by determining, such as, calculation processing load to identify the relatively small idling CPU due, the effect is obtained that can be subjected to selective power saving control.

Further, as a concrete state transition control by the state control means, in the power saving control, the operation of the CPU is suspended by using a clock stopping means provided in the CPU, while in the return control, the CPU is stopped. In the power saving control, the clock frequency supplied to the CPU is switched to a power saving frequency lower than that in the normal state, while in the return control, the clock frequency is switched to the frequency for the normal state. In the control, the power supply to the CPU is cut off to stop the CPU, while in the return control, the power supply to the CPU is restarted to restart the CPU. The power consumption of the entire multiprocessor system can be reduced according to the number of CPUs operating at the same time. Results can be obtained.

Further, as a specific detection process by the state monitoring means, a bus (system bus or processor bus and I / O bus) for relaying the specified value of the boundary condition to a signal exchanged between the constituent elements of the system. Of at least one of the above)
Detecting the load status of the bus at the present time as the operating status of the system, the specified value of the boundary condition is a specific value indicating the load status of the application execution in the entire system, and the load status of the application execution at the present time is the operating status of the system. The boundary value of the boundary condition, which is detected as, controls the state of the task queue or job queue for distributing the task or job that realizes the function of the application to each CPU, and the execution order of the task or job. With a specific value that represents the scheduling state, which is the state of the scheduler,
By performing processing such as detecting the current scheduling status as the operating status of the system, optimum power saving control can be performed according to the characteristics of each individual multiprocessor system that is actually operating. The effect is obtained.

Furthermore, the state monitoring means and the state control means are provided inside a multiprocessor-compatible operating system for performing task thread generation and distribution and scheduling control required for application execution using a plurality of CPUs. With the provision
The system load reference table for registering the prescribed value of the boundary condition in advance is provided in the firmware,
When registering or updating the specified value of the boundary condition, the system load reference table is read from the firmware onto the memory, and various setting values registered in the table on the memory are read according to the operating state of the system. After updating, the newly obtained table is written in the firmware, and when the power saving control of the CPU by the state control unit is performed, an idle thread that does not affect the overall control of the system is set in the CPU. The power saving function of each CPU itself is utilized via the operating system to perform power saving control independent of the hardware configuration, and the idling state of the multiprocessor system is controlled by the system. The system structure is defined by defining it in the load reference table. There is an advantage that it is possible to perform a flexible power saving control accordingly even if changed.

[Brief description of drawings]

FIG. 1 is a block diagram showing an overall configuration of an embodiment of a power saving control system of the present invention.

FIG. 2 is a block diagram showing a configuration of a processor unit in FIG.

FIG. 3 is a diagram showing a processing flow of clock switching in the processor in FIG.

FIG. 4 is a diagram showing a processing flow of stopping / powering off the processor in FIG. 2;

FIG. 5 is a diagram illustrating details of CPU stop processing.

FIG. 6 is a block diagram showing a configuration of a processor bus monitoring unit in FIG.

7 is a block diagram (No. 1) showing another configuration of the processor unit in FIG. 1. FIG.

FIG. 8 is a block diagram (No. 2) showing another configuration of the processor unit in FIG. 1.

9 is a diagram showing an overall configuration of an OS compatible with a multiprocessor system that operates in the system of FIG.

10 is a diagram showing a processing flow of clock switching operation of the processor by the OS of FIG. 9;

FIG. 11 is a diagram showing a processing flow of stopping / powering off any CPU by the OS of FIG. 9;

FIG. 12 is a diagram showing details of a stop process of an arbitrary CPU.

FIG. 13 is a flowchart (part 1) showing another power saving control operation by the OS of FIG. 9;

FIG. 14 is a flowchart (No. 2) showing another power saving control operation by the OS of FIG. 9;

FIG. 15 is a block diagram showing a configuration example of a power supply unit in the power saving control system of the present invention.

FIG. 16 is a block diagram showing another configuration example of the power supply unit in the power saving control system of the present invention.

FIG. 17 is a block diagram showing still another configuration example of the power supply unit in the power saving control system of the present invention.

FIG. 18 is a block diagram showing the overall configuration of another embodiment of the power saving control system of the present invention.

19 is a diagram showing a processing flow of a power saving control operation in the system of FIG.

20 is a diagram showing an overall configuration of an OS compatible with a multiprocessor system which operates in the system of FIG.

21 is a diagram showing a processing flow of a power saving control operation by the OS of FIG. 20. FIG.

22 is a diagram showing an example of a system load reference table in FIG.

23 is a diagram showing a process flow of updating the system load reference table by the OS of FIG. 20.

FIG. 24 is a block diagram showing an example of a conventional power saving control system.

FIG. 25 is a block diagram showing an example of a power supply system in a conventional multiprocessor system.

[Explanation of symbols]

101 system state monitoring unit 102 system state control unit 103, 104, 105 processor unit 106 main memory 107 ROM 109 keyboard 110 power supply device 113 host bus 151 low clock 152 high clock 153 clock switching means 154 processor 155 power supply control unit 156 processor bus Monitoring unit 157 Processor bus 158 ROM 202 Shell 203 User interface 204 Application interface 205 Kernel 206 Task allocation unit 207 Load monitoring unit 208 Memory management unit 211 ₁ , 211 ₂ , 211 _n Task queue 212 ₁ , 212 ₂ , 212 _n Virtual CPU 213 Hardware virtualization layer 215 Power saving control unit 801 System bus 802 System management unit 803 System Load reference table

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Internal reference number FI Technical display location G06F 15/16 460 Z (72) Inventor Atsushi Hara 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Stock-formation Inside Hitachi Systems Development Laboratory (72) Inventor Toshihiko Ogura 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Inside Hitachi Systems Development Laboratory (72) Inventor Koichi Okazawa 292 Yoshida-cho Totsuka-ku, Yokohama-shi, Kanagawa Address Company Hitachi, Ltd. System Development Laboratory (72) Inventor Taka Oeda 292 Yoshida-cho, Totsuka-ku, Yokohama-shi Kanagawa Prefecture System Development Laboratory Hitachi Ltd. (72) Makoto Sano 1410 Inada, Hitachinaka City, Ibaraki Prefecture Stock Company Hitachi, Ltd. Multimedia System Division

Claims (24)

[Claims] 1. In a multiprocessor system including at least two CPUs, a state monitoring means for always detecting an operating state of the system, and an operating state of the system detected by the state monitoring means exceed a predetermined boundary condition. When changed, the designated CPU
And a state control means for performing state transition control for the power saving control system. 2. The state transition control is a power saving control for transitioning an operating state of a CPU from a normal state to a standby state, and C
2. The power-saving control system according to claim 1, wherein the power-saving control system is any one of return control for changing the operating state of the PU from the standby state to the normal state. 3. The power saving control system according to claim 2, wherein the state control means sequentially performs the state transition control for each CPU. 4. The state control means performs the power saving control until the power consumption of the entire system becomes smaller than a predetermined minimum power.
The power saving control system described. 5. The state control means is a C in a normal state.
The power saving control system according to claim 3, wherein the power saving control is performed until there is one PU. 6. The state control means starts the power saving control when the state monitoring means detects a state in which an operating state of the system is lower than a specified value of the boundary condition. Item 6. A power saving control system according to any one of items 2 to 5. 7. The state control means starts the return control when the state monitoring means detects a state in which the operating state of the system exceeds a specified value of the boundary condition. The power saving control system according to any one of 2 to 5. 8. The state control means controls the power saving control when the state monitoring means detects that the operating state of the system is below a prescribed value of the boundary condition for a certain period of time or longer. The power saving control system according to claim 2, which is started. 9. The state control means starts the return control when the state monitoring means detects that the operating state of the system exceeds a prescribed value of the boundary condition for a certain period of time or longer. 3. The method according to claim 2, wherein
The power-saving control system according to any one of items 1 to 5. 10. The state control means starts the power saving control when the state monitoring means detects that the designated input means is in an input waiting state. The power-saving control system according to any one of 1. 11. The state control means starts the return control when the state monitoring means detects an input operation to a designated input means. The power-saving control system according to any one of 1. 12. The power-saving control uses a clock stopping means provided in the CPU to suspend the operation of the CPU, while the return control restarts the operation of the CPU. The power-saving control system according to any one of items 1 to 8. 13. The power saving control switches the clock frequency supplied to the CPU to a power saving frequency lower than that for the normal state, while the return control switches the clock frequency to the frequency for the normal state. The power saving control system according to claim 2. 14. The power saving control cuts off the power supply to the CPU to stop the CPU, while the return control restarts the power supply to the CPU to restart the CPU. The power saving control system according to any one of claims 2 to 8. 15. The specified value of the boundary condition is a specific value representing a load state of a bus that relays a signal exchanged between components of the system, and the state monitoring unit sets the load state of the bus at the present time. The power saving control system according to claim 1, wherein the power saving control system is detected as an operating state of the system. 16. The power saving control system according to claim 15, wherein the bus is at least one of a system bus, a processor bus, and an I / O bus. 17. The specified value of the boundary condition is a specific value representing a load state of application execution in the entire system, and the state monitoring means detects the load state of application execution at the present time as an operating state of the system. The power saving control system according to any one of claims 1 to 14. 18. A task queue or job for distributing the specified value of the boundary condition to each CPU for a task or job that realizes the function of an application.
A specific value representing a scheduling state which is a state of a queue and a state of a scheduler that controls the execution order of the tasks or jobs, and the state monitoring means detects the current scheduling state as an operating state of the system. The power saving control system according to any one of claims 1 to 14. 19. The state monitoring means and the state control means are provided inside a multiprocessor-compatible operating system that performs generation and distribution of task threads required for application execution using a plurality of CPUs and scheduling control. The power saving control system according to any one of claims 1 to 18, wherein the power saving control system is configured to: 20. The firmware is provided with a system load reference table for registering a prescribed value of the boundary condition in advance.
9. The power saving control system according to item 9. 21. When the specified value of the boundary condition is registered or updated, the system load reference table is read from the firmware into a memory and registered in the table in the memory according to the operating state of the system. 21. The power saving control system according to claim 20, wherein the newly obtained table is written in the firmware after updating various setting values. 22. The system load reference table comprises:
Information indicating the number of memory access transactions per unit time on the bus in the system, information indicating the number of memory read transactions, information indicating the number of memory write transactions per unit time, I /
22. The power saving control system according to claim 20, wherein at least one of information indicating the number of O access transactions is registered. 23. The system load reference table comprises:
22. The power saving according to claim 20, wherein one or both of information indicating a memory access address range within a unit time on a bus in the system and information indicating an I / O access address range are registered. Control system. 24. In the power saving control of the CPU by the state control means, the CPU is caused to execute an idle thread that does not affect the overall control of the system. Control system.