JPH0863449A - System protecting device and controller utilizing the same - Google Patents

Abstract

PURPOSE: To prevent an unsafe state from being generated when a system clock signal stops. CONSTITUTION: The system clock signal A and another clock signal B are logically processed to detect the stop of the system clock signal A, and a reset signal E is generated on the basis of an existent system reset signal C or clock signal stop detection signal D to reset the whole or part of the system.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a system protection device and a control device for performing control processing in synchronization with a clock signal, and more particularly to a system protection device provided with a plurality of independently oscillating clock signal oscillation means. Regarding the control device.

[0002]

2. Description of the Related Art In a system, such as a facsimile machine, having heat-generating parts such as a thermal head and a motor and controlling them using a central processing unit (hereinafter referred to as CPU) For some reason, the heat-generating component may remain energized for a long time. If the power is continuously applied for a long time, these parts continue to generate heat and may not operate normally, and in some cases, may be destroyed or ignited.

In order to prevent the occurrence of such a problem, a protective device for detecting the temperature of the heat-generating component and controlling the energization is provided. For example, in the protection device disclosed in Japanese Patent Laid-Open No. 64-85780, current supply is stopped when the temperature of the thermal head exceeds a predetermined temperature due to factors such as CPU runaway, and the thermal head becomes abnormal. This is to inform the user of the fact.

A watchdog timer is known as a method for detecting runaway of the CPU, and the CPU can be immediately reset when an abnormal operation of the CPU is detected.

[0005]

However, in the protection device for detecting the temperature and performing the protection control, a temperature sensor, a temperature fuse, and the like are required for each detection factor, resulting in a high cost.

Further, the watchdog timer functions effectively when the clock signal is normally supplied to the CPU, but does not function when the supply of the clock signal is stopped. Therefore, when the generation of the reference clock signal (hereinafter referred to as the system clock signal) stops in the system with the power turned on, the input / output device is set using the system clock signal. Since the input / output register is fixed at the “high” or “low” level, the input / output device may stop in the energized state. In such a case, in a device provided with a heat-generating component such as a thermal head or a motor as an input / output device, a problem occurs such that the component continues to generate heat and is damaged.

An object of the present invention is to solve the above-mentioned problems caused by the stoppage of the generation of the system clock signal, and the stoppage of the generation of the system clock signal can be detected to stop the apparatus in a safe state. To do so.

[0008]

One of the features of the present invention is as follows.
First and second oscillating and outputting independent clock signals
In the system protection device including the oscillating means and the reset controlling means for resetting a part or the whole of the system, the clock signals output from the first and second oscillating means are logically processed to provide the first transmitting means. Clock signal stop detection means for detecting the stop of the clock signal output from the first control means, and the reset control means detects the stop of output of the clock signal from the first oscillation means from the clock signal stop detection means. Based on the above, a reset signal for resetting the whole or a part of the system is generated.

More specifically, the clock signal stop detecting means outputs a clear signal generating means for generating a predetermined clear signal and a hold signal from the second clock signal, and an output according to a change of the first clock signal. The present invention is characterized by comprising clock signal edge detecting means which is set and whose output is reset by the clear signal, and holding means which holds the output signal of the clock signal edge detecting means by the holding signal.

Further, the second clock signal is characterized by using the clock signal used for the clock means.

Further, the reset control means generates a reset signal based on a system reset signal or the detection signal.

Another feature of the present invention is a system clock signal oscillator for oscillating a system clock signal, a real-time clock signal oscillator for oscillating a clock signal for a real-time clock independently of the system clock signal oscillator, and a system clock signal oscillator. In a system protection device having a reset control means for resetting a part or the whole, a clock signal stop detection for logically processing a clock signal output from the system clock signal oscillator and a real time clock signal oscillator to detect a stop of the system clock signal. Means is provided, and the reset control means is configured to generate a reset signal for resetting the whole or a part of the system on the basis of the detection signal which detects the stop of the system clock signal output from the clock signal stop detecting means. Lies in the fact.

More specifically, the reset control means is characterized by generating a reset signal based on a system reset signal or the detection signal.

Still another feature of the present invention is to include a CPU, an input / output register, an input / output device, and a system clock signal oscillator, wherein the CPU synchronizes with the system clock signal and the input / output register and the input / output device. A clock signal oscillator independent of the system clock signal oscillator, and a clock signal for logically processing the clock signal generated from the clock signal and the system clock signal to detect the stop of the system clock signal. The stop detection means and the reset control means for generating a reset signal when the stop of the system clock signal is detected are provided.

More specifically, the reset control means resets the input / output register.

Also, the reset control means resets the input / output device.

Still another feature of the present invention is to include a CPU, an input / output register, a recording means, a system clock signal oscillator, and a clock signal oscillator for a real time clock, wherein the CPU synchronizes with the system clock signal. In a control device for controlling the input / output register and the recording means, a clock signal stop detection means for logically processing a system clock signal and a clock signal for a real time clock to detect stop of the system clock signal, and stop of the system clock signal There is provided a reset control means for generating a reset signal when the signal is detected.

More specifically, the recording means is characterized by including a thermal head.

[0019]

The clock signal stop detecting means detects the stop of the system clock signal by logically processing the two clock signals of the system clock signal and the other clock signal.

Then, the reset control means generates a reset signal in response to the stop of the system clock signal and the system reset signal.

[0021]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a system protection device according to the present invention. The system protection device 101 includes a clock signal stop detection unit 102 and a reset signal generation unit 103.

FIG. 2 shows the waveforms of each input / output signal of the system protection device 101 and the output signal of the clock signal stop detector 102. In this embodiment, the whole or a part of the system can be reset not only by the system reset signal C but also when the clock signal stop detector 102 detects the stop of the generation of the system clock signal A. It was done like this. Therefore, the system protection device 101 monitors the incoming state of the system clock signal A by using the clock signal B, and when it detects that the incoming of the system clock signal A is stopped, it outputs the reset signal E. To generate. To achieve this, the clock signal stop detection unit 102 changes its output signal (clock signal stop detection signal) D when the incoming system clock A is interrupted.

The clock signal stop detector 102 includes a clock signal edge detector 104, a clear signal generator 105, and a signal level controller 106. The clock signal edge detection unit 104 detects that the incoming system clock signal A has changed from a “high” level to a “low” level or from a “low” level to a “high” level, and detects the signal level of the output signal F. Change. Clear signal generator 1
Reference numeral 05 generates a clear signal G that periodically clears the clock signal edge detection unit 104 based on the incoming clock signal B. Therefore, the clock signal edge detector 10
4 changes the signal level of its output signal F when the level of the system clock signal A changes, and is then cleared by the clear signal G generated by the clear signal generator 105. Then, when the clear is released, the operation of responding to the level change of the system clock signal A is repeated again, and the level change is stopped when the system clock signal A is at the “high” level or the “low” level (incoming is stopped).
If so, the level change is not detected after clearing, so the output in the clear state is continued. Signal level control unit 10
6 receives the output signal F of the clock signal edge detector 104, the clock signal B and the clear signal G, and generates the clock signal stop detection signal D whose signal level changes only when the clock signal stop is detected.

The reset signal generator 103 inputs the output signal D of the clock signal stop detector 102 and the system reset signal C to generate a reset signal E as shown in FIG. And the reset control based on the output signal D of the clock signal stop detector 102. Therefore, even when the stop of the clock signal is detected, the reset control can be forcibly performed on the whole or part of the system.

Next, a concrete example (first embodiment) of the clock signal stop detector 102 will be described in detail with reference to FIGS. 3 and 4. FIG. 3 shows the circuit configuration of the clock signal stop detector 102, and FIG. 4 is a timing chart showing the respective input / output signals and the input / output signals in the internal circuit.

In FIG. 3, 301, 302, 303,
304 is a D-type flip-flop with a clear terminal (hereinafter referred to as FF). In each of the FFs 301 to 304, "C" is a clock signal terminal, "D" is a data signal terminal, "Q" and "Q" are output terminals, and "CLR" is a clear signal terminal. The FF having the clock signal terminal "C" marked with a circle operates so as to latch the input data signal (the signal level of the data signal terminal "D") at the falling edge of the clock signal. The FF of the clock signal terminal “C” that does not have an operation operates so as to latch the input data signal at the rising edge of the clock signal, and the clear signal terminal “C”
When the "low" level clear signal is input to, the latched data is cleared.

Clock signal edge detector 1 shown in FIG.
04 and the clear signal generation unit 105, the FF30
1 and 302, the signal level control unit 106
It corresponds to a combination circuit of 303 and 304.

In FIG. 4, the output signal G is the output signal of the FF 302, which is the clock signal B divided by two. The output signal H is the output signal of the FF 303, and
The output signal G of 02 is used as an input data signal, which is latched at the falling edge of the clock signal B.
The output signal F is the output signal of the FF 301, the input data signal terminal “D” is fixed to “high” level, the system clock signal A is input to the clock signal terminal “C”, and the clear terminal “CLR” is input. It is generated by inputting the output signal G. Therefore, when the system clock signal A changes from the “low” level to the “high” level while the output signal G of the FF 302 is at the “high” level, the output signal F of the FF 301 becomes the “high” level and the output signal G Becomes low level, the FF 301 is cleared.

When the incoming of the system clock signal A is stopped after this clearing, even if the output signal G of the FF302 changes to the "high" level and the clearing is released, the clock signal terminal of the FF301 " Since the signal level of "C" does not change, the FF 301 continuously outputs the output signal F of "low" level.

The output signal D is the output signal of the FF 304. The output signal F is input to the data signal terminal "D" and the output signal H is input to the clock signal terminal "C". This FF
When the system clock signal A is generated normally and is coming in, 304 latches the output signal F at the rising edge of the output signal H while the output signal F of the FF 301 is at the "high" level, so that "high". The level output signal D is continuously output. However, when the incoming of the system clock signal A is stopped, the latch output signal F of the FF 301 remains in the "low" level clear state.
The "low" level is latched at the rising edge of the output signal H of, and the output signal D becomes the "low" level. Accordingly, the clock signal stop detection unit 102 detects the clock signal stop detection of the "high" level output signal D when the system clock signal A is normally input and the "low" level output signal D when the system clock signal A is stopped. It will be output as a signal.

Next, a second embodiment of the clock signal stop detector 102 will be described with reference to FIGS. FIG. 5 shows the circuit configuration of the clock signal stop detection unit 102, and FIG. 6 shows the timing chart of each input / output signal and the input / output signal in the internal circuit.

In FIG. 5, 501, 502 and 504 are FFs. Clock signal edge detector 1 shown in FIG.
04 corresponds to FF501, the signal level control unit 106 corresponds to FF505, and the clear signal generation unit 105 corresponds to FF5.
02 and an OR gate 503.
The FF 502 outputs an output signal obtained by dividing the clock signal B by two, as shown by the output signal G1 in FIG. OR game
503 is the clock signal B and the output signal G1 of the FF502.
To output the output signal G2. And FF50
1, the output signal G2 of the OR gate 503 is input to the clear terminal "CLR", the data signal terminal "D" is fixed to "high" level, and the system clock signal A is input to the clock signal terminal "C". Enter. Therefore, this FF 501 sets the output signal F to the "high" level when the system clock signal A changes from the "low" level to the "high" level while the incoming output signal G2 is at the "high" level, and outputs the output signal G
When 2 becomes the "low" level, it is cleared and the output signal F is set to the "low" level. By repeating this, the generation state of the system clock signal A is constantly monitored.

When the incoming of the system clock signal A is stopped, the FF 501 is cleared by the output signal G2 changing to the "low" level and then cleared, and the clearing is released. However, since the system clock signal A does not rise, the output signal F continues to be in the "low" level clear state.

The FF 504 inputs the output signal F to the data signal terminal "D" and inputs it to the clock signal terminal "C".
When the system clock signal A is normally input and the output signal F of the FF 501 is at the "high" level, the output signal G1 is output at the "high" level when the output signal G1 falls. Latch signal F and maintain its output signal D at a "high" level. However, when the input of the system clock signal A is stopped, the output signal F of the FF 501 remains at the “low” level, so that the “low” level is latched at the falling edge of the output signal G1 of the FF 502,
The output signal D becomes "low" level. Therefore, the clock signal stop detection unit 102 determines that the system clock signal A
Is normally input, the high-level output signal D is output, and when stopped, the low-level output signal D is output as the clock signal stop detection signal.

Next, a third embodiment of the clock signal stop detector 102 will be described with reference to FIGS. 7, 8 and 9.
FIG. 7 shows a circuit configuration of the clear signal generation unit 105 in the clock signal stop detection unit 102, and FIG. 8 shows a circuit configuration of the clock signal stop detection unit 102. 9 is a timing chart of the input / output signals of the respective parts of the clear signal generator 105 and the clock signal stop detector 102.

In FIG. 7, 701, 702, 703
704, 705, and 707 are FFs, and 706 and 708
Is an OR gate. The FF 701 outputs the clock signal B to 2
The frequency is divided and an output signal J as shown in FIG. 9 is output. Then, the FFs 702, 703, 704 input this output signal J to each clock signal terminal “C”. FF702, 7
03 functions to further divide the output signal J by two.
The FF 702 latches the data signal at the rising edge of the output signal J, and the FF 703 latches at the falling edge to output the output signal K and the output signal M as shown in FIG. 9, respectively.

The FF 704 latches the output signal J at the falling edge of the clock signal B, and outputs the output signal N as shown in FIG.
Is output.

The FF 705 inputs the output signal K as the input data to the data signal terminal "D" and inputs the output signal N as the clock signal to the clock signal terminal "C", as shown in FIG.
The output signal P as shown in FIG.

The OR gate 706 inputs the output signal K and the output signal P and outputs the first clear signal Q.

Similarly, the FF 707 inputs the output signals M and N and outputs the output signal R, and the OR gate 708 inputs the output signals M and R and generates the second clear signal S.

As shown in FIG. 8, the clock signal stop detection unit 102 constructed by using the clear signal generation unit 105 as described above includes FFs 801, 802 and an OR gate 803. The FFs 801 and 802 correspond to the clock signal edge detection unit 104 shown in FIG. 1, and the OR gate 803 corresponds to the reset signal generation unit 103.

The FFs 801 and 802 input a "high" level fixed data signal to each data signal terminal "D", and input a system clock signal A to be detected to each clock signal terminal "C". Then, the first clear signal Q is input to the clear signal terminal "CLR" of the FF801.
The second clear signal S is input to the clear signal terminal “CLR” of the FF 802.

Therefore, in the FF 801, when the system clock signal A rises while the first clear signal Q is at "high" level, the output signal T becomes "high" level and the first clear signal Q becomes "low". When the output signal T becomes "low", the output signal T becomes "low" level. Then, when the first clear signal Q becomes "high" level again and the clear state is released, the output signal T becomes "high" level at the rising edge of the system clock signal A, and the operation of clearing is repeated. To do it. Then, when the incoming of the system clock signal A is stopped, the rising of the signal level of the clock signal terminal “C” disappears after the clearing, so that the FF8
01 continues to output the output signal T of "low" level.

Similarly, the FF 802 latches the "high" level data signal at the trailing edge of the system clock signal A, is cleared by the second clear signal S, and outputs the output signal U.
Change the signal level of. When the system clock signal A comes in normally, the first clear signal Q and the second clear signal S clear the FFs 801 and 802 at different timings, so that the output signals T and U of both FFs are both " It will never go "low".

However, when the incoming of the system clock signal A is stopped, the output signals T,
Since both U become "low" level, the output signals T, U
Output signal D of the OR gate 803 for inputting and logically processing
Changes to "low" level, and it becomes possible to detect that the incoming of the system clock signal A has stopped.

Next, the details of the reset signal generator 103 will be described with reference to FIGS. 2 and 10. FIG. 10 shows a circuit configuration of the system protection device 101, and the reset signal generation unit 103 is configured by an AND gate.

The AND gate, which is the reset signal generator 103, outputs the reset signal E as shown in FIG. 2 by inputting the system reset signal C and the output signal D of the clock signal stop detector 102. .

Therefore, the system protection device 101 is
When the system reset signal C becomes “low” level and a reset command is issued, the clock signal stop detection unit 10
When the output signal D2 of 2 goes to the "low" level due to the stoppage of the generation of the system clock signal A, the reset signal E can be set to the "low" level to perform the forced reset control.

As described above, the clock signal stop detector 102 can detect the stoppage of the generation of the system clock signal A by logically processing the timings of the two independent clock signals A and B, and also reset. Signal generator 1
03 can also be realized only by a logic gate, so the system protection device 10 based on a clock signal with only digital circuit elements.
1 can be configured. As a result, the circuit scale can be made smaller than that of the analog circuit, which is advantageous in terms of cost.

Next, an embodiment of a control device using the above-mentioned system protection device 101 will be described with reference to FIG. This controller uses another independent clock signal B which is used to detect the stop of the system clock signal A.
As an example, the clock input to the real-time clock (usually 32.768 kHz) is used, and when the stop of the system clock signal is detected, the entire system is reset.

In FIG. 11, 101 is a system protection device and 1101 is a system clock signal oscillator for oscillating a system clock signal. 1102 is a CPU for controlling the entire system, 1103 is an address decoder, 11
Reference numeral 04 is a timing control unit, 1105 is a main storage device, 11
06 is a real-time clock. The address decoder 1103 decodes the address (signal) output from the CPU 1102. Timing control unit 1104
Uses the decode value to control the timings of read and write signals for exchanging signals with the main memory 1105 and the real-time clock 1106 via the control bus so as to match the respective operations. Main memory 110
5 stores the data handled by the control device, and the CPU 110
2, data is written and read via the address bus, data bus, and control bus. The real-time clock 1106 uses a clock signal B for a real-time clock of an independent clock signal oscillator 1107, which is different from the system clock signal A, and always measures time. Reference numeral 1108 is an input / output register, and 1109 is an input / output device. The input / output register 1108 is provided for the input / output device 1109 when the address assigned to the input / output device 1109 is decoded by the address decoder 1103.
The data to be set to "1" is held or the data is read from the input / output device 1109.

In such a control device, the CPU 11
02 and the timing control unit 1104 perform signal processing in synchronization with the system clock signal A supplied from the system clock signal oscillator 1101, and the real-time clock 1106 performs signal processing based on the clock signal supplied from the clock signal oscillator 1107. Achieve the purpose of the period.

The system reset signal generating means 1
When the generation of the system reset signal C given from 110 and the system clock signal A as described above is stopped, the reset signal D is generated to reset the CPU 1102, the timing control unit 1104, and the input / output register 1108 to operate the control device. Stop in a stable state.

In this embodiment, when the reset signal D is generated, the entire control device is reset.
Reset when the system clock signal A is stopped
You may make it reset only a specific part. For example, if only the input / output register 1108 holding the control data used in the input / output device 1109 is reset, all the set control data can be initialized, so that the safety can be improved especially by stopping the system clock signal. It is also possible to initialize only the setting of control data that causes a problem and make a safe state.

Next, another embodiment of the control device using the system protection device 101 described above will be described with reference to FIG. This control device is a device in a facsimile, and as the clock signal for detecting the stop of the system clock signal, the clock signal input to the real time clock 1106 is used as in the embodiment described in FIG. .

In FIG. 12, reference numeral 1101 denotes a system clock signal oscillator, which oscillates a system clock signal A, which serves as a reference for the entire system, and inputs it to the CPU 1102 and the timing control unit 1104. Reference numeral 1106 denotes a real-time clock, which operates by a clock signal B oscillated by a clock signal oscillator 1107 different from the system clock signal A and provides a clock function. The system protection device 101 includes a system clock signal oscillator 1101.
And a clock signal A from the clock signal oscillator 1107,
B and the system reset signal C from the system reset signal generation means 1110 are input, and the stoppage of the generation of the system clock signal A is detected.

Reference numeral 1201 denotes a CPU interface section, which comprises an address decoder 1103, a timing control section 1104 and an input / output register 1108.

Reference numeral 1202 is a reading sensor for reading the image information of the transmission original, 1203 is an A / D converter for converting the image information in the form of an analog signal read by the sensor 1202 into a digital data signal, and 1204 is the image data. An image processing unit for processing. The image data processed by the image processing unit 1204 is written and stored in the memory 1205.

Reference numeral 1206 denotes a modem, which, at the time of transmission, takes in the image data stored in the memory 1205, performs modulation for transmission, and transmits it. When the image data is received, it is demodulated by the modem 1206 and written and stored in the memory 1205. The image data stored in the memory 1205 is transferred to the thermal head 12
Printing is performed on a thermal paper (not shown) according to 07.

Reference numeral 1208 is a motor for sending the original and the thermal paper for printing at the time of transmission. Reference numeral 1209 denotes a sensor control unit that controls the operation of the reading sensor 1202, 1210 a recording control unit that controls the thermal head 1207, 1211 a motor control unit, 1212 a memory control unit, and 1213 a modem control unit. A chip select signal that enables each component is generated from the decode value of the address assigned to the component.

The CPU interface unit 1201 is shown in FIG.
1 has the same function as that described above with reference to FIG.
The address signal from 2 is decoded by the address decoder 1103, and the timing control unit 1104 controls the timing of the read and write signals.

The input / output register 1108 holds setting data such as the mode of use of the reading sensor 1202, the thermal head 1207, the motor 1208 and the modem 1206, and ON / OFF of energization. This input / output register 1108
The setting data is written and read by a signal from the timing control unit 1104, but when the system clock signal stops, the timing control unit 110
Since the operation of 4 is stopped, the input / output register 11
The data of 08 is retained. Here, when the setting of energization of the thermal head 1207 and the motor 1208 is in the ON state, the thermal head 1207 and the motor 1208 continuously operate and generate heat, resulting in damage to parts.

Therefore, as shown in FIG. 12, the system protection device 101 detects the stop of the system clock signal by the system clock signal A and the clock signal B for the real time clock and holds the setting data. If 1108 is reset, all the held data can be initialized, and the occurrence of problems due to continuous operation can be prevented. Even if the initialization of the setting data is performed only for the recording control unit 1210 and the motor control unit 1211 which are the control units of the heat-generating components, the respective heat-generating components are in the inactive state. It is possible to prevent the occurrence of problems related to the stop.

FIG. 13 shows a modification of the reset control in the facsimile control apparatus described with reference to FIG. The same components as those in the above-described embodiment are designated by the same reference numerals. This modification uses the output signal D of the system protection device 101 to reset the recording control unit 1210 and the motor control unit 1211 when the stop of the system clock signal A is detected. In this way, the same effect can be obtained by resetting only the circuits that pose a safety problem.

FIG. 14 shows another embodiment of the facsimile control apparatus to which the system protection apparatus 101 according to the present invention is applied. The same components as those in the above-mentioned embodiment are designated by the same reference numerals.

Reference numeral 1401 denotes a crystal oscillator that oscillates a clock signal input to the CPU 1102.
Is a system clock signal A based on this clock signal.
Is generated and output. A crystal oscillator 1402 oscillates a clock signal input to the real-time clock 1106, and inputs the clock signal B output from the real-time clock 1106 to the system protection device 101.

Reference numeral 1403 is a facsimile controller, and as shown in the figure, the CPU interface unit 120.
1, including image processing unit 1204, sensor control unit 1209, recording control unit 1210, motor control unit 1211, memory control unit 1212, modem control unit 1213, real time clock 1106, and system protection device 101
It is a thing.

Each means functions similarly to the embodiment of FIGS. 12 and 13. In the system protection device 101, the CPU 1
The stop of the system clock signal is monitored from the system clock signal A from 102 and the clock signal B from the real time clock, and when the stop is detected, the recording control unit 1210 and the motor control unit 1211 are reset.

In this embodiment, the system protection device 101 composed of digital circuit elements is incorporated in an LSI to reduce the circuit scale. Further, by using the clock signal for the real-time clock as in this embodiment, it is not necessary to provide a special clock signal oscillator for detecting the stop of the system clock signal,
Further, since the clock signal oscillator for clocking is always operating, it is convenient to use for detecting the stop of the system clock signal.

The system protection device 101 according to the present invention is
The present invention can be widely applied to recording control devices such as printers and control devices that control heat-generating components such as motors.

[0072]

The present invention logically processes two clock signals, a system clock signal and another clock signal, to detect the stop of the system clock signal, and respond to the detection result or the system reset signal. Since the reset signal is generated, it is possible to solve various problems caused by stopping the generation of the system clock signal and stop the device in a safe state.

[Brief description of drawings]

FIG. 1 is a block diagram showing a circuit configuration of a system protection device according to the present invention.

FIG. 2 is a timing chart of input / output signals of the system protection device shown in FIG.

3 is a block diagram showing a first embodiment of a clock signal stop detection unit in the system protection device shown in FIG.

FIG. 4 is a timing chart of input / output signals of the clock signal stop detector shown in FIG.

5 is a block diagram showing a second embodiment of the clock signal stop detector in the system protection device shown in FIG.

6 is a timing chart of input / output signals of the clock signal stop detection unit shown in FIG.

FIG. 7 is a block diagram of a clear signal generation unit used for modifying the clock signal stop detection unit in the system protection device according to the present invention.

8 is a block diagram of a clock signal stop detector using the clear signal generator shown in FIG. 7.

9 is a timing chart of input / output signals in the clock signal stop detector shown in FIGS. 7 and 8. FIG.

FIG. 10 is a block diagram detailing reset signal generating means of the system protection device according to the present invention.

FIG. 11 is a block diagram of a control device using the system protection device according to the present invention.

FIG. 12 is a block diagram showing a first embodiment of a facsimile using the system protection device according to the present invention.

FIG. 13 is a block diagram showing a second embodiment of a facsimile using the system protection device according to the present invention.

FIG. 14 is a block diagram showing a third embodiment of a facsimile using the system protection device according to the present invention.

[Explanation of symbols]

101 ... System protection device, 102 ... Clock signal stop detection unit, 103 ... Reset signal generation unit, 104 ... Clock signal edge detection unit, 105 ... Clear signal generation unit, 10
6 ... Signal level control unit, 1101 ... System clock signal oscillator, 1107 ... Clock signal oscillator, 1106 ...
Real-time clock, 1108 ... Input / output register, 1
109 ... I / O device, 1110 ... System reset signal generating means, 1207 ... Thermal head, 1210 ... Recording control section, 1403 ... Facsimile controller.

Claims (11)

[Claims] 1. A system protection device comprising first and second oscillating means for oscillating and outputting independent clock signals, and reset control means for resetting a part or the whole of the system, wherein the first and second oscillating means are provided. Clock signal stop detection means for logically processing the clock signal output from the second oscillating means and detecting stop of the clock signal output from the first transmitting means, and the reset control means detects the clock signal stop detection. The system protection device is characterized in that a reset signal for resetting the whole or a part of the system is generated based on a detection signal which detects the stop of the output of the clock signal from the first oscillating means. 2. The clock signal stop detecting means according to claim 1, wherein the clear signal generating means for generating a predetermined clear signal and a hold signal from the second clock signal, and the output by the change of the first clock signal. A system protection device comprising: a clock signal edge detection unit that is set and whose output is reset by the clear signal; and a holding unit that holds the output signal of the clock signal edge detection unit by the holding signal. 3. The system protection device according to claim 1, wherein the second clock signal is a clock signal used for clock means. 4. The system protection device according to claim 1, wherein the reset control means generates a reset signal based on a system reset signal or the detection signal. 5. A system clock signal oscillator that oscillates a system clock signal, a real-time clock signal oscillator that oscillates a clock signal for a real-time clock independently of the system clock signal oscillator, and a part or all of the system is reset. In a system protection device having a reset control means, clock signal stop detection means for logically processing a clock signal output from the system clock signal oscillator and a real-time clock signal oscillator to detect stop of the system clock signal is provided, and the reset The control means is configured to generate a reset signal for resetting the whole or a part of the system based on a detection signal which detects the stop of the system clock signal output from the clock signal stop detection means. The stem protection device. 6. The system protection device according to claim 5, wherein the reset control means generates a reset signal based on a system reset signal or the detection signal. 7. A control device comprising a CPU, an input / output register, an input / output device, and a system clock signal oscillator, wherein the CPU controls the input / output register and the input / output device in synchronization with a system clock signal, A clock signal oscillator independent of the system clock signal oscillator; clock signal stop detection means for logically processing a clock signal generated from the clock signal and the system clock signal to detect stop of the system clock signal; A control device comprising reset control means for generating a reset signal when a signal stop is detected. 8. The control device according to claim 7, wherein the reset control means resets the input / output register. 9. The control device according to claim 7, wherein the reset control means resets the input / output device. 10. A CPU, an input / output register, a recording means, a system clock signal oscillator, and a clock signal oscillator for a real-time clock, wherein the CPU synchronizes with the system clock signal and the input / output register and the recording means. In a control device for controlling a clock signal stop detecting means for logically processing a system clock signal and a clock signal for a real-time clock to detect the stop of the system clock signal, and a reset signal when the stop of the system clock signal is detected. A control device comprising a reset control means for generating a noise. 11. The recording means according to claim 10,
A control device comprising a thermal head.