JPS61109154A - Error detecting system for fixed data register - Google Patents

Abstract

PURPOSE:To detect the runaway or the transformation of data of a computer system by providing an error detecting circuit to detect the inversion of data of a fixed data register and checking the contents of said data register at all times or with an optional timing. CONSTITUTION:When the operation of a computer system is started, a service processor 5 reads the data to be set to a fixed data register 1 out of a floppy disk device 6 and at the same time produces a parity bit corresponding to said data. Then the processor 5 sets the data read out by a scan-in action to a parity bit part 2. The contents of the register 1 and the contents of the part 2 are sent to an error detecting circuit 3. The result of detection of the circuit 3 is supplied to an error holding latch 4 and then sent to the processor 5.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a fixed data register error detection method that is capable of detecting errors in fixed data registers such as operating status setting registers and configuration control registers. It is.

[Conventional technology and problems]

A computer system is provided with an operating state setting register and a configuration control register. The operating status setting register is
For example, it specifies which oscillator should be used among a 15n3 oscillator, a 14na oscillator, and a 13n3 oscillator, and which timing should be checked and stopped. The configuration control register instructs the configuration of the computer system. Conventionally, once a value is set in a fixed data register group such as an operating state setting register or a configuration control register in a computer system, the data read from the fixed data register group is used for configuration control or operating state setting. Currently, it is assumed that logic circuits such as fixed data register groups are not subject to data inversion due to alpha rays or power supply noise, and are not equipped with an error detection circuit. however,
As logic elements become highly integrated LSIs, there is a possibility that a phenomenon of data inversion (soft error) due to alpha rays or the like occurring in storage elements may occur.

[Purpose of the invention]

The present invention is based on the above considerations, and provides an error detection method for fixed data registers that can detect errors occurring in a fixed data register group due to alpha rays, power supply noise, etc. It is an object.

[Means to achieve the purpose]

Therefore, the error detection method for fixed data registers of the present invention sets data read from an external storage medium as an initial value when the computer starts operating, and then sets fixed data registers whose values are not changed during normal operation thereafter. This register error detection method is characterized by providing an error detection circuit for detecting inversion of data in the fixed data register, and checking the contents of the fixed data register at all times or at any timing.

[Embodiments of the invention]

Hereinafter, the present invention will be explained with reference to the drawings. The figure is a block diagram of one embodiment of the present invention. In the figure, 1 indicates fixed data such as configuration control registers and operating state setting registers.
2 is a parity bit section for a fixed data register, 3 is an error detection circuit, 4 is an error holding latch, 5 is a service processor, 6 is a floppy disk device, and Ll to L4 are signal lines, respectively. .

When the computer system starts operating, that is, when the power is turned on, the service processor 5 stores the fixed data register 1.
The data to be set in the floppy disk device 6 is read out from the floppy disk device 6, a parity bit is generated for the data, and the successive data is transferred to the signal line L1 by scan-in.
and set it in fixed data register 1 via
A parity bit is set in parity bit section 2 via signal line L1'. Information such as configuration control or operation state setting set in the fixed data register 1 is distributed to the computer system etc. via the signal line L3.

Contents of fixed data register 1 and parity/focus section 2
The contents are sent to the error detection circuit 3 via the signal line L3. The detection result of the error detection circuit 3 is input to the error holding latch 4. A pulse train that turns on at regular intervals is always input to the clock terminal of the error holding latch 4. The output of the error holding edge 4 is sent to the service processor 5 via the signal line L4, and when the signal on the signal line L4 is turned on, an interrupt is applied to the service processor 5.

If data inversion occurs in fixed data register 1 or parity check section 2 due to alpha rays, power supply noise, etc.
The error detection circuit 3 detects an error, and the error holding latch 4 outputs an on signal. The service processor 5 recognizes that an error has occurred in the fixed data register l, causes the computer system to interrupt processing, and
The data to be set in the fixed data register 1 is read again from the 2-bit disk device 6, a parity bit is generated for the read data, the read data is set in the fixed data register 1, and the parity bit is set as the parity bit. Set in bit section 2. As a result, if the error is cleared, the service processor 5 treats it as a soft error in the flip-flop and causes the computer system to resume the interrupted process. If the error is not cleared even after resetting the data in the fixed data register 1 and parity bit section 2, the system is taken down as a bird error. In the above description, the clock is constantly supplied to the error holding latch 4, but the clock may be applied at any timing.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, it is possible to detect runaway of a computer system or data corruption that occurs when data set in a fixed data register is reversed due to alpha rays, power supply noise, etc. I can do it.

[Brief explanation of the drawing]

The figure is a block diagram of one embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Fixed data registers such as configuration control registers and operating state setting registers, 2... Parity bit section for fixed data registers, 3... Error detection circuit, 4... Error holding latch, 5 . . . Service processor, 6 . . Floppy disk device, Ll to L4 . . . Signal line.

Claims (1)

[Claims] An error detection method for fixed data registers in which data read from an external storage medium is set as an initial value when the computer, etc. starts operating, and the value is not changed during normal operation thereafter. 1. An error detection method for a fixed data register, characterized in that an error detection circuit for detecting a reversal of the fixed data register is provided, and the contents of the fixed data register are checked constantly or at an arbitrary timing.