JPH0652070A - Device and method for data protection in integrated circuit - Google Patents

Abstract

PURPOSE:To surely save internal state data to external memory when power interruption occurs by restoring data saved via a scan pass to an original register. CONSTITUTION:A counter 4 counts a scan clock SC, and outputs the address A of the external memory 3 in which the data outputted from an integrated circuit 2 is stored. The integrated circuit 2 outputs the internal state data from a scan output terminal SO synchronizing with the scan clock SC, and such data is supplied to the data input terminal D1 of the external memory 3, and is stored in an address-designated position by the counter 4. In other words, the internal state data transferred synchronizing with the scan clock SC by utilizing the scan pass of the integrated circuit 2 can be outputted from the scan output terminal SO and it can be saved to the external memory 3. Thence, when the power source of a system is restored. the data restoration mode of resume function is set, and the system restores saved internal state data to the integrated circuit 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit data protection device for protecting internal state data of an integrated circuit used in a computer or the like.

[0002]

2. Description of the Related Art Many computer systems such as personal computers have a resume function. The resume function saves the stored data in various registers to the non-volatile memory when the computer power is turned off, and sets the saved storage data in the original register when the power is turned on again. This is a function that enables data processing to be executed from the state immediately before the switch is turned off.

[0003]

However, conventionally, when there is a large amount of data to be saved, it takes time to save the data. For this reason, there is a problem that the time from when the switch is turned off until the computer is actually turned off becomes abnormally long, and in some cases, data cannot be completely saved.

For example, a so-called state machine, such as a graphic controller, which transitions to the next state depending on the previous state, is an integrated circuit (LS) having a large number of various registers such as temporary registers and control registers.
I) is used. Therefore, when saving the internal state data of the integrated circuit, the data transfer may take too much time, and the resume function may not be realized.

The object of the present invention was made in view of the above circumstances, and in an integrated circuit having a large number of registers,
An object of the present invention is to provide a data protection device for an integrated circuit that can surely save internal state data to an external memory when power is interrupted. Another object of the present invention is to provide an integrated circuit capable of saving data held in an internal register at high speed.

[0006]

In order to achieve the above object, an integrated circuit according to claim 1 responds to an external signal and a plurality of registers connected so as to form a scan path, and is in a data saving mode. , A data saving means for forming a scan path in the plurality of registers and reading the data held in each register to the outside via the formed scan path; and a data saving means for responding to an external signal to the plurality of registers in the data restoration mode. Data recovery means for forming a scan path and for restoring the data saved through the formed scan path to the original register.

According to a second aspect of the present invention, in the data saving mode, a scan path is formed in a plurality of registers in the integrated circuit, and the data held in each register is read out through the formed scan path. A data save step of saving the read data in the protection memory, and reading the save data for protection and forming a scan path in the plurality of registers in the data recovery mode, and saving via the formed scan path And a data restoring step of restoring the original data to the original register.

Further, in the apparatus according to the third aspect, the data protection memory means for storing the internal state data of the integrated circuit in the data saving mode and the input / output of the data of a predetermined bit width to / from the integrated circuit. Data input / output means, serial / parallel conversion of the internal state data read through the scan path into data of the predetermined bit width in the data save mode, and the data protection memory means through the data input / output means And a data saving means for storing the internal state data from the data protection memory means in the data restoration mode and input from the data input / output means to serially store the data having the predetermined bit width in the internal state data. Data recovery means for converting the data into data and recovering through the scan path.

According to a fourth aspect of the present invention, in the data saving mode, the internal state data of the integrated circuit is stored in the data protection memory means, and the data of a predetermined bit width is input / output to / from the integrated circuit. And a step of performing serial / parallel conversion of the internal state data read through the scan path into data of the predetermined bit width in the data save mode, storing the data in the data protection memory means, and saving the data. In the return mode, there is a step of reading the internal state data from the data protection memory means, converting the data of the predetermined bit width into the serial internal state data, and returning through the scan path.

[0010]

According to the first to fourth aspects of the invention, at the time of data saving and data restoration, data is sequentially transferred in the scan path (shift register) composed of registers and read out to the outside, or It is set in the original register. Therefore, even if the number of internal registers is large, the held data can be saved / restored in a short time.

[0011]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a data protection apparatus according to the first embodiment. This device has an LSI test device 1, an integrated circuit (LSI) 2, an external memory 3, and a counter 4. The data held in the internal register of the integrated circuit 2 is the object of saving / protection in this embodiment.

The LSI test apparatus 1 is an apparatus for testing the integrated circuit 2 by using the scan path in the integrated circuit 2 by the scan path method. The integrated circuit 2 has a scan path (shift path circuit) configured by a series of registers (flip-flops) inside, and is an LSI (large scale integrated circuit) used for a state machine such as a graphic controller. The integrated circuit 2 is, for example, a processor (C
PU).

The external memory 3 is, for example, a RAM backed up by a battery and serves as a save destination of internal data of the integrated circuit 2 in the data save mode of the resume function. The external memory 3 may be a non-volatile memory. The output data of the counter 4 is supplied to the external memory 3 as the address A. The counter 4 updates the count value in synchronization with the scan clock SC. Next, the operation of the data protection device of FIG. 1 will be described with reference to the flowchart of FIG.

In the normal test mode (test of the integrated circuit 2), the LSI test apparatus 1 supplies an instruction signal to the scan control terminal SC of the integrated circuit 2 to serially connect the internal registers to form a scan path. At the same time, the scan clock SC is input to the scan clock terminal SCK, and the scan path system test is executed (YES in step S1). The LSI test apparatus 1 supplies test data (scan path data SP1), which is serial data, through the scan input terminal SI of the integrated circuit 2 in synchronization with the scan clock SC (step S2).

On the other hand, the LSI test apparatus 1 includes an integrated circuit 2
Output data (scan path data SP2) corresponding to the test data is received in synchronization with the scan clock SC via the scan output terminal SO (step S).
3). The scan path data SP2 is compared with the reference data prepared in advance, and the circuit test of the integrated circuit 2 is executed.

Next, when the power supply of the system including the integrated circuit 2 is interrupted, the resume function is set, and the internal state data of the integrated circuit 2 is saved in the external memory 3 (NO in step S1). The operation will be described. In the data save mode of the resume function, the system CPU interrupts the normal operation of the integrated circuit 2 (YE in step S4).
S, S5). The data saving mode is executed not only for the resume function but also for task switching, interrupt processing, and the like.

The CPU supplies an instruction signal to the scan control terminal SC of the integrated circuit 2 to serially connect the internal registers to form a scan path and also supplies the scan clock SC to the scan clock terminal SCK.
At the same time, the scan clock SC is supplied to the counter 4 and activated (step S6). Counter 4 scans
The clock SC is counted and the address A of the external memory 3 for storing the data output from the integrated circuit 2 is output.

The integrated circuit 2 outputs the internal state data from the scan output terminal SO in synchronization with the scan clock SC. This internal state data is supplied to the data input terminal DI of the external memory 3 and stored at the position addressed by the counter 4 of the external memory 3 (step S
7).

That is, utilizing the scan path of the integrated circuit 2, the internal state data transferred in synchronization with the scan clock SC is output from the scan output terminal SO and saved in the external memory 3. Since the external memory 3 is backed up by the battery, the internal state data of the integrated circuit 2 is surely saved even while the system power is off.

If the external memory 3 has a sufficient storage capacity, the CPU may output the memory bank switching signal SEL to the external memory 3 to control the bank switching of the external memory 3. This allows the external memory 3
It becomes possible to store the internal state data in a memory bank different from the memory bank used for the normal data processing of. Further, when the bank of the external memory 3 is switched in response to task switching, one LS shared by a plurality of tasks
The internal state data of I can be stored in the corresponding memory bank for each task.

Next, when the power supply of the system is restored, the resume mode data restoration mode is entered, and the system performs a process of restoring the saved internal state data to the integrated circuit 2 (YES in step S8). The CPU of the system presets the counter 4, supplies the scan clock SC to activate the counter 4, and updates the count value (step S9). The preset value of the counter 4 is the address A of the external memory 3 which stores the internal state data in the data saving mode. Further, the CPU sets the external memory 3 to the read mode.

The external memory 3 reads the data from the storage location designated by the address supplied from the counter 4 and outputs it to the data output terminal DO. This output data is supplied to the scan input terminal SI of the integrated circuit 2 (step S10). Integrated circuit 2 is scan clock SC
In synchronization with, the internal state data supplied to the scan input terminal SI is input and shifted on the scan path. When all the data is set in the original register, CP
U stops the supply of SC of the scan clock, and
The supply of the instruction signal supplied to the scan control SC is stopped, the internal register is set to the normal state, and the scan path is eliminated. As described above, the saving and restoring of the data of the register in the integrated circuit 2 can be realized by using the scan path.

FIG. 2 is a block diagram showing the structure of a data protection device according to the second embodiment of the present invention. In the second embodiment, each mode of data saving and data restoring of the integrated circuit 2 is executed by using a data bus (for example, 8 bit width) 6 connected to the I / O port 5 of the system.

As shown in FIG. 2, the integrated circuit 2 includes multiplexers 7, 20, and 21 as a series of registers R1.
~ Rn, internal control circuit 8, counter 9, P / S circuit 10
And a buffer circuit 13 and an internal data bus 11 connected to the data bus 6 of the system through the data input / output terminal 12.

The registers R1 to Rn are a series of shift registers or flip-flops forming a scan path. It is assumed that the registers R2 and R3 are flip-flops that do not need to retain their internal states when switching tasks.

The internal control circuit 8 is provided in the registers R1 to Rn.
Scan path control signal and scan clock terminal S
The scan clock signal SCK from C is supplied. Each of the registers R1 to Rn has a data input terminal and an output terminal for a normal purpose as well as a data input terminal and an output terminal for a scan path. When the scan path control signal is off, the registers R1 to Rn have a predetermined function. When the normal input / output terminals connected so as to form a logic circuit are enabled and the scan path control signal is on, the serial path as shown in FIG. 2 is formed to form the scan path consisting of the registers R1 to Rn. The input / output terminal for the scan path connected to is enabled. The output terminals for the eight registers Rn-7 to Rn scan lines are supplied to the buffer 13. The buffer 13 has an internal control circuit 8
In response to the control signal from, the 8-bit data on the scan path is output in parallel to the internal data bus 11.

The multiplexer 20 supplies the data supplied from the register R1 to one of the register R2 and the multiplexer 21 in response to the switching signal from the internal control circuit 8. Further, the multiplexer 21 supplies one of the data supplied from the register R3 and the data supplied from the multiplexer 21 to the register R4 in response to the switching signal.

The multiplexer 7 is responsive to a control signal from the internal control circuit 8 to provide either one of the test data supplied from the scan input terminal SI and the internal state data supplied from the P / S (parallel / serial) conversion circuit. To output.

The internal control circuit 8 is connected to the CPU of the system through the control terminal 22, supplies various signals to the register and the multiplexer, and controls the timing at which the CPU accesses the integrated circuit 2.

The counter 9 has a scan clock terminal S
The count operation is performed by the scan clock SC supplied to CK, and the count value is supplied to the internal control circuit 8 and the P / S circuit 10.

The P / S circuit 10 is a parallel / serial conversion circuit, and converts the parallel data restored through the internal data bus 11 into serial data in response to the count value of the counter 9. The buffer 13 is a register Rn-7
Output data (8 bits) of .about.Rn is output onto internal data bus 11 in response to a control signal from internal control circuit 8. Next, the operation of the circuit according to the second embodiment will be described with reference to FIG. (1) During normal operation, the scan path shown in FIG. 2 does not function, and each register operates to form a necessary logic circuit.

(2) In the normal test mode, the CPU supplies control data to the internal control circuit 8 to instruct the formation of the scan path. In response to this control data, the internal control circuit 8 supplies a control signal to the registers R1 to Rn to form a scan path, further causes the multiplexer 20 to supply the data to the register R2, and the multiplexer 21
To select the output of the register R3.

After that, the CPU instructs the LSI test apparatus 1 to start the test. In response to this instruction, the LSI test apparatus 1 scans the integrated circuit 2 with the scan clock terminal SC.
The scan clock SC is input to K and a scan type test process is executed (YES in step S20). That is, the LSI test apparatus 1 applies the test data (scan path data SP1) to the scan input terminal SI of the integrated circuit 2.
) Is serially supplied in synchronization with the scan clock SC (step S21). The multiplexer 7 responds to the control signal from the internal control circuit 8 to transfer the test data supplied from the scan input terminal SI to the registers R1 ...
Output to the scan path composed of Rn. The registers R1 to Rn take in the data supplied in synchronization with the scan clock SC and output the held data.

The LSI test apparatus 1 receives output data (scan path data SP2) corresponding to the test data from the scan output terminal SO of the integrated circuit 2 in synchronization with the scan clock SC (step S22). The scan path data SP2 is compared with the reference data prepared in advance, and the circuit test of the integrated circuit 2 is executed.

(3) When the power of the system including the integrated circuit 2 is interrupted while the resume function is turned on (NO in step S20), the process of saving the internal state data of the integrated circuit 2 is executed. (YE in step S23
S).

More specifically, the CPU supplies control data to the internal control circuit 8 and gives an instruction to save the data. The internal control circuit 8 supplies a control signal to the registers R1 to Rn to form a scan path, and further, the multiplexer 2
0 causes data to be supplied to the register R2 and causes the multiplexer 21 to select the output of the register R3. Further, the internal control circuit 8 activates the counter 4.

The CPU scans the LSI test apparatus 1
The clock SC is output. The counter 4 is an octal counter, and outputs a signal to the internal control circuit 8 every time the scan clock SC is counted by 8 clocks. The internal control circuit 8 controls the buffer B in response to the count value from the counter 4, and registers R every eight scan clocks.
The outputs of n-7 to Rn are output to the internal data bus 11. That is, the serial internal state data transferred through the scan path is converted into 8-bit parallel data and output to the internal data bus 11 (step S24). Further, the internal control circuit 8 notifies the CPU of the access timing every 8 scan clocks.

The internal state data read through the internal data bus 11 and the data input / output terminal 12 of the integrated circuit 2 are output to the data bus 6 of the system. CPU is
In response to the timing signal supplied from the internal control circuit 8, the data on the data bus 6 is sent to the I / O port 5 corresponding to the external memory 3 (step S25). CPU
Stores the internal state data read to the I / O port 5 in the external memory 3 (step S26). The CPU controls the completion of reading the internal state data from the integrated circuit 2 by performing a check process or an interrupt process using a status register prepared in advance.

In this way, the internal state data held in the integrated circuit 2 can be saved in the external memory 3 before the power of the system is interrupted. Since the external memory 3 is backed up by the battery, the saved internal state data of the integrated circuit 2 is surely saved.

When the power of the system is restored, the system performs a process of restoring the saved internal state data to the integrated circuit 2 (YES in step S27). The CPU divides the internal state data saved in the external memory 3 into 8-bit units in the order of reading in the data saving mode and temporarily holds the data in the I / O port 5 (step S28). The CPU also supplies the scan clock SC to activate the counter 4.

The CPU uses the internal state data held in the I / O port 5 in 8-bit units as the data bus 6 of the system.
And input to the internal data bus 11 of the integrated circuit 2 through the data input / output terminal 12. The P / S circuit 10 latches the parallel internal state data input to the internal data bus 11. The counter 9 is an octal counter, counts the number of clocks of the scan clock SC, and supplies the count output to the P / S circuit 10. P / S circuit 10
Converts the latched 8-bit parallel data into serial data according to the count output (step S2
9).

The multiplexer 7 stores the serial internal state data supplied from the P / S circuit 10 in the registers R1 to R1.
Output to the scan path consisting of Rn (step S3)
0). Registers R1 to Rn are used for scan clock SC
The supplied data is shifted in synchronization with. That is, the integrated circuit 2 uses the scan path to restore the internal state data saved in the external memory 3 to the original register.
The CPU ends the internal state data writing (restoring) process when the saved data is reset to the original register by the check process by the status register or the interrupt process.

In this way, by using the scan path and the data bus, the internal state data can be saved when the power is interrupted and the internal state data saved when the power is restored can be restored. Therefore, the internal state data can be read and saved at high speed and reliably as compared with the case where each register of the integrated circuit 2 is sequentially addressed and the held value is read. Therefore, even if the number of registers is large, the internal data can be saved in a short time.

(4) In the operation at the time of task switching, the multiplexer 20 supplies the data to the multiplexer 21,
The operation is the same as the above-described data saving / restoring operation except that the multiplexer 21 selects the output data of the multiplexer 20. Next, a third embodiment of the present invention will be described with reference to FIGS.

This embodiment is an example in which the present invention is applied to a microprocessor. In FIG. 5, reference numeral 111
Is a bus interface, which exchanges commands and data with external circuits. Reference numeral 112 is an instruction buffer, which holds an instruction fetched by the bus interface 111. Reference numeral 113 is a decoder, which decodes the instruction held in the instruction buffer 112,
Generate a control signal. Reference numeral 114 is an execution unit, which executes the instruction decoded by the decoder 113.
Reference numeral 115 is a state controller, which controls the entire microprocessor. Reference numeral 116 is an interface signal, which includes an address, data, and a control signal.

The register 121 for holding the state information and data necessary for the resume operation in the effective unit 114 and the state controller 115 shown in FIG. 5 is connected in series as shown in FIG. Each register 121 has
Data input (D) for normal operation, clock input (C
P), data output (Q), serial data input (S
I), serial data output (SD), scan lock input (A, B).

In normal operation, A = B = “H”, and the register 121 operates at the rising edge of the clock CP. At this time, the value of the SI input does not affect the operation.
On the other hand, during the scan operation, CP = “H” is set, data is taken in by A = negative pulse and data is output by B = positive pulse. At this time, the value of the D input does not affect the operation. The operation of the shift register 121 is shown in the form of a timing chart in FIG. 7 and in the form of a truth table in FIG.

A resume request signal is one of the control signals of the interface signal 116 of FIG. 5, and when a resume request is input to the present microprocessor from an external circuit, the state controller 115 stops the normal operation of the microprocessor. , Resume operation is started.

The data signal of the interface signal 116 includes serial data out (SD output of the register n in FIG. 6). First, this value is stored in the external memory (not shown) connected to the bus interface 111. To do. Next, the state controller 115 uses the clock C.
With P fixed at "H", clocks A and B are used to shift the data held in the serially connected registers. That is, the value of the register (i-1) is transferred to the register (i) (i is 1
Through n). By repeating this operation a necessary number of times, all the values of the serially connected registers are saved in the external memory.

By the above operation, after saving the data held in all the registers, the microprocessor is set to H level.
The ALT state is entered, and the HALT signal indicating this is output to the outside via the bus interface 111. This HAL
If the T signal is detected by an external circuit, turn off the power of the device,
The device can be stopped.

When the device is powered on again, the microprocessor sequentially supplies the data saved in the external memory to the SI input of the register 121 in the same manner as in the case of saving the register, and shifts the contents in the shift register. Transfer sequentially.
When the data is returned to all the registers, the resume operation is ended and the normal operation is resumed.

[0053]

As described above in detail, according to the present invention, the internal path data is surely saved when the power is interrupted by using the scan path used as the test circuit of the scan system of the integrated circuit, and the power is supplied. The internal state data can be restored to the integrated circuit upon restoration. Therefore, the internal state data of the integrated circuit provided with a large number of various registers can be saved at high speed and reliably,
The data of the integrated circuit can be surely protected. Also, if multiple internal states are retained, multiple tasks can
It is possible to access one LSI.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a data protection device for an integrated circuit according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing the configuration of a data protection device for an integrated circuit according to a second embodiment of the present invention.

FIG. 3 is a flowchart for explaining the operation of the first embodiment.

FIG. 4 is a flowchart for explaining the operation of the second embodiment.

FIG. 5 is a block diagram showing a configuration of an integrated circuit according to a third embodiment of the present invention.

6 is a block diagram showing a configuration of a register of the integrated circuit shown in FIG.

FIG. 7 is a timing chart for explaining the operation of the sixth register.

FIG. 8 is a diagram for explaining the operation of a sixth register.

[Explanation of symbols]

2 ... Integrated circuit (LSI), 3 ... External memory, 4, 9 ... Counter, R1 to Rn ... Register, 111 ... Bus interface, 112 ... Instruction buffer, 113 ... Decoder,
114 ... Execution unit, 115 ... State controller, 116 ... Interface signals, 121 ... Register.

Claims (4)

[Claims] 1. A plurality of registers connected so as to form a scan path, and a plurality of registers forming a scan path in response to an external signal in a data save mode, and the scan path is formed via the formed scan path. Data saving means for reading the data held in each register to the outside, and in response to an external signal, in the data restoration mode, a scan path is formed in the plurality of registers, and the data saved via the formed scan path is saved. An integrated circuit comprising: a data restoring means for restoring the original register. 2. In a data saving mode, a scan path is formed in a plurality of registers in an integrated circuit, the data held in each register is read out through the formed scan path, and the read data is used as a protection memory. And a data saving step of saving the data in the data recovery mode, reading the saved data for protection, forming a scan path in the plurality of registers, and saving the data saved via the formed scan path. A method for saving / restoring data held in an internal register of an integrated circuit, comprising a data restoring step of restoring to a register. 3. A data protection device for an integrated circuit, which uses a scan method for performing a circuit test using a scan path formed inside the integrated circuit, wherein internal state data of the integrated circuit is stored in a data save mode. Data protection memory means, data input / output means for inputting / outputting data of a predetermined bit width to / from the integrated circuit, and the internal state data read through the scan path in the data saving mode to the predetermined state. Data saving means for performing serial / parallel conversion to data having a bit width of, and storing the data in the data protection memory means through the data input / output means, and reading the internal state data from the data protection memory means in the data restoration mode. Input from the data input / output means, and the data of the predetermined bit width It converts the state data data protection apparatus for an integrated circuit, characterized by comprising a data restoring means for returning through the scan path. 4. A data protection method for an integrated circuit using a scan method for performing a circuit test using a scan path formed inside the integrated circuit, wherein the internal state data of the integrated circuit is data protected in a data save mode. Memory means for storing the data, inputting / outputting data of a predetermined bit width to / from the integrated circuit, and in the data saving mode, the internal state data read through the scan path to the predetermined bit width. Serial / parallel conversion to the data of the above, storing and saving in the data protection memory means, and reading the internal state data from the data protection memory means in the data restoration mode, A step of converting the data into the serial internal state data and returning through the scan path. Data protection method characterized by comprising a.