JP2008210358A - Data processor, and data control circuit used therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data processor capable of saving/restoring properly a data of an electronic circuit part in response to turning-on/-off of an electric power source, without requiring a sub-electric power source and a data back-up operation during normal operation. <P>SOLUTION: This data processor of the present invention has a data save control part 2 for saving all the data required for restoring a state of the electronic circuit part 1 into a nonvolatile memory 3, during a period until an electric power source voltage VDD reaches an operation securing lower-limit voltage of the processor after detecting a drop of the electric power source voltage VDD, when the electric power source is broken. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a data processing apparatus (microprocessor, image processor, multimedia processor, IP core, personal computer, network server, mobile device, game machine, PDA [Personal Digital / Data Assistants], etc.) provided with an electronic circuit unit In addition, the present invention relates to a data control circuit used therefor, and particularly relates to a data saving / restoring technique.

  Conventionally, temporary storage data such as register data of an electronic circuit unit provided in a data processing device disappears at the same time as the power is turned off, and cannot be restored to the original state even after the power is restored. For this reason, in the conventional data processing apparatus, when an unintended power interruption such as a power failure occurs, damage such as loss of work data is incurred.

  For data processing devices that require software control, such as personal computers, it is necessary to reload the software when the power is turned on again. Therefore, it takes a long time to turn the power on / off (hardware startup). The user was wasted stress. For this reason, in the conventional data processing apparatus, even when the electronic circuit unit is in the process waiting state, the power supply to the electronic circuit unit cannot be easily cut off, resulting in an increase in wasted power consumption.

  In addition, patent documents 1-5 etc. can be mentioned as a prior art relevant to the above.

  In Patent Document 1, a running state of a program being processed is stored when the power is turned off, and the program is continuously executed when the power is restored. In such an apparatus that can hold the program by, for example, an off-state detecting means for detecting that the power is turned off, a plurality of stack areas for storing the program running state when the power is turned off, and storing in the stack area Provided with an identification means for identifying whether the running program is a power-off program that operates when the power is turned off, and when the power-off state, the program running state is sequentially stored in the plurality of stack areas, and the power recovery state Conversely, the program running state is read sequentially, and this is read until the read program is no longer a power-off program. Power failure recovery method being characterized in that the Suyo has been disclosed or proposed.

  In Patent Document 2, it is determined whether or not each area of the buffer memory satisfies the save condition at regular time intervals, the data in the area satisfying the save condition is saved in the magnetic disk device, and When a failure occurs in the buffer memory in the memory, the valid data is saved by distinguishing between the area where the valid data is saved and the area where the invalid data is saved using the invalid area judgment means. A data evacuation / restoration method has been disclosed and proposed in which data is restored using the data saved in the magnetic disk unit, and invalid data is saved based on the update history information. .

  Patent Document 3 discloses a data holding circuit that holds data by connecting the first and second inverter circuits in a loop shape at the time of data latch, and an input node of the first inverter circuit at the time of data writing. In a state where one end is connected, a nonvolatile state corresponding to data existing in the data holding circuit is stored, and at the time of data restoration, the one end is connected to the input node of the first inverter circuit, and the other end is used for reading. By applying a signal, a charge corresponding to the stored nonvolatile state, which is higher or lower than the threshold voltage of the first inverter circuit, is input to the input node of the first inverter circuit. A non-volatile memory element configured to discharge the generated charge to an input node of the first inverter circuit, and the data holding A path between a non-volatile storage element connection node defined as a connection node between an input node of the first inverter circuit and one end of the non-volatile storage element; and an output node of the second inverter circuit Insertion is controlled so that the relay state is established at the time of data latching and data writing, and at the time of data restoration, the disconnection state is established when the read signal is applied, and then the relay state is established after a predetermined period. The applicant of the present invention has disclosed and proposed a data holding device provided with a loop interrupting gate that is controlled to be interrupted.

  Patent Document 4 includes a processing device for executing an instruction, which includes a sequential circuit including a plurality of combinational logic circuits and a plurality of storage elements that are combined with them to form a sequential circuit; Read a plurality of internal data held in the save memory and the plurality of storage elements, save to the save memory, read the plurality of saved internal data from the save memory, and A recovery circuit for recovering to the storage element, and after the plurality of internal data are saved by the save recovery circuit, a power supply voltage for a standby state is supplied to the processing device, and the save recovery circuit restores the save data. A power supply for switching the power supply voltage supplied to the processing device so that the power supply voltage for normal operation is supplied to the processing device before a plurality of internal data is recovered. Data processing apparatus having a supply switching circuit, has been disclosed and proposals.

In Patent Document 5, in a warm boot method of a program in a computer system comprising at least a central processing unit having a main storage memory and, if necessary, an external storage device, immediately before the computer system is turned off. When a power failure interrupt indicating power failure is generated and the power failure interrupt occurs, the state of the central processing unit registers and peripheral integrated circuits at that time is saved to a specific address of the main memory, and a flag indicating a power failure Set and wait until the computer system is powered off, and at the same time the computer system is powered off, the power supply to the main memory is switched from the power source to the battery for backup. As soon as it is turned on, the power supply to the main memory When the power failure flag is set and the power failure interrupt flag is set, the state of the registers and peripheral integrated circuits saved by the power failure interruption is reset and the power failure flag is reset. If not set, a warm boot method of a program in a computer system is disclosed and proposed, wherein a control program and a processing program are loaded from the external storage device.
JP 58-169218 A JP-A-4-107725 JP 2004-186874 A Japanese Patent Laid-Open No. 10-78836 JP-A-3-163617

  Certainly, according to the prior arts of Patent Documents 1 to 5, it is possible to save / restore or hold data in the electronic circuit unit.

  However, in the prior art of Patent Document 1, it is necessary to provide a sub power source separately from the main power source, such as an uninterruptible power supply (UPS) and a battery backup. It was a factor inviting.

  Further, in the prior art of Patent Document 2, since it is necessary to perform a data backup operation during a normal operation, it is a factor that lowers the capacity of the data processing apparatus, and if the frequency of data backup is lowered, There was a problem that the amount of data loss increased.

  The prior art disclosed in Patent Document 3 is a technique for allowing a register used in a data storage circuit in an electronic circuit to hold data without power supply, and is a technique for saving / restoring data. There wasn't.

  The prior art of Patent Document 4 is a technique for reducing power consumption by reducing the leakage current during standby by switching the power supply voltage before and after data saving, and the power supply is cut off. No assumption was made about the data saving / restoring at that time.

  Further, the prior art of Patent Document 5 is a technique for saving / restoring the state of the registers of the central processing unit and the peripheral integrated circuit by a program executed on the central processing unit. Therefore, it is necessary to reload the restoration program every time data is restored, and a long time is required for power on / off (hardware activation). In addition, when the existing system is provided with a data saving / restoring function, the compatibility of the program cannot be maintained, so that the program needs to be corrected. Further, in the data saving / restoring process by software processing, the process itself takes a long time.

  In view of the above problems, the present invention can appropriately save / restore data in an electronic circuit unit in accordance with power on / off without requiring a sub power source or a data backup operation during normal operation. An object is to provide a data processing apparatus.

  In addition, the present invention can be realized in a short development period by effectively utilizing the design assets of existing electronic circuits (ICs, LSIs, IP cores, etc. that have been put on the market) without making large-scale changes. An object of the present invention is to provide a data control circuit and a data processing device using the same, in order to realize an improvement in convenience of the electronic circuit and a reduction in power consumption during standby in terms of cost.

  It is another object of the present invention to provide a data processing device that can prevent malfunction even when the completion timing of data restoration varies for each of a plurality of data processing devices.

  In order to achieve the above object, the data processing apparatus according to the present invention provides an electronic circuit between when a power supply voltage drop is detected and when the power supply voltage reaches the operation guarantee lower limit voltage when the power is shut off. A configuration (first configuration) is provided that includes data saving control means for saving all data necessary for restoring the state of each section in the nonvolatile memory.

  Further, the data processing device having the first configuration may be configured such that, when the power is turned on, the nonvolatile memory is in a period from when the power supply voltage reaches the operation guarantee lower limit voltage until the electronic circuit unit starts operating. It is preferable to adopt a configuration (second configuration) including data return control means for returning data saved in the memory to the electronic circuit unit.

  Further, in the data processing device having the first or second configuration, the electronic circuit unit uses a shift register structure to save / restore data necessary for returning the state by serial data transfer. A configuration (third configuration) is preferable.

  Further, in the data processing device having the third configuration, the electronic circuit unit is configured to change a flip-flop to a shift register structure in accordance with a predetermined control signal separately from the normal first signal path. A configuration (fourth configuration) including a signal path (such as a scan path) may be used.

  The data processing device having the third or fourth configuration converts the data serially input from the electronic circuit unit to parallel conversion and outputs the data to the nonvolatile memory when saving data, while A configuration (fifth configuration) including a serial / parallel conversion unit that serially converts data input in parallel from the nonvolatile memory and outputs the converted data to the electronic circuit unit may be employed.

  In the data processing apparatus having any one of the first to fifth configurations, the nonvolatile memory uses any one of a hysteresis characteristic of a ferroelectric material, a magnetoresistive effect of a magnetic material, or a phase change of an element. Thus, the data may be stored in a nonvolatile manner (sixth configuration).

  In addition, the data control circuit according to the present invention is an electronic circuit having a data input port and a data output port for accessing a memory element inside the circuit from the outside of the circuit (IC, LSI, IP core having a track record in the market, etc. And a data saving control function for saving the data of the electronic circuit outside the circuit (memory, register, etc.) via the data output port (seventh configuration).

  In the data control circuit having the seventh configuration, the data inside the electronic circuit is register data, and the register data saved outside the circuit via the data input port is stored in the register of the electronic circuit. A configuration (eighth configuration) having a data return control function for returning may be used.

  The data control circuit having the eighth configuration monitors power on / off of the electronic circuit, saves the register data of the electronic circuit when the power is shut off, and stores the register data when the power is turned on. A configuration for returning to the register of the electronic circuit (a ninth configuration) is preferable.

  Alternatively, the data control circuit having the eighth configuration includes a power control unit that controls power on / off of the electronic circuit, and a state monitoring unit that monitors an operating state of the electronic circuit, and When the electronic circuit enters a standby state, the register data is saved and the power to the electronic circuit is shut off. When the electronic circuit is to be returned from the standby state, the electronic circuit is turned on and the register data is stored. A configuration for performing the return (tenth configuration) may be used.

  In the data control circuit having the tenth configuration, the state monitoring unit monitors an input / output signal exchanged between the electronic circuit and a peripheral circuit to determine an operation state of the electronic circuit. A configuration (eleventh configuration) is preferable.

  Further, in the data control circuit having the eleventh configuration, the state monitoring unit is configured such that when the data request signal is sent from the electronic circuit to the peripheral circuit, the electronic circuit is in a standby state. On the other hand, when a response signal is sent from the peripheral circuit to the electronic circuit, it is preferable to detect that the electronic circuit should be returned from the standby state (a twelfth structure).

  The data control circuit having the eighth configuration may be configured to replace the register data (a thirteenth configuration) in accordance with processing executed by the electronic circuit.

  The data control circuit having the thirteenth configuration may be configured to simultaneously execute a data saving operation and a data restoring operation (fourteenth configuration) when the register data is exchanged.

  A data processing apparatus according to the present invention includes an electronic circuit having a register data input port and a register data output port for accessing a register in the circuit from the outside of the circuit, and any of the seventh to fourteenth configurations. And a storage circuit as a save destination of the register data (fifteenth configuration).

  In the data processing apparatus having the fifteenth configuration, the electronic circuit and the data control circuit may both be integrated in the same chip (sixteenth configuration).

  Alternatively, in the data processing device having the fifteenth configuration, the electronic circuit and the data control circuit may each be configured to be integrated in separate chips (seventeenth configuration).

  Here, in the data processing device having any one of the fifteenth to seventeenth configurations, the electronic circuit uses a parallel input / output of a plurality of register data in parallel as the register data input port and the register data output port. A configuration having an port (eighteenth configuration) is preferable.

  Alternatively, in the data processing device having any one of the fifteenth to seventeenth configurations, the electronic circuit switches the flip-flop to a shift register structure in accordance with a predetermined control signal, separately from the normal first signal path. A second signal path (scan path, JTAG, etc.) for connecting the second signal path and inputting / outputting a plurality of register data in series as the register data input port and the register data output port A configuration having a serial port (a nineteenth configuration) may be used.

  In the data processing device having the nineteenth configuration, the register data input port and the register data output port of the electronic circuit may be configured to be debug ports (twentieth configuration).

  Further, the data processing device having any one of the fifteenth to twentieth configurations includes, as the storage circuit, SRAM [Static Random Access Mmemory], DRAM [Dynamic RAM], EEPROM [Electronically Erasable and Programmable Read Only Memory], flash Memory, FeRAM [Ferroelectric RAM], MRAM [Magnetroresistive RAM], PRAM [Phase change RAM], RRAM [Resistance RAM], NVSRAM [Non-Volatile SRAM], BBSRAM [Batery Backup SRAM], and similar memories, or , A latch, a register, and a storage element similar to the above (a twenty-first configuration).

  The data processing apparatus according to the present invention is a data processing apparatus comprising an electronic circuit and a data control circuit connected to the electronic circuit, wherein the data control circuit includes data of the electronic circuit. A data saving control unit for saving the data saved outside the circuit, a data restoration control unit for restoring the data saved outside the circuit to the electronic circuit, a restoration monitoring control unit for monitoring a data restoration state in another data processing device, An operation resumption control unit that stops the operation of the electronic circuit until data restoration in all data processing devices is completed (a 22nd configuration).

  In the data processing device having the twenty-second configuration, when the data recovery of the electronic circuit is completed, the data recovery control unit is configured to send a notification signal indicating that (23rd configuration). Good.

  Further, in the data processing device having the above-described twenty-third configuration, the return monitoring control unit monitors all the data by monitoring the notification signals or their logical operation signals respectively transmitted from a plurality of data processing devices. It is preferable to adopt a configuration (24th configuration) for determining whether or not data restoration in the processing device is completed.

  In the data processing device having any one of the twenty-second to twenty-fourth configurations, the operation resumption control unit may be configured to control supply / cutoff of a driving clock to the electronic circuit (25th configuration).

  Further, in the data processing device having any one of the twenty-second to twenty-fifth configurations, the data control circuit includes a state monitoring unit that monitors an operation state of the electronic circuit, and according to the monitoring result, A configuration (a twenty-sixth configuration) for controlling data save / restore of the electronic circuit may be employed.

  In the data processing device having the above-described twenty-sixth configuration, the state monitoring unit indicates that the electronic circuit is in a standby state when a data request signal is sent from the electronic circuit to a peripheral circuit. It may be configured to detect and detect that the electronic circuit should be returned from the standby state when a response signal is sent from the peripheral circuit to the electronic circuit.

  Alternatively, in the data processing device having the twenty-sixth configuration, the state monitoring unit may monitor a processing stop signal of the electronic circuit and determine an operation state of the electronic circuit (a twenty-eighth configuration). Good.

  Alternatively, in the data processing device having the twenty-sixth configuration, the state monitoring unit monitors a dedicated signal indicating a standby state of the electronic circuit and determines an operating state of the electronic circuit (29th configuration) ).

  Alternatively, in the data processing device having the twenty-sixth configuration, the state monitoring unit determines the operation state of the electronic circuit by monitoring data exchanged via the general-purpose data input / output port of the electronic circuit. It is good also as a structure (30th structure) to do.

  With the data processing device according to the present invention, it is possible to appropriately save / restore register data in the electronic circuit unit according to the power on / off without requiring a sub power source or a data backup operation during normal operation. It becomes.

  In addition, the data control circuit according to the present invention makes it possible to use the design assets effectively without making a large-scale change to an existing electronic circuit, thereby reducing the cost of the electronic circuit in a short development period. It is possible to improve performance and reduce power consumption during standby.

  Further, with the data processing device according to the present invention, even if the completion timing of data restoration varies for each of the plurality of data processing devices, the malfunction can be prevented.

  FIG. 1 is a block diagram showing an embodiment of a data processing apparatus according to the present invention.

  As shown in the figure, the data processing apparatus of the present embodiment includes an electronic circuit unit 1, a data save / restore control unit 2, and a nonvolatile memory 3.

  The electronic circuit unit 1 is a CMOS logic circuit (CPU [Central Processing Unit] or the like) that performs data arithmetic processing using a plurality of registers 11 to 13. In the normal operation of the electronic circuit unit 1, 8-bit parallel signals (PI / PO) are input / output via the registers 11 to 13, respectively. Further, the number of registers and the number of input / output bits are not limited to this.

  On the other hand, the electronic circuit unit 1 of the present embodiment includes a flip-flop FF that forms the registers 11 to 13 separately from the normal first signal path (input / output path of the parallel signal PI / PO). A second signal path (serial signal SI / SO input / output path, so-called scan path) is also provided. Since this scan path is a well-known technique widely used for debugging a CMOS logic circuit having a large number of registers, a detailed description of the scan path is omitted, but the electronic circuit unit 1 of the present embodiment is omitted. In this configuration, register data is input / output as a serial signal (SI / SO) by using the above scan path when saving / restoring register data. That is, the arithmetic processing unit 1 according to the present embodiment shifts the flip-flop FF to the shift register based on the normal enable signal NE (enabled during normal operation, disabled during data saving / restoring) input from the data saving / restoring control unit 2. It is configured to control whether to switch to the structure.

  Based on the reset signal RST for detecting power-on / power-off, the data saving / restoring control unit 2 detects a drop in the power supply voltage VDD at the time of power-off, and the power supply voltage VDD is the lower limit for guaranteeing the operation of the device. Data evacuation control for evacuating register data of the electronic circuit unit 1 to the non-volatile memory 3 until reaching a voltage (lower limit value of the power supply voltage VDD that guarantees normal operation of the apparatus, for example, 90% of the normal voltage value) Means, and when the power is turned on, the register data saved in the non-volatile memory 3 is stored in the electronic circuit after the power supply voltage VDD reaches the operation guarantee lower limit voltage until the electronic circuit unit 1 starts operating. Data return control means for returning to the unit 1.

  FIG. 2 is a waveform diagram for explaining a data saving period and a data restoration period.

  As shown in this figure, the data saving period and the data recovery period are both extremely short periods (several hundreds [μs]) immediately after power-off or immediately after power-on. In the data processing apparatus of this embodiment, The saving / restoring of the register data is completed within the period. With such a configuration, the register data of the electronic circuit unit 1 can be appropriately saved / restored in accordance with the power on / off without requiring a sub power source or a data backup operation during normal operation. It is possible to realize a system in which the register data of the electronic circuit unit 1 is substantially non-volatile.

  The data saving / restoring control unit 2 of the present embodiment includes an operation mode control unit 21, a sequence control unit 22, a data scan control unit 23, a serial / parallel conversion unit 24, an address generation unit 25, a read / Write control unit 26.

  The serial / parallel converter 24 includes a SIPO [Serial-In-Parallel-Out] register 24a, a PISO [Parallel-In-Serial-Out] register 24b, and a bidirectional I / O [Input / Output]. And a buffer (3-state I / O buffer) 24c.

  The operation of each part of the data saving / restoring control unit 2 having the above configuration and the saving / restoring operation of register data using this will be described in detail later.

  The nonvolatile memory 3 is a storage means that can retain the stored contents even when the power is shut off. In the data processing device of this embodiment, the register data is stored in a nonvolatile manner by using the hysteresis characteristic of the ferroelectric. FeRAM [Ferroelectric RAM] (256 Kb = 32 Kb × 8) is used.

  Next, the saving operation of the register data in the data processing apparatus having the above configuration will be described in detail with reference to FIG.

  FIG. 3 is a timing chart for explaining the saving operation of the register data.

  When the power is shut down, as shown in FIG. 2 above, when the drop of the power supply voltage VDD is detected and the reset signal RST rises to a high level, the operation mode control unit 21 registers the registers 11 to 13 of the electronic circuit unit 1. In order to switch to the shift register structure, the normal enable signal NE (not shown in FIG. 3) is disabled and the sequence controller 22 is instructed to save data. More specifically, the operation mode control unit 21 inputs an address signal ADDR indicating a register data write destination address to the sequence control unit 22 and instructs a register data write operation to the nonvolatile memory 3. The write signal WRITE to be performed is enabled (high level in this embodiment).

  In the sequence control unit 22 that has received the data save instruction, a write operation flag WRITEST is set to indicate that the register data write operation to the nonvolatile memory 3 is instructed. When the write operation flag WRITEST is set, the address generation unit 25 is in a state of generating a register data write destination address, and the read / write control unit 26 is in a state of performing a write operation to the nonvolatile memory 3. Become.

  In the sequence control unit 22, a sequence control counter COUNT used for timing control of a data read operation from the electronic circuit unit 1 and a data write operation to the nonvolatile memory 3 in synchronization with the positive edge of the clock signal CLK. Is counted up. That is, in the data processing apparatus of the present embodiment, the register data saving operation is controlled as a state machine corresponding to the count value of the sequence control counter COUNT.

  Further, the sequence control unit 22 instructs the data scan control unit 23 to execute data scan (reading of register data) of the registers 11 to 13 by the scan path. Specifically, the sequence control unit 22 enables the data scan control signal SCAN instructing whether or not the data scan control unit 23 can operate (high level in this embodiment). The data scan control signal SCAN is enabled during the period when the sequence control counter COUNT indicates 0 to 7 counts.

  The data scan control unit 23 that has received the instruction to execute the data scan by the scan path hits the scan enable signal SE eight times, and instructs the SIPO register 24a to read the data in the registers 11 to 13 by 8 bits. As a result, data of 8 bits (in this embodiment, one register) is stored in the SIPO register 24a (refer to the SIPO input data REGIN in the figure).

  On the other hand, at the sixth count of the sequence control counter COUNT, the load signal FLOAD is raised, and preparation work for reading out the register data accumulated in the SIPO register 24a is started.

  Thus, after the accumulation of data in the SIPO register 24a is completed, the register data write control to the nonvolatile memory 3 is performed based on the chip enable signal FCE, the output enable signal FOE, and the write enable signal FWE. Migrate to

  The chip enable signal FCE is enabled when the access to the nonvolatile memory 3 is permitted, and disabled when the access to the nonvolatile memory 3 is prohibited. Note that the chip enable signal FCE transitions to enable using a negative edge as a trigger and transitions to disable using a positive edge as a trigger. In the case of FIG. 3, the chip enable signal FCE is raised to a high level at the ninth count of the sequence control counter COUNT, becomes a preparation state for a negative edge (enable transition), and is lowered to a low level at the tenth count. Enabled.

  The output enable signal FOE is enabled when register data is read from the nonvolatile memory 3 and disabled when register data is written to the nonvolatile memory 3. In the case of FIG. 3, the output enable signal FOE is always disabled (low level in this embodiment).

  Contrary to the output enable signal FWE, the write enable signal FWE is disabled when register data is read from the nonvolatile memory 3, and is enabled when register data is written to the nonvolatile memory 3. In the case of FIG. 3, the write enable signal FWE is enabled (high level in this embodiment) during the period when the sequence control counter COUNT indicates 8 to 15 counts.

  The memory input / output signal FIO is an 8-bit parallel signal exchanged between the bidirectional I / O buffer 24c and the nonvolatile memory 3, and triggered by a negative edge (enable transition) of the chip enable signal FCE as a trigger. The accumulated data of the register 24a is taken. In the data processing apparatus of this embodiment, 8-bit register data is transferred in parallel to the nonvolatile memory 3 via the bidirectional I / O buffer 24c at the 10th count of the sequence control counter COUNT.

  Thereafter, the chip enable signal FCE is maintained at a low level by 2 counts of the sequence control counter COUNT, and then is set to a high level. At the 15th count, the chip enable signal FCE is returned to the default low level again. Note that the logic state of the memory input / output signal FIO after the register data write process may be indefinite as shown in FIG.

  Finally, at the 15th count of the sequence control counter COUNT, the access end signal OPEN is raised, and it is recognized that the data saving for one word has been completed.

  As described above, in the data processing device of this embodiment, based on the count value of the sequence control counter COUT, 8-bit register data is transferred from the electronic circuit unit 1 in the first 8 counts (0 to 7 counts). The operation of reading and writing the register data read in the next 8 counts (8 to 15 counts) to the nonvolatile memory 3 is repeated.

  As described above, when data scan of the electronic circuit unit 1 by the scan path is performed, unnecessary data is sequentially overwritten in the registers 11 to 13, but such unnecessary data is lost when the power is turned off. Therefore, no trouble occurs when data is restored.

  Next, the restoring operation of the register data in the data processing apparatus having the above configuration will be described in detail with reference to FIG.

  FIG. 4 is a timing chart for explaining the restoring operation of the register data.

  When the power is turned on, as shown in FIG. 2 above, when the rise of the power supply voltage VDD is detected and the reset signal RST rises to a low level, the operation mode control unit 21 registers the registers 11 to 13 of the electronic circuit unit 1. In order to switch to the shift register structure, the normal enable signal NE (not shown in FIG. 4) is disabled, while the sequence control unit 22 is instructed to restore data. More specifically, the operation mode control unit 21 inputs an address signal ADDR indicating a register data read destination address to the sequence control unit 22 and instructs a register data read operation to the nonvolatile memory 3. The read signal READ to be enabled is enabled (high level in this embodiment).

  In the sequence control unit 22 that has received an instruction to restore data, a read operation flag READST is set to indicate that a register data read operation to the nonvolatile memory 3 is instructed. When the read operation flag READST is set, the address generation unit 25 is in a state of generating a read destination address of the register data, and the read / write control unit 26 is in a state of performing a read operation from the nonvolatile memory 3. Become.

  In the sequence control unit 22, a sequence control counter COUNT used for timing control of a data read operation from the nonvolatile memory 3 and a data write operation to the electronic circuit unit 1 in synchronization with the positive edge of the clock signal CLK. Is counted up. That is, in the data processing apparatus of this embodiment, the return operation of the register data is controlled as a state machine corresponding to the count value of the sequence control counter COUNT.

  When the preparation for reading the register data from the nonvolatile memory 3 is completed, the reading control of the register data to the nonvolatile memory 3 is performed based on the chip enable signal FCE, the output enable signal FOE, and the write enable signal FWE.

  In the case of FIG. 4, the chip enable signal FCE is raised to a high level at the first count of the sequence control counter COUNT, becomes a preparation state for a negative edge (enable transition), and is lowered to a low level at the second count. Enabled. Further, the output enable signal FOE is enabled (high level in this embodiment) during the period when the sequence control counter COUNT indicates 0 to 7 counts. On the other hand, the write enable signal FWE is always disabled (low level in this embodiment). Therefore, in the data processing apparatus of this embodiment, the 8-bit register data is transferred in parallel from the nonvolatile memory 3 via the bidirectional I / O buffer 24c at the second count of the sequence control counter COUNT. Become.

  At the sixth count of the sequence control counter COUNT, the load signal FLOAD is raised, and register data is stored in the PISO register 24b.

  Thereafter, the chip enable signal FCE is kept at the low level for 2 counts of the sequence control counter COUNT, and then is set to the high level. At the seventh count, the chip enable signal FCE is returned to the default low level again. Note that the logic state of the memory input / output signal FIO after the register data read processing may be indefinite as shown in FIG.

  After the accumulation of data in the PISO register 24b is completed in this way, the sequence control unit 22 scans the data scan control unit 23 with the data scan of the registers 11 to 13 by the scan path (the saved register). Data write) is executed. Specifically, the sequence control unit 22 enables the data scan control signal SCAN instructing whether or not the data scan control unit 23 can operate (high level in this embodiment). The data scan control signal SCAN is enabled during a period when the sequence control counter COUNT indicates 8 to 15 counts.

  The data scan control unit 23 that has received an instruction to execute data scan by the scan path hits the scan enable signal SE eight times to instruct the PISO register 24b to output data serially bit by bit. As a result, data of 8 bits (in this embodiment, one register) is restored to the registers 11 to 13 (see PISO output data REGOUT in the figure).

  Finally, at the 15th count of the sequence control counter COUNT, the access end signal OPEN is raised, and it is recognized that the data restoration for one word is completed.

  As described above, in the data processing apparatus of the present embodiment, the register data restoring operation is performed in the reverse procedure of the saving operation described above. That is, based on the count value of the sequence control counter COUT, the register data is read from the nonvolatile memory 3 for 8 bits in the first 8 counts (0 to 7 counts), and the register data is read in the next 8 counts (8 to 15 counts). Is written to the electronic circuit unit 1 repeatedly.

  Next, a device for realizing non-volatility of a large-scale electronic circuit unit will be described in detail with reference to FIGS.

  FIG. 5 is a block diagram showing a schematic configuration of the all wiring lead-out type (a) and the shift register utilization type (b). FIG. 6 is a diagram illustrating the relationship between the number of registers and the wiring length. FIG. 7 is a diagram illustrating data transfer rates of the arithmetic processing unit and the nonvolatile memory.

  As shown in FIG. 5A, register data can be saved at a high speed by adopting a format (all wiring extraction type) in which data saving wiring is drawn out from each of a plurality of registers. However, when this format is adopted, the same number of wirings and output ports as registers are required. Therefore, as shown in FIG. Therefore, it becomes difficult to apply to a large-scale electronic circuit unit.

  On the other hand, as shown in FIG. 5B, if a plurality of registers are serially connected and a data saving wiring is drawn out from the final stage register (shift register utilization type), Since it is only necessary to add a wiring between adjacent registers and a single output port without depending on the number of registers, as shown in FIG. 6B, there is almost no increase in the wiring length even if the number of registers is increased. Application to a large-scale electronic circuit unit becomes easy.

  For example, when registers are arranged at regular intervals in a 1 [mm] square logic block, the wiring length is about 500 [mm] in the all-wire pull-out type, whereas in the shift register utilizing type, The wiring length can be suppressed to 1/10 or less (about 30 [mm]).

  In particular, since a CPU or the like equipped with a scan path function has a serial output port, if this is used, the present invention can be applied without affecting the existing logic.

  In terms of the data transfer rate, the all-wire pull-out type is faster than the shift register utilization type. For example, as shown in FIG. 7, the data transfer speed of the CPU (Z80) driven at 50 [MHz] is about 400 [Mbps] for the all-wire drawer type and about 50 [Mbps] for the shift register utilizing type. .

  However, for example, the data transfer speed required to save all 250 register data used for the CPU (Z80) within the data saving period (several hundred [μs]) shown in FIG. 2 is 1 [Mbps]. Therefore, even when the shift register utilizing type is adopted, a sufficient margin is secured, and no particular problem occurs.

  On the other hand, it is necessary to use a non-volatile memory 3 having a data transfer rate as fast as possible. An EEPROM or the like having only a data transfer rate of about 80 [Kbps] realizes non-volatilization of a large-scale electronic circuit unit. Inappropriate above. Therefore, in the data processing apparatus of the present embodiment, FeRAM having a data transfer rate of 16 [Mbps] is used as the nonvolatile memory 3. With such a configuration, it is possible to save all register data in the electronic circuit section within the data saving period.

  However, even when FeRAM is used as the non-volatile memory 3, the data transfer rate is considerably slower than the data transfer rate of the arithmetic processing unit 1, so that data transfer from the electronic circuit unit 1 to the non-volatile memory 3 is consistently performed. If performed serially, the saving ability of the register data is limited by the data transfer rate of the nonvolatile memory 3.

  Therefore, the data processing apparatus according to the present embodiment converts register data serially input from the electronic circuit unit 1 to parallel conversion and outputs the data to the nonvolatile memory 3 when saving data, while paralleling from the nonvolatile 3 memory when restoring data. A serial / parallel conversion unit 24 that serially converts input register data and outputs the converted data to the electronic circuit unit 1 is provided.

  With such a configuration, a plurality of register data can be read out from the electronic circuit unit 1 during one access to the nonvolatile memory 3, so that the above rate-limiting state can be eliminated. It becomes.

  As described above, the data processing apparatus according to the present embodiment has the register data (data processed by the electronic circuit unit 1) immediately after power-off or within a very short period (several hundred [μs]) immediately after power-on. In the case of a data processing apparatus that does not use a volatile memory as a means for storing data, all the data necessary for returning the state of the electronic circuit unit 1 is saved / restored, so that the register data of the electronic circuit unit 1 is substantially saved. It is configured to be nonvolatile.

  By adopting such a configuration, the loss of register data can be prevented even when a sudden power interruption such as a power failure occurs without requiring a sub power supply or a data backup operation during normal operation. It is possible to suppress damage such as lost work time.

  For example, if the present invention is applied to a network server (network management system), the processing state can be maintained even during a power failure, and the processing can be resumed after the power is restored. You will not receive.

  In the case of a data processing device that requires software control such as a personal computer, the register data of the electronic circuit unit can be restored to the power-off state when the power is turned on. It is possible to greatly shorten the startup time. Therefore, it is possible to provide the user with an environment in which a personal computer can be easily used as if handling household appliances such as a television. Furthermore, with the data processing apparatus of this embodiment, even if the power is turned on / off at intervals as short as a few seconds, the user is not stressed, so the electronic circuit unit is in a state of waiting for processing. It is possible to reduce power consumption by frequently detecting the power and shutting off the power supply.

  For example, when the present invention is applied to a desktop personal computer or a stationary game machine, it is possible to instantly start up and start up the power, and there is no need to save or start up data, thereby providing a stress-free IT environment. It becomes possible.

  Further, if the present invention is applied to a notebook computer or a mobile device, battery backup becomes unnecessary, and even if there is no remaining battery power, it is possible to hold data without any problem for several months.

  The configuration of the present invention can be variously modified in addition to the above-described embodiment without departing from the gist of the invention.

  For example, in the above embodiment, the configuration using FeRAM as the nonvolatile memory 3 has been described as an example. However, the configuration of the present invention is not limited to this, and the nonvolatile memory 3 may be a magnetic material. An MRAM [Magnetroresistive RAM] that stores register data in a nonvolatile manner using the magnetoresistive effect or a PRAM [Phase change RAM] that stores register data in a nonvolatile manner using the phase change of the element may be used. I do not care.

  The MRAM has a higher data transfer rate than FeRAM (about 8 times), but consumes more power than FeRAM and the power supply voltage VDD decreases more quickly. Therefore, when the MRAM is used as the nonvolatile memory 3, the MRAM is used. Note that the time available for saving data is reduced.

  On the other hand, the PRAM has a data transfer rate comparable to or slightly slower than the FeRAM, but the limit of the number of data rewrites is stricter than that of the FeRAM. Note that is shortened.

  Next, as an application example of the present invention described above, a data control circuit having a register data saving / restoring control function separately from existing electronic circuits (IC, LSI, IP core, etc. that have been marketed) With reference to FIG. 8, a detailed description will be given of a technology for constructing a system that can improve the convenience of electronic circuits and reduce power consumption during standby easily and at low cost.

  FIG. 8 is a block diagram showing an example of a system configuration equipped with a data control circuit according to the present invention. 8A shows an example of the SoC [System-on-Chip] configuration, and FIG. 8B shows an example of the on-board system configuration.

  In the data processing apparatus having the SoC configuration shown in FIG. 8A, the system LSI (SoC) 100 includes an electronic circuit 100a (such as a CPU core), a data control circuit 100b, and an embedded memory 100c in the same chip. It is integrated.

  The electronic circuit 100a corresponds to the electronic circuit unit 1 in FIG. 1, and includes a register data input port and a register data output port (debug port such as a scan path) for accessing a register inside the circuit from the outside of the circuit. Be prepared.

  The data control circuit 100b corresponds to the data save / restore control unit 2 in FIG. 1, and the data save control for saving the register data of the electronic circuit 100a to the outside of the circuit via the register data output port of the electronic circuit 100a. It is equipped with functions. The data control circuit 100b includes a data return control function for returning register data saved outside the electronic circuit 100a to a register in the circuit via the register data input port of the electronic circuit 100a.

  The embedded memory 100c corresponds to the nonvolatile memory 3 of FIG. 1, and is a storage circuit that serves as a save destination for register data read from the electronic circuit 100a.

  In FIG. 8A, the symbol X1 indicates a serial signal (corresponding to the serial signal SI in FIG. 1) given from the data control circuit 100b to the register of the electronic circuit 100a via the register data input port. Reference numeral X2 represents a serial signal (corresponding to the serial signal SO in FIG. 1) read from the register of the electronic circuit 100a to the data control circuit 100b via the register data output port. Reference numeral X3 indicates an input / output path (a debug line such as a scan path) for a serial signal in the electronic circuit 100a. The scan path may be formed as an option when the CMOS core circuit is synthesized. Reference numeral X4 indicates a scan path enable signal (corresponding to the scan path enable signal SE in FIG. 1). Reference numeral X5 represents an internal memory bus for inputting / outputting register data between the data control circuit 100b and the embedded memory 100c. Reference numeral X6 indicates an external bus for inputting / outputting register data between the data control circuit 100b and another LSI or an external memory. Symbol X7 indicates a data control signal (trigger signal for controlling saving / restoring of register data) input from a power supply control circuit or the like.

  On the other hand, in the data processing apparatus having the on-board system configuration shown in FIG. 8B, the electronic circuit 110 (CPU and the like), the data control circuit 120, and the memory 130 are each integrated in a separate chip. It is individually mounted on the motherboard.

  The electronic circuit 110 corresponds to the electronic circuit unit 1 of FIG. 1, and includes a register data input port and a register data output port for accessing a register inside the circuit from the outside of the circuit.

  The data control circuit 120 corresponds to the data saving / restoring control unit 2 in FIG. 1, and the data saving control for saving the register data of the electronic circuit 110 to the outside of the circuit via the register data output port of the electronic circuit 110. It is equipped with functions. Further, the data control circuit 120 includes a data return control function for returning the register data saved outside the electronic circuit 110 to a register inside the circuit via the register data input port of the electronic circuit 110.

  The memory 130 corresponds to the non-volatile memory 3 in FIG. 1 and is a storage circuit that serves as a save destination for register data read from the electronic circuit 110.

  In FIG. 8B, the symbol Y1 indicates a serial signal (corresponding to the serial signal SI in FIG. 1) given from the data control circuit 120 to the register of the electronic circuit 110 via the register data input port. A symbol Y2 indicates a serial signal (corresponding to the serial signal SO in FIG. 1) read from the register of the electronic circuit 110 to the data control circuit 120 via the register data output port. Reference symbol Y3 indicates a serial signal input / output path (scan path, debug line such as JTAG) in the electronic circuit 110. Symbol Y4 indicates a scan path enable signal and a JTAG control signal (corresponding to the scan path enable signal SE in FIG. 1). Reference numeral Y <b> 5 indicates a memory bus for inputting / outputting register data between the data control circuit 120 and the memory 130. A symbol Y6 indicates a data bus for inputting / outputting register data between the data control circuit 120 and another LSI. Symbol Y7 indicates a data control signal (a trigger signal for controlling saving / restoring of register data) input from a power supply control circuit or the like.

  As described above, in addition to the existing electronic circuits 100a and 110 (IC, LSI, IP core, etc. that have been put on the market), the data control circuits 100b and 120 having a register data saving / restoring control function are mounted. By making effective use of design assets without making any changes to the electronic circuits 100a and 110, the convenience of the electronic circuits 100a and 110 can be improved and the power consumption during standby can be reduced at a low cost in a short development period. Can be realized.

  Next, an application example relating to data retention at power-on / off will be described in detail with reference to FIGS.

  FIG. 9 is a block diagram showing an example of a configuration for realizing data holding at power-on / off, and FIG. 10 is a time chart showing an example of data holding operation.

  The data control circuit 120 monitors power on / off for the electronic circuit 110 (in the example of FIG. 9, a power control signal input from the outside via the power control circuit 140), and when the power off is instructed, The register data of the electronic circuit 110 is saved, and when the power-on is instructed, the register data is restored to the register of the electronic circuit 110 to return the electronic circuit 110 to the original state.

  Therefore, when power off is instructed during normal operation, first, the register data of the electronic circuit 110 is saved in the memory 130 and then the power is shut off. Then, when power on is instructed, After the register data saved in the memory 130 is restored to the electronic circuit 110, the electronic circuit 110 starts normal operation (see FIG. 10).

  By adopting such a configuration, it is possible to avoid the loss of register data due to power shutdown, so that the electronic circuit 110 can be restored to the state before power shutdown without delay immediately after the power is turned on again. It is possible to shorten the hardware startup time associated with software reloading. Therefore, it is possible to provide the user with an environment in which a personal computer can be easily used as if handling household appliances such as a television.

  As described above, the register data of the electronic circuit 110 is saved in the memory 130 by utilizing the discharge time of the power supply voltage after the power supply voltage drop is detected and before the operation guarantee lower limit voltage is reached. With this configuration, a sub power source (UPS, battery backup, etc.) at the time of data saving becomes unnecessary, and it is possible to cope with an unexpected power failure. Further, unlike the configuration in which register data backup processing is performed during normal operation, the processing speed of the electronic circuit 110 is not affected.

  Next, an application example relating to low power consumption by shutting off standby power will be described in detail.

  FIG. 11 is a block diagram illustrating a configuration example for realizing low power consumption by shutting off the standby power source.

  As shown in FIGS. 11A and 11B, the data control circuit 120 of this configuration example monitors the operation state of the electronic circuit 110 and the power supply control unit 120a that controls power on / off of the electronic circuit 110. And when the electronic circuit 110 is in a standby state, the register data is saved and the power to the electronic circuit 110 is shut off. When the electronic circuit 110 is to be returned from the standby state, the electronic circuit 110 is configured to turn on power and restore register data.

  By adopting such a configuration, it is possible to automatically control power on / off according to the operation status while retaining the register data of the electronic circuit 110. It becomes possible to suppress electric power.

  FIG. 12 is a block diagram illustrating a configuration example for detecting an operation state of the electronic circuit 110 by the state monitoring unit 120b.

  As shown in FIGS. 12A and 12B, in the data control circuit 120 of this configuration example, the state monitoring unit 120b monitors input / output signals exchanged between the electronic circuit 110 and the peripheral circuit 150. Thus, the operation state of the electronic circuit 110 is determined.

  More specifically, the state monitoring unit 120b indicates that when the data request signal is transmitted from the electronic circuit 110 to the peripheral circuit 150, the electronic circuit 110 is in a standby state (waiting for external information from the peripheral circuit 150). On the other hand, when a response signal (data signal) is sent from the peripheral circuit 150 to the electronic circuit 110, it is detected that the electronic circuit 110 should be returned from the standby state. Yes.

  With this configuration, even during high-speed data transfer, if the standby time of the electronic circuit 110 is several milliseconds, the register data can be saved and the power supply can be shut off. Can be turned on / off to reduce power consumption.

  FIG. 13 is a diagram for explaining the effect of suppressing leakage power according to the present invention. In addition, this figure (a) has shown the power consumption behavior of this invention, and this figure (b) has shown the power consumption behavior of the conventional structure. Moreover, the vertical axis | shaft of this figure (a), (b) has shown all power consumption, and the horizontal axis has shown time all.

  As shown in FIG. 13B, in the conventional configuration, leakage power is consumed not only during operation but also during standby (see the hatched portion in the figure). On the other hand, according to the configuration of the present invention, the register data can be saved and the power supply can be cut off during standby, so that power consumption can be reduced.

  In particular, the ratio of leakage power to the total power consumption tends to increase as the device technology nodes (semiconductor process basic rules defined in ITRS [International Technology Roadmap for Semiconductors]) become smaller. It can be said that the reduction of the leakage power is very important in reducing the size of the device.

  FIG. 14 is a diagram for explaining the power consumption reduction effect of the entire device according to the present invention. In addition, the vertical axis | shaft of this figure has shown the power consumption (standardization) of a device, and the horizontal axis has shown the operation rate (%) of the device. Further, this figure shows a case where the ratio of the leak power occupying the total power consumption is 30%.

  As is clear from comparison between the solid line L1 (present invention: normally off) and the broken line L2 (conventional configuration: always on), the lower the operation rate, the greater the effect of suppressing leakage power during standby, and the operation rate. In the case of 20%, the total power consumption can be reduced by about 50%.

  Next, an application example relating to processing switching by replacement of register data will be described in detail.

  FIG. 15 is a block diagram illustrating a configuration example for realizing process switching by exchanging register data.

  As shown in the figure, the data control circuit 120 of this configuration example is configured to replace register data in accordance with processing executed by the electronic circuit 110. More specifically, when the processing executed in the electronic circuit 110 is switched from A to B, the register data (processing A data) stored in the electronic circuit 110 executing the processing A is used as the electronic circuit 110. Is temporarily saved in the memory 130, while the register data (processing B data) saved in the memory 130 when the process B is executed is returned to the electronic circuit 110, and the register data of the electronic circuit 110 is restored. By replacing all of the above, the processing to be executed is switched without initializing the electronic circuit 110. Further, when the processing executed in the electronic circuit 110 is switched from B to A, it can be realized by the operation reverse to the above.

  By adopting such a configuration, even if it is necessary to interrupt a process in the middle and restart another process in the middle, the operation can be switched only by hardware, so switching is faster than software. Can be realized.

  Note that the data control circuit 120 of the above configuration example may be configured to simultaneously execute a data saving operation and a data restoring operation when register data is exchanged, as shown in FIG. More specifically, when the process executed in the electronic circuit 110 is switched from A to B, the register data saved in the first memory 130a when the process B is executed (process B data) ) Is serially input to the electronic circuit 110 bit by bit, and the register data (processing A data) in the electronic circuit 110 that is output bit by bit in response to the restoration of the processing B data is stored in the second memory 130b. By saving, all register data of the electronic circuit 110 is replaced. In FIG. 16, the return data is represented by a gray box and a solid line arrow, and the saved data is represented by a white box and a broken line arrow.

  By adopting such a configuration, it is possible to quickly complete the register data replacement operation and, in turn, the process switching operation.

  The first and second memories 130a and 130b may be separate chips, or the dual port memory storage area may be divided and used as the first and second memory areas 130a and 130b.

  Next, the memory used and the data transfer amount will be described in detail with reference to FIG.

  FIG. 17 is a diagram showing the relationship between the used memory and the data transfer amount. In this figure, the vertical axis represents the saved data amount, and the horizontal axis represents the data transfer rate at the time of data writing.

  For example, if a save time of 10 [ms] or more can be secured in order to save several hundred [bit] register data (such as Z80 system register data), an EEPROM is used as a data save destination memory. However, when it is necessary to save several [Kbit] of register data (such as ARM7 system register data) in a shorter time (about 1 [ms]), a storage circuit (flash memory) faster than the EEPROM can be used. Or FeRAM) must be used.

  That is, in the data processing apparatus according to the present invention, the data transfer rate that can save all the register data from the electronic circuit is considered as the save destination of the register data in consideration of the relationship between the save data amount and the save time. Equipped with suitable storage circuits (SRAM, DRAM, EEPROM, flash memory, FeRAM, MRAM, PRAM, RRAM, NVSRAM, BBSRAM, and similar memories, or latches, registers, and similar storage elements) Use it.

  Next, an application example in which not only register data of an electronic circuit but also data saving / recovery of a volatile memory storing data processed by the electronic circuit is realized by hardware will be described in detail with reference to FIG. To do.

  FIG. 18 is a block diagram illustrating a configuration example for realizing, in hardware, data saving / restoring of a volatile memory that stores data processed by an electronic circuit. In the figure, solid line arrows indicate data save / return paths, and broken line arrows indicate control signal transmission paths.

  As shown in FIG. 18, the data processing device of this configuration example includes an electronic circuit 210 such as a large-scale CPU, a data control circuit 220, and a nonvolatile memory 230. Note that the electronic circuit 210, the data control circuit 220, and the nonvolatile memory 230 described above are all connected to the data bus 240.

  The electronic circuit 210 corresponds to the electronic circuit 110 in FIG. 8B (or the electronic circuit 100 in FIG. 8A excluding the data control circuit 100b), and in addition to the CPU core 210a, It comprises a mixed memory 210b, a cache memory 210c, a debug line control circuit 210d, and a DMA [Direct Memory Access] controller 210e.

  Each of the CPU core 210a, the embedded memory 210b, and the cache memory 210c has a data input port and a data output port (a debugging port such as a scan path or JTAG) for accessing a storage element inside the circuit from the outside of the circuit. Be prepared. Such a debugging port may be provided as an option when performing circuit synthesis.

  The embedded memory 210 b and the cache memory 210 c are volatile memories that store data processed by the electronic circuit 210. In the example of FIG. 18, description is given by taking as an example a configuration in which both the embedded memory 210b and the cache memory 210c are built in the electronic circuit 210, but the configuration of the present invention is not limited to this. , Each may be externally attached.

  The debug line control circuit 210d performs data save / restore control via the debug port and data transfer via the data bus 240 between the CPU core 210a, the embedded memory 210b and the cache memory 210c, and the data control circuit 220. In addition to performing save / restore control, it is a means that serves as an input / output path for save data / restore data via the debug port.

  The DMA controller 210e is means for performing DMA transfer control of the embedded memory 210b based on an instruction from the data control circuit 220. The DMA controller 210e may be built in the data control circuit 220.

  The data control circuit 220 corresponds to the data control circuit 120 of FIG. 8B, and stores not only register data of the CPU core 210a constituting the electronic circuit 210 but also data processed by the electronic circuit 210. Functions for realizing data evacuation / recovery of data in the volatile memory (in FIG. 18, the embedded memory 210b and the cache memory 210c) by hardware (in FIG. 18, the CPU core 210a, the embedded memory 210b, the cache memory via the debug port) 210c and a DMA transfer instruction function of the embedded memory 210b for the DMA controller 210e). Note that the data control circuit 220 can be incorporated in the electronic circuit 210 as in FIG.

  The non-volatile memory 230 corresponds to the memory 130 in FIG. 8B, and a storage circuit serving as a save destination for various data (register data, memory data, and cache data) read from the electronic circuit 210. It is. Note that the nonvolatile memory 230 can also be incorporated in the electronic circuit 210 as in FIG.

  As described above, the nonvolatile memory 230 includes SRAM, DRAM, EEPROM, flash memory, FeRAM, MRAM, PRAM, RRAM, NVSRAM, BBSRAM, and similar memories, or latches and registers. And a similar memory element may be used.

  In addition, a configuration may be adopted in which a nonvolatile memory serving as a data saving destination via the debug line and a nonvolatile memory serving as a data saving destination via the data bus 240 are individually provided.

  The data saving process of the data processing apparatus having the above configuration will be described with reference to FIG. 19 together with FIG.

  FIG. 19 is a flowchart illustrating an example of the data saving process. In FIG. 19, the case where the data saving process of the electronic circuit 210 is performed by using an instruction to turn off the power as an example will be described as an example. However, the application target of the present invention is not limited to this. In addition, as described above, it is naturally possible to perform the data saving process of the electronic circuit 210 triggered by the detection of the standby state of the electronic circuit 210 or the detection of the process switching. .

  First, when a signal for instructing power off is detected in step S10, an interrupt process is performed from the data control circuit 220 to the electronic circuit 210 in step S11, and a process being executed in the electronic circuit 210 is interrupted. The Thereafter, in steps S12 and S13, the data control circuit 220 saves data in the cache memory 210c and saves data in the embedded memory 210b via the debug line or the data bus 240. In step S14, the drive clock of the electronic circuit 210 is cut off by the data control circuit 220. After the operation of the CPU core 210a is stopped, the register data is saved via the debug line in step S15. Then, after the saving of all data is completed, the power source of the electronic circuit 210 is turned off in step S16.

  In addition, regarding the data saving of the cache memory 210c in step S12 and the data saving of the embedded memory 210b in step S13, the cache memory 210c and the embedded memory 210b are connected via the debug line as in the case of saving the register data of the CPU core 210a. And the data may be saved via the debug line or the data bus 240. When data is saved via the debug line, the data saving path from the data control circuit 220 to the nonvolatile memory 230 may be a path via the data bus 240 or may be saved to the nonvolatile memory 230. A route for directly writing data may be used.

  In addition to the above-described method, the data control circuit 220 controls the DMA controller 210e mounted on the electronic circuit 210 to save the data in the embedded memory 210b in step S13. It is also possible to DMA transfer the stored data to the nonvolatile memory 230.

  In addition to the CPU core 210a and the DMA controller 210e, if there is a control subject (for example, a memory controller) of the embedded memory 210b, the stored data in the embedded memory 210b is controlled via the data bus 240 by controlling this. Can be transferred to the nonvolatile memory 230.

  As described above, with the configuration shown in FIG. 18, not only the register data of the CPU core 210a that constitutes the electronic circuit 210 but also the volatile memory that stores data processed by the electronic circuit 210 (in FIG. Data save / restore of the memory 210b and the cache memory 210c) can also be realized by hardware. Therefore, the data save program is executed by the CPU core 210a and data save control is performed by software processing. Can be saved / restored (and thus turned on / off) at high speed.

  In the above data saving control, the data stored in the embedded memory 210b is indispensable for returning the state of the electronic circuit 210, and therefore cannot be discarded without saving, but the data stored in the cache memory 210c is Even if there is no cache data after the electronic circuit 210 returns to the state, it is sufficient to read the stored data in the embedded memory 210b again. For this reason, the data stored in the cache memory 210c may be discarded without being saved.

  However, if the data is saved in the electronic circuit 210 at the timing when the CPU core 210a uses the cache data, if the cache data is discarded when the electronic circuit 210 is restored, the CPU core 210a uses the cache data. Since the cache data inside seems to have suddenly disappeared, there is a possibility that the operation may be hindered. Therefore, when the above configuration for discarding the cache data is adopted, the machine cycle of the electronic circuit 210 is monitored, and the data of the electronic circuit 210 is saved in anticipation of the cache data not being used by the CPU core 210a. It is desirable to have a configuration.

  Also, in FIG. 19, the description has been given by exemplifying the configuration in which the register data saving of the CPU core 210a, the data saving of the embedded memory 210b, and the data saving of the cache memory 210c are processed in series. However, the data stored in the embedded memory 210b is saved by DMA transfer via the data bus 240, and the register data of the CPU core 210a is saved via a debug line, for example. The stored data may be processed in parallel such that the stored data is discarded. By adopting such a configuration, it is possible to execute data save / restore (and thus power on / off) at a higher speed.

  Further, when the debug line control circuit 210d and the DMA controller 210e are not provided and the data save control by software processing must be performed using the CPU core 210a, the description will be given with reference to FIG. It is only necessary to quickly shift to the data saving program through the register data replacement process and save the data stored in the embedded memory 210b and the cache memory 210c to the nonvolatile memory 240 via the data bus 240.

  Next, the data restoration process of the data processing apparatus having the above configuration will be described with reference to FIG. 20 together with FIG.

  FIG. 20 is a flowchart illustrating an example of the data restoration process. 20A and 20B includes steps for causing the electronic circuit 210 to execute specific processing (such as wait processing and user notification processing) when the electronic circuit 210 restores data. It is.

  First, the flowchart of FIG. 20A (a method for realizing the specific processing by interrupt control by the data control circuit 220) will be described.

  When the power is turned on in step S20, the data saved in the nonvolatile memory 230 is returned to the electronic circuit 210 in the subsequent step S21. Of the data recovery in step S21, regarding the data recovery of the embedded memory 210b and the cache memory 210c, the embedded memory 210b and the cache memory 210c are controlled via the debug line as in the case of recovering the register data of the CPU core 210a. Then, the data may be restored via the debug line or the data bus 240. Note that when data is saved via the debug line, the data return path from the nonvolatile memory 230 to the data control circuit 220 may be the path via the data bus 240 or may be recovered from the nonvolatile memory 230. A route for directly reading data may be used.

  In addition to the above-described method, the data control circuit 220 controls the DMA controller 210e mounted on the electronic circuit 210 and restores the nonvolatile memory via the data bus 240 with respect to the data restoration of the embedded memory 210b in step S21. It is also possible to DMA transfer the saved data 230 to the embedded memory 210b.

  In addition to the CPU core 210a and the DMA controller 210e, if there is a control subject (for example, a memory controller) of the embedded memory 210b, the nonvolatile memory 230 can be saved via the data bus 240 by controlling this. It is also possible to transfer data to the embedded memory 210b.

  When the restoration of data in step S21 is completed, in step S22, the data control circuit 220 supplies the drive clock for the electronic circuit 210 and activates the CPU core 210a.

  In step S23, a predetermined interrupt process is performed from the data control circuit 220 as a process for notifying the electronic circuit 210 that the data has been saved / restored. In the subsequent step S24, the specific process is performed. A program prepared in advance for realization (hereinafter referred to as a specific program) is executed.

  When the specific process in step S24 is completed, in step S25, the normal operation of the electronic circuit 210 (the operation performed before data saving) is resumed.

  Next, the flowchart of FIG. 20B (a method for realizing the specific processing by the data replacement processing by the data control circuit 220) will be described.

  When the power is turned on in step S30, in the subsequent step S31, the aforementioned specific program is input to the electronic circuit 210 instead of the saved data in the nonvolatile memory 230.

  When the input of the specific program in step S31 is completed, in step S32, the drive clock of the electronic circuit 210 is supplied by the data control circuit 220, and the CPU core 210a is activated. In step S33, the specific program is executed.

  Thereafter, when the specific processing in step S33 is completed, in step S34, the saved data in the nonvolatile memory 230 is restored to the electronic circuit 210 by applying the register data replacement processing described above with reference to FIG.

  In step S35, the normal operation of the electronic circuit 210 (the operation performed before saving data) is resumed.

  As described above, when the data saved in the nonvolatile memory 230 is restored, a specific process different from this is executed before the electronic circuit 210 resumes the process performed before the data is saved. In such a configuration, prior to resuming the normal operation of the electronic circuit 210, the user is notified that the data has been saved / restored, and a message prompting the user to prepare for the resumption of the normal operation is displayed. Since it is possible to select whether to maintain or discard the processing contents, it is possible to improve convenience.

  In other words, since the drive clock is cut off during the data saving / restoring, the electronic circuit 210 cannot determine whether or not the data saving / restoring has been performed by itself. The operation before the data saving is attempted to be resumed as if there was not, but prior to the resumption of the operation, for example, a power outage of an application (for example, a game machine) that constantly requests a user operation by performing the specific processing described above. Even if data is saved at times, a message that prompts the user to prepare for resumption of normal operation can be issued after the data is restored, so the operation before the data saving is suddenly resumed, It becomes possible to prevent the user from dealing with it.

  In FIGS. 20A and 20B, as a method for realizing the above-described specific processing, the flow for performing interrupt control and the flow for performing data replacement processing are separately depicted and described. As for this flow, only one of the flows may be implemented, or both flows may be used in combination.

  For example, the flow for interrupt control shown in FIG. 20A is easy to deal with a large-capacity program, but is software processing using the CPU core 210a, which is disadvantageous in terms of processing speed. On the other hand, the flow for performing the data exchange process in FIG. 20B can execute the specific program quickly by hardware processing, but it is difficult to cope with a large-capacity program. Therefore, when both flows are used in combination, either one of the flows may be selectively used according to the contents of the specific program (processing weight).

  As means for notifying the electronic circuit 210 of data save / restore, in addition to the above-described interrupt control, predetermined notification data for notifying data save / restore is sent via the data bus 240, and the electronic circuit 210 A configuration in which the specific program described above is executed when the notification data is detected is conceivable. However, when adopting this configuration, a program for constantly monitoring the data bus 240 by the CPU core 210a is required.

  In addition, the above configuration is a configuration that assumes a case where data restoration is performed after the power is shut off for a relatively long period of time, such as in the event of a sudden power failure, but the power is shut off when the electronic circuit 210 is on standby. In the case where data is saved / restored frequently in a short period of time, the normal operation may be resumed without delay without executing the specific program.

  Next, an application example relating to simultaneous restoration of a plurality of existing data processing apparatuses will be described in detail with reference to FIGS. 21 and 22.

  FIG. 21 is a block diagram illustrating a configuration example for realizing simultaneous return of a plurality of existing data processing apparatuses. In FIG. 21, description will be made by taking a system including three data processing devices 200A, 200B, and 200C as an example, but the number of data processing devices is not limited to this.

  As shown in FIG. 21, the data processing device 200A includes an electronic circuit 210A, a data control circuit 220A, and a nonvolatile memory 230A. The data processing device 200B includes an electronic circuit 210B, a data control circuit 220B, and a nonvolatile memory 230B. The data processing device 200C includes an electronic circuit 210C, a data control circuit 220C, and a nonvolatile memory 230C.

  The electronic circuits 210A, 210B, and 210C correspond to the electronic circuit 210 in FIG. 18, and the data control circuits 220A, 220B, and 220C correspond to the data control circuit 220 in FIG. The memories 230A, 230B, and 230C correspond to the nonvolatile memory 230 in FIG.

  FIG. 22 is a block diagram showing an internal configuration of the data control circuit 220A. The data control circuits 220B and 220C have the same configuration.

  As shown in FIG. 22, the data control circuit 220A includes a data saving control unit A1 that saves the data of the electronic circuit 210A in the nonvolatile memory 230A, and the data saved in the nonvolatile memory 230A is returned to the electronic circuit 210A. When the data recovery of the electronic circuit 210A is completed, the data recovery control unit A2 that sends a data recovery completion notification signal SA indicating that and the data recovery state in the other data processing devices 200B and 200C (FIGS. 21 and In the configuration example 22, the operation of the electronic circuit 210A is stopped until the data recovery in the recovery monitoring control unit A3 that monitors the data recovery completion detection signal SD) and the data processing devices 200A, 200B, and 200C is completed. And an operation resumption control unit A4. The data control circuits 220B and 220C have the same configuration.

  That is, the data control circuits 220A, 220B, and 220C, in addition to the data saving / restoring function described above, respectively, send functions for sending the data restoration completion notification signals SA, SB, SC, and simultaneous restoration according to the data restoration completion detection signal SD, respectively. And features.

  Note that the data recovery completion notification signals SA, SB, and SC are binary logic signals that are at a low level during data recovery and are at a high level after completion of data recovery, for example, in the configuration example of FIG. Are input to the logical product calculator 250.

  The data restoration completion detection signal SD is an output signal of the AND operator 250 (an AND operation signal of the data restoration completion notification signals SA, SB, SC), and any of the data restoration completion notification signals SA, SB, SC is used. Is at the high level only (when the data recovery of the data processing devices 200A, 200B, and 200C has been completed), and is at the low level otherwise.

  In this manner, the logical product calculator 250 is provided separately from the data processing devices 200A, 200B, and 200C as means for generating the data recovery completion detection signal SD from the data recovery completion notification signals SA, SB, and SC. Thus, it is possible to easily cope with the addition of data processing devices. However, the configuration of the present invention is not limited to this. For example, the data control completion signals SA, SB, SC may be directly monitored between the data control circuits 220A, 220B, 220C. . Alternatively, another logical operation circuit (such as a majority operation unit) may be used instead of the logical product operation unit 250 as long as it does not interfere with the resumption of operation of the data processing devices 200A, 200B, and 200C.

  As described above, the data control circuits 220A, 220B, and 220C include the return monitoring control unit A3 and the operation resumption control unit A4, and the data recovery is performed after the completion of the respective data recovery processes. The drive clocks of the electronic circuits 210A, 210B, and 210C are stopped until the completion detection signal SD becomes high level, and when the data return completion detection signal SD becomes high level, supply of the drive clock is resumed. It is configured.

  As described above, the data control circuits 220A, 220B, and 220C are each provided with a function of monitoring the data restoration status of each other, and when the data restoration of all the data processing devices 200A, 200B, and 200C is completed, By adopting a configuration in which the operation is resumed, even if the data restoration completion timing varies for each of the data processing devices 200A, 200B, and 200C, it is possible to match the respective operation resumption timings.

  In other words, with the above configuration, the data processing device that has completed the data restoration first does not resume operation while the other data processing devices are restoring data (stopping processing), thus preventing malfunction. It becomes possible to do.

  In the case of realizing low power consumption by shutting off the power supply during standby of the electronic circuits 210A, 210B, 210C, in the data control circuits 220A, 220B, 220C, the operation state of the electronic circuits 210A, 210B, 210C (standby state) As the detection means, the electronic circuit 210A, 210B, 210C is changed from the electronic circuit 210A, 210B, 210C to the peripheral circuit (not shown in FIG. 21) as the detecting means. On the other hand, when a data request signal is sent, it is detected that the electronic circuits 210A, 210B, 210C are in a standby state, and when a response signal is sent from the peripheral circuit, the electronic circuits 210A, 210B, 210C. It is only necessary to provide a state monitoring unit that detects whether to return from the standby state.

  As described above, if the standby state is detected by monitoring the existing signal terminals of the electronic circuits 210A, 210B, and 210C, the design assets can be changed without making any changes to the electronic circuits 210A, 210B, and 210C. Therefore, it is possible to improve the convenience of the electronic circuits 210A, 210B, and 210C and reduce the power consumption during standby in a short development period and at a low cost.

  However, the means for detecting the operation state (whether or not the electronic circuit 210A, 210B, 210C is in the standby state) is not limited to the above, and any configuration may be used.

  For example, when the electronic circuits 210A, 210B, and 210C have an output terminal of a processing stop signal (for example, a HALT signal that is flagged when the processing is forcibly stopped due to some trouble such as when the CPU is hung up). For example, the signal terminal may be monitored.

  Further, if the electronic circuits 210A, 210B, and 210C have dedicated signal terminals indicating the respective standby states, the signal terminals may be monitored.

  Alternatively, if the electronic circuits 210A, 210B, and 210C have a function of sending data indicating that each is in a standby state via a general-purpose data input / output port (data bus 240 in FIG. 21), A configuration for monitoring data may be used.

  The present invention improves the convenience of a microprocessor, an image processor, a multimedia processor, an IP core, a personal computer, a network server, a mobile device, a game machine, a PDA, etc. (data protection and battery switching speed when the battery is exhausted) ) And power consumption reduction during standby (extension of driving time and battery life in battery devices).

These are block diagrams which show one Embodiment of the data processor which concerns on this invention. FIG. 4 is a waveform diagram for explaining a data saving period and a data restoration period. These are timing charts for explaining the data saving operation. These are timing charts for explaining the data recovery operation. These are block diagrams which show schematic structure of all wiring drawer | drawing-out type (a) and shift register utilization type | mold (b). These are figures which show the relationship between the number of registers and wiring length. These are figures which show the data transfer speed of an arithmetic processing part and a non-volatile memory. These are block diagrams which show an example of the system configuration | structure which mounts the data control circuit which concerns on this invention. These are block diagrams which show the example of 1 structure for implement | achieving data retention at the time of power activation / shutdown. These are time charts showing an example of the data holding operation. These are block diagrams which show the example of 1 structure for implement | achieving the reduction in power consumption by power supply interruption at the time of standby. These are block diagrams which show the example of 1 structure for detecting the operation state of the electronic circuit 110 by the state monitoring part 120b. These are the figures for demonstrating the suppression effect of the leak electric power by this invention. These are the figures for demonstrating the power consumption reduction effect of the whole device by this invention. These are block diagrams which show the example of 1 structure for implement | achieving process switching by replacement of register data. FIG. 5 is a block diagram showing an example of a configuration for realizing simultaneous execution of data save / restore. These are the figures which showed the relationship between used memory and data transfer amount. These are block diagrams which show the example of 1 structure for implement | achieving data backup / data restoration of the volatile memory which stores the data processed with an electronic circuit. FIG. 10 is a flowchart illustrating an example of a data saving process. These are flowcharts showing an example of data restoration processing. These are block diagrams which show the example of 1 structure for implement | achieving the simultaneous return of multiple data processing apparatuses. These are block diagrams showing the internal configuration of the data control circuit 220A.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Electronic circuit part 2 Data saving / restoration control part 3 Nonvolatile memory (FeRAM)
11, 12, 13 Register 21 Operation mode control unit 22 Sequence control unit 23 Data scan control unit 24 Serial / parallel conversion unit 24a SIPO register 24b PISO register 24c Bidirectional I / O buffer 25 Address generation unit 26 Read / write control unit 100 System LSI (SoC)
100a Electronic circuit (CPU core, etc.)
100b Data control circuit 100c Embedded memory 110 Electronic circuit (CPU, etc.)
120 Data Control Circuit 120a Power Supply Control Unit 120b Status Monitoring Unit 130 Memory 130a First Memory (First Storage Area)
130b Second memory (second storage area)
140 Power supply control circuit 150 Peripheral circuit 200A, 200B, 200C Data processing device 210, 210A, 210B, 210C Electronic circuit (CPU, etc.)
210a CPU core 210b Mixed memory (volatile)
210c Cache memory (volatile)
210d Debug line control circuit 210e DMA controller 220, 220A, 220B, 220C Data control circuit 230, 230A, 230B, 230C Non-volatile memory 240 Data bus 250 AND operation unit A1 Data save control unit A2 Data return control unit A3 Return monitoring control Part A4 Operation resumption control part

Claims (30)

  Data that saves all the data necessary to restore the state of the electronic circuit section to the non-volatile memory after the power supply voltage drop is detected when the power is shut off until the power supply voltage reaches the operation guarantee lower limit voltage of the device A data processing apparatus comprising a retreat control means.   When the power is turned on, the data saved in the non-volatile memory is restored to the electronic circuit unit after the power supply voltage reaches the operation guarantee lower limit voltage until the electronic circuit unit starts operating. The data processing apparatus according to claim 1, further comprising a data restoration control unit.   The data processing apparatus according to claim 1, wherein the electronic circuit unit saves / restores data necessary for state recovery by serial data transfer.   4. The electronic circuit unit according to claim 3, further comprising a second signal path for switching the flip-flop to a shift register structure in accordance with a predetermined control signal, in addition to the first signal path in a normal state. The data processing apparatus described in 1.   When data is saved, data serially input from the electronic circuit unit is converted into parallel data and output to the nonvolatile memory. On the other hand, when data is restored, data input in parallel from the nonvolatile memory is serially converted and converted to the electronic circuit. 5. The data processing apparatus according to claim 3, further comprising a serial / parallel conversion unit that outputs to the unit.   2. The nonvolatile memory stores register data in a nonvolatile manner by utilizing one of a hysteresis characteristic of a ferroelectric material, a magnetoresistive effect of a magnetic material, and a phase change of an element. The data processing device according to claim 5.   Data evacuation connected to an electronic circuit having a data input port and a data output port for accessing a memory element inside the circuit from outside the circuit, and evacuating the data of the electronic circuit to the outside of the circuit via the data output port A data control circuit comprising a control function.   The internal data of the electronic circuit is register data, and is provided with a data return control function for returning the register data saved outside the circuit to the register of the electronic circuit via the data input port. The data control circuit according to claim 7.   The power supply on / off of the electronic circuit is monitored, the register data of the electronic circuit is saved when the power supply is cut off, and the register data is restored to the register of the electronic circuit when the power supply is turned on. 9. The data control circuit according to 8.   A power control unit that controls power on / off of the electronic circuit; and a state monitoring unit that monitors an operation state of the electronic circuit. When the electronic circuit is in a standby state, the register data 9. The power supply to the electronic circuit and the restoration of the register data are performed when the electronic circuit is to be saved and the power supply to the electronic circuit is shut off and the electronic circuit is to be returned from a standby state. Data control circuit.   The data control circuit according to claim 10, wherein the state monitoring unit monitors an input / output signal exchanged between the electronic circuit and a peripheral circuit to determine an operation state of the electronic circuit. .   The state monitoring unit detects that the electronic circuit is in a standby state when a data request signal is transmitted from the electronic circuit to the peripheral circuit, and from the peripheral circuit to the electronic circuit. 12. The data control circuit according to claim 11, wherein when the response signal is transmitted, it is detected that the electronic circuit should be returned from a standby state.   9. The data control circuit according to claim 8, wherein the register data is exchanged in accordance with processing executed in the electronic circuit.   14. The data control circuit according to claim 13, wherein when the register data is replaced, a data saving operation and a data restoring operation are executed simultaneously.   An electronic circuit having a register data input port and a register data output port for accessing a register inside the circuit from outside the circuit, the data control circuit according to any one of claims 7 to 14, and the register data A data processing apparatus having a storage circuit as a save destination.   16. The data processing apparatus according to claim 15, wherein the electronic circuit and the data control circuit are both integrated in the same chip.   16. The data processing apparatus according to claim 15, wherein the electronic circuit and the data control circuit are each integrated in separate chips.   18. The electronic circuit includes a parallel port that inputs and outputs a plurality of register data in parallel as the register data input port and the register data output port. A data processing device according to any one of the above.   The electronic circuit includes a second signal path for switching a flip-flop to a shift register structure in accordance with a predetermined control signal, in addition to the normal first signal path, and the register data input port and the register 18. The data according to claim 15, further comprising a serial port connected to the second signal path for serially inputting / outputting a plurality of register data as a data output port. Processing equipment.   20. The data processing apparatus according to claim 19, wherein the register data input port and the register data output port of the electronic circuit are debugging ports.   As the storage circuit, SRAM, DRAM, EEPROM, flash memory, FeRAM, MRAM, PRAM, RRAM, NVSRAM, BBSRAM, and similar memories, or latches, registers, and similar storage elements are used. The data processing apparatus according to any one of claims 15 to 20, wherein the data processing apparatus includes:   A data processing apparatus comprising: an electronic circuit; and a data control circuit connected to the electronic circuit, wherein the data control circuit includes a data saving control unit that saves data of the electronic circuit outside the circuit; A data recovery control unit that returns data saved outside the circuit to the electronic circuit, a recovery monitoring control unit that monitors a data recovery state in another data processing device, and data recovery in all data processing devices is completed. An operation resumption control unit for stopping the operation of the electronic circuit until the operation is completed.   23. The data processing apparatus according to claim 22, wherein when the data recovery of the electronic circuit is completed, the data recovery control unit sends a notification signal indicating the fact.   The return monitoring control unit monitors the notification signals transmitted from a plurality of data processing devices or their logical operation signals to determine whether or not the data recovery in all the data processing devices has been completed. 24. The data processing apparatus according to claim 23.   25. The data processing apparatus according to claim 22, wherein the operation resumption control unit controls supply / cutoff of a drive clock to the electronic circuit.   The data control circuit includes a state monitoring unit that monitors an operation state of the electronic circuit, and controls data save / restore of the electronic circuit according to a monitoring result. The data processing device according to any one of 22 to 25.   The state monitoring unit detects that the electronic circuit is in a standby state when a data request signal is transmitted from the electronic circuit to the peripheral circuit, and responds to the electronic circuit from the peripheral circuit. 27. The data processing apparatus according to claim 26, wherein when the signal is transmitted, it is detected that the electronic circuit should be returned from a standby state.   27. The data processing apparatus according to claim 26, wherein the state monitoring unit monitors a processing stop signal of the electronic circuit to determine an operating state of the electronic circuit.   27. The data processing apparatus according to claim 26, wherein the state monitoring unit monitors an exclusive signal indicating a standby state of the electronic circuit to determine an operation state of the electronic circuit.   27. The data processing according to claim 26, wherein the state monitoring unit determines an operation state of the electronic circuit by monitoring data exchanged via a general-purpose data input / output port of the electronic circuit. apparatus.

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