JPH08330964A - Digital/analog converter - Google Patents

Abstract

PURPOSE: To reduce the chip size as the whole by inputting and decoding a digital input signal and controlling switching of the decoded signal to first and second switch groups to reduce the output signal decoding part in an N-bit digital/analog converter. CONSTITUTION: A first switch group 2 which performs switching control based on the signal obtained by decoding the digital input signal so that each resistor of a first resistor network 1 is disconnected from the first resistor network 1 and a second switch group 4 which have taps led out from end parts of resistors constituting a second resistor network 3 and performs switching control based on the signal obtained by decoding the digital input signal so that taps are connected to an output terminal are provided. Further, a control circuit 5 which outputs a switching control signal to first and second switch groups 2 and 4 is provided. Thus, the required number of switch circuits and the circuit scale of the decoder circuit are considerably reduced to not only simplify the circuit constitution but also reduce the chip size as the whole.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital-analog converter (DAC), and more particularly to a high-precision digital-analog converter in which the circuit scale of an output signal decoding circuit is reduced.

[0002]

2. Description of the Related Art A conversion method of a digital-to-analog converter that converts an input digital signal into an analog signal output is a binary weight (Binary weight) in which a current and a voltage having a binary ratio are combined and output according to a digital input signal. -Weight) method and a resistance strings method in which a reference voltage is divided by a resistor network and an output is obtained from a desired tap in the resistor network according to a digital input signal are conventionally used.

FIG. 2 shows an example of the configuration of a conventional N-bit resistor string type digital-analog converter.

Referring to FIG. 2, V1 and V2 are first and second reference voltage sources serving as a reference for analog output.
Between the second reference voltage sources V1 and V2, resistors R1, R2, R3, ..., R2 ^N having the same resistance value according to the resolution are 2 ^N.
Resistor strings 6 each of which is connected in series are provided.

Further, a total of 2 ^N taps T1, T2, ..., T2 ^N are respectively drawn from the connection points of the first reference voltage source V1 and the resistors of the resistor string 6 to obtain the first and second reference voltages. The voltage of the sources V1 and V2 is configured to be divided into 2 ^N , and the output VO and taps T1, T2, ..., T
2 ^N number of switches SW1, SW2 to connect the 2 ^N,
, SW2 ^N is provided, and one side terminals of the switches SW1, SW2, ..., SW2 ^N are commonly connected to the output VO.

Upon receiving an N-bit digital input signal input from the digital signal input terminal VI, one switch of the decoding switch group 7 is selected according to the digital value input by the control circuit 5, and the selected switch is selected. Is closed (turned on) to obtain the desired analog output.

It should be noted that Japanese Patent Publication No. 3933/1993 discloses a resistor for upper N bits for the purpose of providing a digital analog converter capable of expanding the accuracy from an N bit digital analog converter to (N + P) bits. A digital-to-analog converter has been proposed which is configured to rearrange a network and a resistance network of lower P bits in parallel.

[0008]

In the configuration of the conventional resistor string type digital-analog converter, when the resolution is N bits, 2 ^N resistors are used to take out 2 ^N taps and controlled by a switch. However, there is a problem in that the circuit scale (and hence the area) of the decoding section increases as the resolution increases, and the area ratio to the entire area increases.

Further, in the structure disclosed in the above Japanese Patent Publication No. 3-20933, since the resistance network of the lower P bits is connected in parallel to the upper N bits, the impedance of the switch is included. There was a problem that it became a factor.

Therefore, the present invention solves the above-mentioned problems, and
It is an object of the present invention to provide a digital-to-analog converter that can reduce the output signal decoding unit in a bit digital-to-analog converter and reduce the chip size as a whole.

[0011]

In order to achieve the above object, the present invention provides a digital-to-analog converter that converts an N-bit (N is a predetermined integer) digital input signal into an analog voltage and outputs the analog voltage. A first resistance network connected between a first reference voltage source serving as a voltage reference and a second reference voltage source, wherein the first resistance network comprises:
Both ends of the resistor included in the first resistor network are divided by taps in order to divide the first reference voltage source and the second reference voltage source into 2 ^{(N / 2)} according to the resolution. , 2 ^{(N / 2)} resistors having the same resistance value are arranged in series, and each resistor of the first resistor network is connected from the first resistor network based on a signal obtained by decoding a digital input signal. the first group of switches, the first half of the resistance value per resistor one resistor network (N ^{/ 2)} resistance 2 having a resistance value of ^{(N / 2)} number of switching control to disconnect A second resistor network connected in series is further provided, and a tap is drawn out from an end of a resistor forming the second resistor network, and the tap is connected to an output terminal based on a signal obtained by decoding the digital input signal. And a second switch group for switching control so that the digital input signal is input. Providing a digital-analog converter, characterized in that the decoded decode signal and a control circuit for outputting a switching control signal to said first and second switch groups.

In the present invention, preferably the first
The switch group is configured such that the impedance of the first resistance network becomes constant regardless of whether the resistance of the first resistance network is disconnected by switching the first switch group. And

In the present invention, preferably the first
Switch group uses the signal obtained by decoding the digital input signal as a switching control signal to electrically connect both ends of the second resistance network to the first resistance network instead of the resistance separated from the first resistance network. It is characterized in that it is configured to be connected to.

The present invention comprises a first-stage resistor network connected between a first reference voltage source and a second reference voltage source, which serve as a reference for an analog output voltage, and the first-stage resistor network. A resistor network of a plurality of stages from the second stage to the Mth stage (M is a predetermined integer of M> 2) is provided for the network, and the first stage resistance network includes the first reference voltage source and the first reference voltage source. In order to divide the second reference voltage source according to the resolution, both ends of the resistor forming the first resistor network are divided by taps, and a plurality of resistors having the same resistance value are arranged in series. In the resistance network of the L-th stage (L = 2 to M), the resistance of the resistance network of the (L-1) -th stage is 1
The resistance constituting the resistance network from the first stage to the (M-1) th stage is equal to the resistance value per unit, and should be separated from each resistance network according to the value of the signal obtained by decoding the digital input signal by the corresponding switch group. The tap is drawn from the end of the resistor that constitutes the resistance network of the Mth stage which is the final stage, and is connected to the output terminal according to the signal obtained by decoding the digital input signal by the switch group corresponding to the tap. A digital-analog converter is provided, which is switch-controlled as described above, and further includes a control circuit that receives the digital input signal, decodes the digital input signal, and outputs the decoded signal.

In the present invention, preferably, both ends of the resistor network of the latter stage are electrically connected to the resistor network of the former stage instead of the resistors separated from the resistor network of the former stage based on the signal obtained by decoding the digital input signal. It is characterized by

[0016]

According to the present invention having the above-mentioned structure, the required number of switch circuits and the circuit scale of the decoder circuit are greatly reduced as compared with the conventional system, and the circuit structure is simplified and the total digital / analog converter is realized. To reduce the chip size. That is, in the conventional example shown in FIG. 2, 2 ^N switch parts are required as the resolution becomes higher, and the circuit scale of the decoder circuit increases, which causes an increase in chip size (for example, In the case of 8 bits, 2 ⁸ = 256 switches and a decoding circuit for outputting the corresponding 256 decoded signals are required.) According to the present invention, 4 × 2 ^{(N / 2)} + 4 + 2 ^{(N / 2)} = 84, which is about 1/3 to 1/4, which makes it possible to simplify the circuit configuration and reduce the total chip size as a digital-analog converter.

Further, according to the present invention, the impedance of the circuit including the first resistance network between the first and second reference voltage sources and the first switch group disconnects the resistance from the first resistance network, and Instead, the first switch group is configured so as not to change even when the second resistor network is connected in series, which results from the switch switching in the conventional method described in Japanese Patent Publication No. 3933/1993. The error is eliminated and high precision conversion is realized.

[0018]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows the circuit configuration of an N-bit digital-analog converter (N = 8) according to an embodiment of the present invention.

With reference to FIG. 1, the present embodiment has first and second embodiments.
In order to divide the reference voltage sources V1 and V2 of 2 into 2 ^(8/2) = 16, there is provided a first resistor network 1 in which 16 resistors having a resistance value R are arranged, and a tap is drawn out from each resistor, The connection with the second resistor network 3 is switched by the first switch group 2.

The second resistance network 3 has a resistance value R per resistance of the first resistance network 1 of 1/2 ^(8/2) = 1/16
A resistance having a resistance value r (r = R / 16) such that
1 to r16 are connected in series and taps t1 to t
16 is pulled out and is connected to the output VO by the second switch group 4.

Upon receiving the digital signal input to the digital input signal terminal VI, the control circuit 5 outputs a decode signal for controlling ON / OFF of each switch of the first and second switch groups 2 and 4. , The first switch group 2 includes resistors R1 to R1 of the first resistor network 1 selected by the digital input signal.
Any one resistor of R16 and the second resistor network 3 can be replaced with each other for connection.

The second switch group 4 is configured to deliver a signal to the output VO according to a digital signal.

The operation of this embodiment will be described in detail below.

For example, when the digital input signal is "00010100", the decode signal output from the control circuit 5 causes the switch SW0 of the first switch group 2 to have the terminal 1 turned on, the terminal 3 turned off, and the switch SW1 to be the terminal. 1 and 3 are both on, terminals 2 and 4 are both off, switch SW2 is terminals 2 and 4 are both on, terminals 1 and 3 are both off, and switch S is
In W16, the terminal 1 is turned on, the terminal 3 is turned off, and in the other switches SW3 to SW15, the terminals 1 and 4 are turned on and the terminals 2 and 3 are turned off, so that the resistor R2 is substantially disconnected from the first resistor network 1. .

At the same time, a second resistor network 3 having a resistance value equal to that of the resistor R2 is connected in series between the resistors R1 and R3 by the switches SW1 and SW2, and the second switch group 4 is connected via the tap t4. It is transferred to the output VO by the switch SW3 '.

In this way, the 8-bit digital input signal n
A desired analog output corresponding to (V1−V2) × (n / 2 ⁸ ) can be taken out from the output VO.

In FIG. 1, terminals 1 and 3 of the switch SW0 of the first switch group 2 and terminals 1 and 2 of the switch SW16.
Z is the impedance when the switch is on, and the switch SW
By setting the impedance when the terminals 1, 2, 3 and 4 of 1 to 15 are in the off state to Z ′ and having a relationship of Z = 2Z ′, the relative ratio of the impedances including the switch part can be changed by switching the switches. It will be constant.

In the conventional example, as the resolution becomes higher (= N bits), 2 ^N switch units are required and the circuit scale of the decoder circuit increases, which causes the increase of the chip size. For example, in the conventional example of FIG.
In the case of bits (N = 8), 2 ⁸ = 256 switches and decode signal lines are required), and according to the above embodiment, 4 × 2
^{(N / 2)} + 4 + 2 ^{(N / 2)} pieces (= 84), which is about 1/4, and the chip size can be reduced.
Further, according to the above-described embodiment, it is possible to provide a digital converter that prevents an error factor due to switch switching and enables highly accurate conversion.

In accordance with the principle of construction of the above-described embodiment, the resistance networks are arranged in multiple stages (M stages, M> 2), and the plurality of resistors constituting the L-th stage (L = 2 to M) resistance network are composed in series. The resistance value is equal to the resistance value per resistance of the resistance network of the previous stage (= L-1th stage), and the resistances that form the resistance network of the 1st stage to the M-1th stage are the corresponding second to second stages. The M-1 switch group controls the digital input signal to be separated from each resistor network according to the value of the decoded signal, and taps from the end of the resistor forming the final stage (= Mth stage) resistor network. And the tap may be controlled to be connected to the output terminal VO according to a signal obtained by decoding the digital input signal by the corresponding M-th switch group.

Although the present invention has been described with reference to the above embodiment, the present invention is not limited to the above embodiment,
As a matter of course, it includes various aspects according to the principle of the present invention.

[0031]

As described above, according to the present invention,
As compared with the conventional method, the number of switch circuits required and the circuit scale of the decoder circuit are significantly reduced, and the circuit configuration is simplified and the total chip size as a digital-analog converter is reduced. That is, in the conventional example, as the resolution becomes higher, 2 ^N switch sections are required and the circuit scale of the decoder circuit increases, which causes the increase in chip size (for example, in the case of 8 bits). 2 ⁸ = 256 switches and a decode circuit and decode signal wiring for outputting 256 decode signals corresponding thereto are required), according to the present invention,
It is possible to fit in about 1/4, which is 4 × 2 ^{(N / 2)} + 4 + 2 ^{(N / 2)} , and it is possible to simplify the circuit configuration and reduce the total chip size as a digital-analog converter.

According to the present invention, the Japanese Patent Publication No. 3-2093
There is an effect that an error factor due to switch switching in the conventional method described in Japanese Patent Publication No. 3 is prevented and a highly accurate digital-analog converter can be realized.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of an exemplary embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a conventional resistor string type digital-analog converter.

[Explanation of symbols]

 V1, V2 Reference voltage source VI Digital signal input terminal VO Analog signal output terminal 1 First resistance network 2 First switch group 3 Second resistance network 4 Second switch group 5 Control circuit 6 Resistor string 7 Decode switch group

Claims (5)

[Claims] 1. A digital-analog converter for converting an N-bit (N is a predetermined integer) digital input signal into an analog voltage and outputting the analog voltage, wherein a first reference voltage source and a second reference voltage source serving as a reference of the analog voltage to be output. A first resistor network connected between a reference voltage source and the first resistor network, wherein the first resistor network comprises the first reference voltage source and the second resistor network;
The reference voltage source and the reference voltage source are divided into 2 ^{(N / 2)} in accordance with the resolution, and both ends of the resistor included in the first resistor network are divided by taps.
^{The first (N / 2)} pieces are arranged in series, and each of the resistors of the first resistor network is switched and controlled so as to be disconnected from the first resistor network based on a signal obtained by decoding a digital input signal. A switch group and 1/2 of the resistance value per resistance of the first resistance network
^A second resistor network in which 2 ^{(N / 2)} resistors having a resistance value of ^{(N / 2)} are connected in series is further provided, and a tap is pulled out from an end portion of the resistor forming the second resistor network. A second switch group that controls switching so that the tap is connected to an output terminal based on a signal obtained by decoding the digital input signal; and inputting and decoding the digital input signal to decode the decoded signal 2. A digital-analog converter, comprising: a control circuit that outputs a switching control signal to a switch group of 2. 2. The impedance of the first resistor network is constant regardless of whether the first switch group disconnects a resistor from the first resistor network by switching the first switch group. The digital-analog converter according to claim 1, wherein the digital-analog converter is configured as described above. 3. The first switch group uses the signal obtained by decoding the digital input signal as a switching control signal in place of a resistor separated from the first resistor network, and connects both ends of the second resistor network to each other. The digital-analog converter according to claim 1, wherein the digital-analog converter is configured to be electrically connected to the first resistor network. 4. A first-stage resistance network connected between a first reference voltage source and a second reference voltage source serving as a reference of an analog output voltage, and the first-stage resistance network is provided. On the other hand, a plurality of resistance networks from the second stage to the Mth stage (M is a predetermined integer of M> 2) are provided, and the first stage resistance network includes the first reference voltage source and the second reference voltage source. In order to divide the reference voltage source according to the resolution, the first
Both ends of the resistors that form the resistor network are divided by taps, and a plurality of resistors having the same resistance value are arranged in series to form a resistor network of the Lth stage (L = 2 to M). The plurality of resistors that are configured have a combined series resistance value equal to the resistance value per resistor of the resistance network of the (L-1) th stage that is the preceding stage, and form a resistance network of the 1st stage to the M-1th stage. The resistors are switch-controlled by corresponding switch groups so as to be separated from each resistor network according to the value of the signal obtained by decoding the digital input signal, and tapped from the end of the resistors forming the final M-th stage resistor network. Switch control is performed so that the tap is connected to an output terminal according to a signal obtained by decoding the digital input signal by a corresponding switch group, and further, the digital input signal is input, decoded and decoded. A digital-analog converter, comprising: a control circuit that outputs a signal. 5. The resistance network of the latter stage is electrically connected to both ends of the resistance network of the latter stage in place of the resistance separated from the resistance network of the former stage based on the signal obtained by decoding the digital input signal. The digital-analog converter according to claim 4.