JPH08316946A - Clock break detection circuit - Google Patents

Abstract

PURPOSE: To detect the number of breaks of a clock to be monitored, which is asynchronous with a monitor clock and has the same speed as the monitor clock, in the unit of one clock by the monitor clock by using the monitor clock to detect the presence or the absence of a change point of the frequency divided clock to be monitored. CONSTITUTION: A clock CLK to be monitored has the frequency divided by (n) in a frequency division part 11, and the width of two clocks is given to high and low level parts by a decoder part 12, and the change point is shifted by one clock. The frequency divided clock to be monitored which has the change point shifted is applied to corresponding edge detection parts 21 to 24, and pulses having the width of one monitor clock are taken out by edge detection in these parts, and AND is operated in an AND part 3, and the result is applied to the load terminal of a counter 4. When AND is in the low level, the counting operation is not performed. When it is in the high level, the counting operation is performed; and at the time of full counts, a pulse is sent from the CO terminal to indicate that a break of the clock is detected.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock loss detection circuit used in, for example, a data transmission device.

[0002] Usually, during data transmission, data and a clock synchronized with this data (called a monitored clock) are sent from the transmitting side to the receiving side. On the receiving side, a disconnection of the received monitored clock may be detected using a system clock (referred to as a monitoring clock) that is asynchronous with the monitored clock at the same speed.

At this time, it is necessary to detect the number of monitored clocks in units of one clock.

[0004]

2. Description of the Related Art FIG. 6 is an explanatory view (1) of a conventional example.
(a) is a configuration diagram, (b) is an explanatory diagram of normal operation, and FIG. 7 is an explanatory diagram of a conventional example (No. 2). (a) is an abnormal operation (fixed to H)
And (b) is an explanatory diagram of another abnormal operation (fixed to L),
FIG. 8 is an explanatory diagram of another conventional example, (a) is a configuration diagram, (b) is an explanatory diagram of normal operation, and (c) is an abnormal operation (H → L, L →
It is explanatory drawing of (H).

6 to 8 will be described below.
(b), FIG. 7 (a), (b), FIG. 8 (b), and (c) have the reference numerals in FIG. 6 (a),
The waveform of the same code part in FIG. 8 (a) is shown. First, the clock loss detection is mainly performed by the following methods A and B. That is, A. When the monitoring clock and the monitored clock are asynchronous and have the same speed, the monitoring clock monitors the non-monitoring clock at regular intervals, and if there is no input of the monitored clock within that period, a clock outage occurs ( 6 and 7). B. If the monitored clock and the monitored clock are asynchronous and the monitored clock is slower than the monitored clock, the monitored clock detects the edge of the monitored clock, but a clock loss occurs when the edge detection period is longer than the preset period. Is the method (in the case of FIG. 8).

Now, as shown in FIG. 6 (a), the 2-bit counter 51 divides the input monitor clock (hereinafter, abbreviated as monitor CLK) by 4 to generate a CLK divided by 4 (see FIG. b)-,
FF is a flip-flop (hereinafter, FF)
Abbreviated as)) Add to CK pin of 54 and 55. Therefore, these FFs take in + 5V, that is, the "H" level at the rising point of CLK divided by 4.

On the other hand, through the AND gate 52 and the AND gate 53 which are turned on by the application of the "H" level XRST signal,
The monitored CLK and the inverted monitored CLK are
Applied to the R terminal of FF 55.

If the outputs of the AND gates 52 and 53 are at "L" level, the corresponding FF is reset, so FF 5
A narrow pulse is periodically output from the Q terminal of 4 by OR gate 56.
And the "L" level is ORed from the Q terminal of FF 55.
It is sent to the gate 56 (see Fig. 6 (b)-~ ,,)
.

This is due to AND gates 52, 53 and FFs 54, 55.
The signal passing through is output with a slight delay from the input side due to the delay generated in the element. However, it is applied to FF 54, 55
Since the output of the counter 51 is directly added to CLK, there is no delay.

Therefore, for FF 54, "H" from the Q terminal
Since it is reset immediately after sending the level, it becomes "L" level after a narrow pulse appears. However, FF 55 is in the reset state when + 5V is fetched, so it becomes "L" level without sending a narrow pulse.

Since the OR gate 56 takes the logical sum of the outputs of the FFs 54 and 55 and then sends the logical sum to the FF 57, the FF 57 takes in the logical sum output with the above-mentioned quarter frequency CLK. At this time, CL divided by 4
Since the state of the OR gate 56 at the rising edge of K is "L" level, "L" level is output from the Q terminal. Therefore, the clock loss alarm does not occur (see Fig. 6 (b)-,).

However, as shown in FIG. 7 (a)-, CL divided by 4
There is only one change point during one cycle of K, and for the rest of the cycle, when the monitored CLK fixed at "H" level is input, the output from AND gates 52, 53 shown in Fig. 7 (a)-, becomes FF. 54, 55 of
Apply to R terminal.

On the other hand, the 2-bit counter 51 uses the monitor CLK to generate a CLK divided by 4 and applies it to the CK terminals of the FFs 54 and 55.
(See Figure 7 (a)-,). Therefore, the FF 54, 55 sends the output shown in Fig. 7 (a)-, to the OR gate 56 according to the state of the R terminal and the CK terminal.
Send the output shown in to FF 57.

FF 57 is an OR gate at the rising edge of CLK divided by 4.
The output of 56 is taken in, but if the monitored CLK is not input during one cycle of CLK divided by 4, an alarm of the monitored CLK interruption is sent at the rising point of the next cycle (see Figure 7 (a)-). ).

Further, as shown in FIG. 7B, CLK divided by 4
There is only one change point during one cycle, and the rest of the cycle
When the monitored CLK with the fixed "L" level is input, as in the case with the fixed "H" level above, the monitored CLK is input at the rising point of the cycle next to one cycle of the quarter CLK without the monitored CLK input. CL
Sends a K disconnection alarm (see Figure 7 (b)).

Next, the portion of FF 61, FF 62 and AND gate 63 in FIG. 8A constitutes an edge detecting portion which operates with the monitor CLK. Therefore, when the monitor CLK detects a rising point of the monitored CLK, for example, AND pulse of "H" level is detected.
It is sent from the gate 63 to the counter 64. The monitored CLK
When is normal, the above pulse is sent to the counter at a constant cycle (see FIG. 8 (b)-).

Therefore, the counter 64 resets the count value each time a pulse is input, starts counting from 0, and sends the count value to the decoder 65. The decoder 65 monitors the decode output when the count value exceeds 4, for example.
It is sent as an alarm of CLK loss, but 4
Alarm is not sent because it does not exceed (Fig. 8 (b)-,
See).

However, as shown in FIG. 8 (c)-, the monitored CL
When an error occurs in K (the dotted line part is normal and there is no change point), the count value is not reset and increments as it is. Therefore, the decoder 65 has a count value of 4
When it becomes, an alarm will be sent out (Fig. 8 (c)-
~).

[0019]

As described above, by using the conventional techniques A and B, the condition that the number of CLKs in which the monitoring CLK and the monitored CLK are asynchronous and the speeds are the same can be detected in 1 CLK units. The following problems occur when detecting the CLK disconnection. In the case of conventional technology A, if the monitored CLK is not input at all during one cycle, the monitored CLK interruption occurs, so the exact number of CLK interruptions cannot be detected. Also, even if the CLK interruption is detected, the alarm does not occur until the next cycle comes, so it takes time from the occurrence of the interruption to the occurrence of the alarm. In the case of conventional technology B, the edge detection of the monitored CLK is monitored CL
It is not always possible to detect with K.

Since the change point of the monitored CLK is detected by the monitor CLK, the change point may not be detected when the change points of the two CLKs are the same. Therefore, the monitored CL
Even if K is input, it may be detected as disconnected.

An object of the present invention is to enable a supervisory clock to detect the number of monitored clocks having the same speed asynchronously with the supervisory clock in units of one clock.

[0022]

When a monitor clock detects a disconnection of a monitored clock of the same speed asynchronously with the monitor clock, the first aspect of the present invention is to provide frequency dividing means and clock disconnection detecting means. The monitored clock is frequency-divided by the frequency dividing means to generate n series of frequency-divided monitored clocks whose change points are sequentially shifted. Then, the clock break detecting means detects the presence or absence of a change point of the divided monitored clock by using the monitoring clock, and detects the break of the monitored clock in units of one clock from the detection result.

A second aspect of the present invention provides a clock loss detecting means,
Counting means for counting the detected number of monitored clocks is provided. The load value of the counting means can be set externally so that the number of alarms at the start of alarm transmission can be changed.

[0024]

1 is a block diagram showing the principle of the present invention, and FIG. 2 is a diagram for explaining the operation of FIG. The operation of FIG. 1 will be described below with reference to FIG.

First, in order to reliably detect the edge of the monitored CLK that is asynchronous with the monitoring CLK at the same speed as the monitoring CLK,
The monitored CLK needs to have a width of two or more monitoring CLK cycles. Therefore, after the frequency of the monitored CLK is divided by n in the frequency dividing means 1 (for example, by 4), the width of the "H" level portion and the width of the "L" level portion are divided by the decoder portion 12. The width of 2 CLK is secured for each, and the change point (for example, the rising point) is 1 CL.
Shift by K (see Figure 2-).

As a result, the monitored CLK is 1 CL of the monitored CLK.
It can be monitored in K units. Shown in Figure 2-
CLK is called the frequency-divided monitored CLK. Now, in addition to the divided monitored CLK whose change point is shifted to the corresponding edge detection part (operating with monitoring CKL) 21 to 24, the edge is detected in this part and a pulse of 1 monitoring CLK width is added. Then, the logical product is taken out in the logical product part 3 and added to the load (L) terminal of the counter 4. (See Figure 2--).

Here, by taking the above logical product,
As shown in Fig.2-, the place where the monitored CLK is missing 1 bit is "H" level of 1 monitor CLK width, and the place where 2 bits is missing is "H" level of 2 monitor CLK width.

On the other hand, similarly to the above, the counter 4 does not perform the counting operation when the logical product is at the "L" level, but performs the counting operation when the logical product is at the "H" level, and when the full count is reached, the CO pin is output. Pulse out to indicate clock loss detection. (See Figure 2-).

Since the load value can be set externally,
The number of monitored CLKs can be easily changed. For example, when the number of clock interruptions is 2, the output of the CO terminal of the counter remains "L" level when the output of the AND is 1 bit, but when it is 2 bits or more, it becomes "H" level and sent as an alarm. It

That is, the monitoring clock can detect the number of monitored clocks having the same speed asynchronously with the monitoring clock in units of one clock.

[0031]

FIG. 3 is a block diagram of the first embodiment of the present invention, and FIG.
Is a configuration diagram of the second embodiment of the present invention, and FIG. 5 is an operation explanatory diagram of FIG.

Here, the same reference numerals denote the same objects throughout the drawings. Further, the reference numerals on the left side of FIG. 5 indicate the waveforms of the portions having the same reference numerals in FIG. The operation explanatory diagram of FIG. 3 is the same as FIG. 2, and the dotted line portion 2 in FIGS. 3 and 4 is a specific configuration example of the edge detecting means 2 in FIG.

3 to 5 will be described below with the frequency division ratio n = 4, the parts described in detail above will be briefly described, and the part of the present invention will be described in detail. In Fig. 3, the Q0 output and Q1 output of the 2-bit counter 11a operating with the monitored CLK are generated through the EX-NOR gate 12a, and the pulse shown in Fig. 2--1 and the inverted pulse are generated as shown in Fig. 2-3. To do.

The pulse shown in FIG. 2-2 and the pulse shown in FIG. 2-4 are generated from the Q1 output of the 2-bit counter 11a, and the pulse shown in FIG. 2-4 is generated. The monitor CLK is sequentially shifted by one bit width.

Further, FF 211a, FF 212a, AND gate 213a
2 constitutes an edge detecting portion, that is, a differentiating circuit 21a,
-The rising edge of the pulse shown in -1 is detected, and if the edge can be detected, 1 CLK of the monitor CLK as shown in Figure 2--1.
Output "L" level pulse of width.

Similarly, each of the differentiating circuits 22a, 23a, 24a outputs an "L" level pulse having a 1 CLK width of the monitor CLK as shown in FIGS. 2-2 to 2-4 if an edge can be detected. . Then, these four pulses are logically ANDed by the AND gate 3 to form one pulse, which is applied to the L terminal of the 6-bit counter 4, for example.

The load value can be made variable by setting it with a switch SW from the outside. However, since the counter is 6 bits, the load value is also 6 bits (0 to 63 can be changed). Set. The counter 4 does not count up and outputs the load value as it is because the "L" pulse is input to the L terminal while the differential circuit is performing edge detection.

However, while the edge cannot be detected (the monitored
When CLK is off), "H" pulse is input to the L terminal, so the counter 4 counts up and outputs a pulse from the CO terminal of the counter when the counter is fully counted.

That is, since the value of (full count number)-(load value) is the number of clock loss detections, the number of clocks can be changed by changing the load value. For example, as shown in Fig.2--, the load value of the counter 4 is set to "2".
If the monitored CLK is cut off by 2 CLK while set to, the counter sends an "H" pulse from the CO pin and an alarm is sent. However, when 1 CLK is cut off, no "H" pulse is output, so no alarm is sent.

FIG. 4 shows a microcomputer (not shown)
(Hereinafter, abbreviated as "microcomputer") is used to set the number of clock interruptions. Omit it.

Since the load value from the microcomputer (not shown) is stored in the register 41, this value is inverted and input to the D terminal of the 6-bit counter 4. For example,
When the register value is 000001, 111110 is loaded.

When the "H" level pulse is input from the AND gate 3 to the L terminal, the counter 4 starts the counting operation, increments the count value by one, and sends the carry to the register 42 from the CO terminal.

As a result, the register 42 holds this carry and outputs it as an alarm, but the output of the alarm is stopped by adding the read timing to the E terminal of the register (see FIGS. 5--2).

That is, in the present invention, the monitored CLK and the monitored CLK are
If the two are asynchronous and have the same speed, the non-monitored CLK can be monitored in units of 1 CLK. Therefore, it is possible to accurately detect the clock loss for the number of interruptions and "H" only for the time when the CLK interruption occurs.
Level pulses can be generated.

In addition, the occurrence and recovery of clock loss are asynchronous CL
It can be done by changing time of K and 1 CLK of monitoring CLK. For example, the rising edge of the clock disappears in the dotted line portion of FIG. 5A, but the detection time for this is almost zero as shown in FIG.

Since the setting of the number of cuts can be changed from the outside, the setting of the number of cuts can be changed after the design. In particular,
When setting the number of breaks with a microcomputer or the like, external setting pins and the like are not required and can be easily changed.

[0047]

As described in detail above, according to the present invention, there is an effect that the supervisory clock can detect the number of monitored clocks of the same speed asynchronously with the supervisory clock in units of one clock.

[Brief description of drawings]

FIG. 1 is a block diagram showing the principle of the present invention.

FIG. 2 is an operation explanatory diagram of FIG. 1;

FIG. 3 is a configuration diagram of an embodiment of the first present invention.

FIG. 4 is a configuration diagram of a second embodiment of the present invention.

5 is an operation explanatory diagram of FIG. 4;

FIG. 6 is an explanatory view (1) of a conventional example, (a) is a configuration diagram,
(b) is an explanatory view at the time of normal operation.

7A and 7B are explanatory views of a conventional example (part 2), FIG. 7A is an explanatory view during abnormal operation (fixed to H), and FIG. 7B is an explanatory view during another abnormal operation (fixed to L).

FIG. 8 is an explanatory diagram of another conventional example, (a) is a configuration diagram, (b) is an explanatory diagram at the time of normal operation, and (c) is at the time of abnormal operation (H → L, L →
It is explanatory drawing of (H).

[Explanation of symbols] 1 frequency dividing means 3 AND gate 4 counter 11 frequency dividing portion 12 decoder 21 to 24 edge detecting portion

Front page continued (72) Inventor Shinya Takigawa 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Fujitsu Limited

Claims (2)

[Claims] 1. When a monitoring clock detects a disconnection of a monitored clock of the same speed asynchronously with the monitoring clock, the monitored clock is divided by n (a positive integer of n ≧ 4) to obtain a change point. Frequency dividing means for sequentially generating the shifted n-series divided monitored clocks, and the presence or absence of a change point of the divided monitored clocks are detected using the monitoring clocks, and the monitored clocks are disconnected from the detection result. A clock loss detection circuit having a clock loss detection means for detecting in units of one clock. 2. The clock loss detecting means is provided with a counting means for counting the number of detected monitored clock interruptions, the load value of the counting means can be set externally, and the clock interruption alarm transmission start time is set. 2. The clock loss detection circuit according to claim 1, wherein the number of interruptions is variable.