KR100208295B1 - Clock monitor - Google Patents

Abstract

The present invention relates to a clock monitoring apparatus for detecting a duplicated clock signal to determine whether or not a normal clock signal is input. To this end, the present invention is a value counted by performing an up count on a rising edge of a duplicated clock signal. The watch signal counter continuously outputting the signal, and when the count value of the clock signal provided from the watch clock counter reaches a first predetermined value, a trigger signal having a 'LOW' level is generated to initialize the counter and the error detector. The trigger signal generator generates a counted value by continuously counting up the reference clock and initializes the count value generated based on the trigger signal of the 'LOW' level provided from the trigger signal generator. If the set value is reached, error detection is determined as an error of the redundant clock signal and output as an error signal. Includes entry.

Description

Clock monitor

The present invention relates to a clock monitoring apparatus of an all-electronic switch, and more particularly, to a clock monitoring apparatus for detecting a normalized clock signal by detecting a duplicated clock signal in a redundant serial communication path configuration.

In general, a clock monitoring device for monitoring a duplicated clock signal used in an all-electronic exchange is implemented using an integrated circuit 74LS393 chip. The 74LS393 chip includes a reference clock input terminal, a monitoring clock input terminal, and an error signal output terminal. Therefore, when there is no input of the monitoring clock, the internal counter performs up counting on the rising edge of the reference clock and outputs an error detection signal based on the counted clock.

FIG. 1 is a diagram showing the configuration of a 74LS393 chip having a conventional clock monitoring function, and is not shown when a reference clock (FIG. 5A) is periodically input to the 74LS393 chip and a monitoring clock (FIG. 5B) is normally input. The internal counter does not count, and the output waveform (Figure 5d) also remains LOW, indicating that the watchdog clock is normal.

The reference clock at this time must be longer or at least equal to the period than the monitoring clock.

If the watchdog clock is 'LOW', that is, if the watchdog clock is not input, the count by the reference clock is increased, and the output Q is 'HIGH' based on the counted clock, thereby indicating an error of the watchdog clock. Will occur.

However, there is a problem that the 74LS393 chip continues to be cleared and generates an error signal even when the watchdog clock is 'HIGH' again, that is, even when the watchdog clock is in a normal state. → There is a problem that the monitoring function cannot be performed properly by repeatedly outputting abnormal signals.

Accordingly, the present invention is to solve the above-mentioned problems of the prior art, the clock clock can detect the error in both the 'HIGH' or 'LOW' state and the clock monitoring that can detect the error regardless of the period of the reference clock The purpose is to provide a device.

In order to achieve the above object, the present invention provides a clock clock counter for continuously outputting a counted value by performing an up count at a rising edge of a duplicated clock signal, and a count value for a clock signal provided from the clock clock counter is increased. A trigger signal generator for generating a trigger signal having a 'LOW' level when the first predetermined value is reached to initialize the counter and the error detector, and continuously counting up the reference clock to generate a counted value from the trigger signal generator. It includes an error detection unit for initializing the count value generated based on the trigger signal of the 'LOW' level provided, and if the generated count value is a predetermined value to determine the failure of the duplicated clock signal and output as an error signal Provides a clock monitor.

1 is a diagram showing a configuration of a 74LS393 chip having a conventional clock monitoring function.

2 is a block diagram showing the configuration of a clock monitoring apparatus according to a preferred embodiment of the present invention.

3 is a diagram illustrating a configuration of a monitoring clock counter unit in a clock monitoring apparatus according to an embodiment of the present invention.

4 is a diagram showing the configuration of an error detector in a clock monitoring apparatus according to an embodiment of the present invention.

5 is a diagram illustrating a reference clock, a monitoring clock, and an output signal of a counter and an error detector input to a clock monitoring apparatus.

* Explanation of symbols for main parts of the drawings

10: watch clock counter 20: trigger signal generator

30: error detection unit

The above and other objects and various advantages of the present invention will become more apparent from the preferred embodiments of the present invention described below with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram showing the configuration of a clock monitoring apparatus according to a preferred embodiment of the present invention, which includes a monitoring clock counter 10, a trigger signal generator 20, and an error detector 30.

The supervisory clock counter unit 10 has an input terminal for a supervisory clock (Fig. 5b) and a reset signal, and the trigger signal generator 20 is a supervisory clock counter unit based on the reference clock (Fig. 5a). A trigger signal is generated from the count signal of (10) and supplied to the monitoring clock counter unit 10 and the error detector 30 again, and the error detector 30 is also triggered based on the reference clock (FIG. 5A). The error generation signal is output from the trigger signal provided from the signal generator 20.

The trigger signal generator 20 is configured to transition the trigger signal between the 'HIGH' level and the 'LOW' level in synchronization with the reference clock.

This state transition causes the trigger signal to be at the 'LOW' level when the output of the monitoring clock counter unit 10 becomes a preset count value, for example, '3', and immediately sets the trigger signal at the 'LOW' level to 'HIGH'. 'Make it level.

Thus, the trigger signal transitions to the 'LOW' level for every one period of the reference clock.

3 is a diagram illustrating a detailed configuration of a monitoring clock counter unit 10 that counts a monitoring clock in a clock monitoring apparatus according to an embodiment of the present invention, wherein the monitoring clock input terminal, the logic of the reset signal and the trigger signal are logic. A stage for inputting the OR gate and the result of the OR gate to be multiplied, and a 3-bit counter having counter output stages Q1, Q2, and Q3.

The monitoring clock counter unit 10 counts up at the rising edge of the monitoring clock, and initializes the count value when the reset signal from the outside or the 'LOW' level of the trigger signal from the trigger signal generator 20 is input.

That is, after the count value becomes '0' by the reset signal in the initial state, the up counting is performed in synchronization with the rising edge of the inputted watch clock, and when the trigger signal is provided from the trigger signal generator 20 during the up counting. The count value is initialized to '0'.

4 is a diagram illustrating a configuration of an error detector in a clock monitoring apparatus according to an exemplary embodiment of the present invention, which includes a reference clock input terminal, a trigger signal input terminal, and an error signal output terminal P as shown in the same diagram. It consists of a 4-bit up counter.

The above-described error detector 30 continuously counts the reference clock inputted periodically. When the trigger signal provided from the trigger signal generator 20 is provided in a 'LOW' state, the counted value is set to '0'. It will clear and count the reference clock again.

In addition, an inverter circuit is configured at the trigger signal input terminal of the monitoring clock counter unit 10 shown in FIG. 3 and the trigger signal input terminal of the error detection unit 30 shown in FIG. Even if the signal provided from 20) is a 'LOW' signal, each signal is input as a 'HIGH' signal equal to the level of the reset signal.

In this embodiment, the operation of the clock monitoring apparatus on the assumption that the period of the reference clock is about twice as fast as that of the monitoring clock will be described.

When the monitoring clock (FIG. 5a) is normally input, the monitoring clock counter unit 10 performs up counting on the rising edge of the monitoring clock and outputs the counted value through the output terminals Q1, Q2, and Q3 to generate the trigger signal. Provided at 20.

The trigger signal generator 20 may output a trigger signal having a 'LOW' level when the count value output from the watch clock counter 10 is a preset value, for example, '3'. By providing the reset input terminal, the monitoring clock counter unit 10 is initialized to '0' so that the monitoring clock counter unit 10 performs counting again.

In addition, the error detection unit 30 also clears the count value of the reference clock by the 'LOW' level trigger signal provided from the trigger signal generator 20 while up counting the input reference clock (FIG. 5a). Perform counting again.

On the other hand, since the trigger signal generator 20 maintains the 'LOW' state only for one cycle of the reference clock (FIG. 5a), the trigger signal generator 20 switches to the 'HIGH' state after one cycle of the reference clock. 10 and the error detector 30 may perform counting again after initializing the value counted by the trigger signal.

As described above, when a failure occurs while the periodic watch clock is normally input and the input of the watch is interrupted or a fault occurs in the watch, only the signal of the 'LOW' or 'HIGH' level is input. ) Stops counting operation because there is no rising edge of watch clock.

Accordingly, since the count value of the watched clock provided from the watched clock counter 10 is not '3', the trigger signal generator 20 continuously outputs a trigger signal having a 'HIGH' level, and the watched clock counter ( 10) and the error detector 30 cannot be initialized, the error detector 30 continuously counts the input reference clock to generate an error signal when the counted value becomes a predetermined value, for example, '8'. do.

On the other hand, if an error occurs and outputs an error signal, and then the normal monitoring clock is input again, the monitoring clock counter unit 10 counts the monitoring clock following the previously counted value and provides it to the trigger signal generator 20. When the count signal '3' provided from the watch clock counter 10 is initialized, the trigger signal generator 20 initializes the watch clock counter 10 to perform counting again, and to the reference clock of the error detector. The error detection unit 30 also stops the output of the error occurrence signal by initializing the count value.

In the above-described embodiment, the watch clock counter 10 is configured as a 3-bit counter so that when the output becomes '3', the trigger signal generator 20 outputs a trigger signal having a 'LOW' state. The error value is output by setting the counter value of the error detection unit 30 to '8', but this adjusts the period of the reference clock to adjust the error detection speed by the clock, that is, the speed at which the error signal is output by the counted value. There is a number.

As described above, according to the present invention, it is possible to detect both the continuous 'HIGH' and the 'LOW' error of the clock signal, so that the redundant circuit configuration can be easily effected. It is also possible to detect an error in which no rising edge occurs.

Claims (4)

A clock monitoring apparatus for detecting a duplicated clock signal and determining whether or not a normal clock signal is inputted, the clock monitoring apparatus comprising: a monitoring clock counter for continuously outputting a counted value by performing an up count at an rising edge of the duplicated clock signal; ; A trigger signal generator for generating a trigger signal having a 'LOW' level when the count value of the clock signal provided from the watch clock counter reaches a first predetermined value to initialize the counter and the error detector; Continue counting up a reference clock to generate a counted value and initialize the generated count value based on the trigger signal of the 'LOW' level provided from the trigger signal generator, wherein the generated count value is a preset value. In this case, the clock monitoring device including an error detection unit for determining that the redundant clock signal is a failure and outputs as an error signal. 2. The clock monitoring apparatus according to claim 1, wherein said monitoring clock counter comprises a 3-bit up counter. The clock monitoring device according to claim 1, wherein the error detection unit comprises a 4-bit up counter. The clock monitoring apparatus according to claim 1, wherein the period of the reference clock is twice that of the redundant clock cycle.