JPH08263456A - Diagnostic controller - Google Patents

Abstract

PURPOSE: To accelerate fault processing by providing specified connection memories in respective parallelly connected cards, reporting fault generation to a diagnostic processor(DGP) at such a time and parallelly performing diagnostic control inside the cards corresponding to an instruction from the DGP for each card. CONSTITUTION: Respective CPU cards are composed of CPUs 2-1 to 2-4, system control parts 2-5 and diagnostic control parts 2-6 equipped with control memories 2-7 and the control memory 2-7 stores the respective routines of reset processing, initializing processing, constitution control processing, fault processing and diagnostic processing. When any fault is generated at the CPU inside the CPU card during ordinary operation, the fault processing routine in the control memory 2-7 is started and the generation of the fault is reported to a DGP 1-6. The DGP 1-6 discriminates the degree of that fault and outputs the instruction corresponding to this degree, and the control memory 2-7 parallelly performs diagnostic control inside the card for each card based on the instruction from the DGP 1-6.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a diagnostic control device, and more particularly to a diagnostic control in an information processing device constituted by connecting a plurality of cards each having a plurality of CPUs and a diagnostic processor (hereinafter referred to as "DGP") via a bus. Regarding the device.

[0002]

2. Description of the Related Art Conventionally, in the field of information processing apparatuses, since performance by a single processor was emphasized, there was a DGP in a tightly coupled unit, and since there were few CPUs, each CPU and DGP forming a tightly coupled unit. There is an individual diagnostic bus between them, and diagnostic control is performed by using this diagnostic bus.
It was possible directly from.

However, in an information processing device in which cards having a plurality of CPUs are connected in parallel by bus connection or the like,
There is a physical limit to the one-to-one connection of the diagnostic bus between the DGP and each CPU. Therefore, conventionally, a diagnostic control unit by hardware is provided in each card, and an instruction from the DGP is received and the corresponding control is performed only by the hardware.

[0004]

In the above-described conventional diagnostic control device, the diagnostic control unit is constructed by all hardware even if only reset, process setting, configuration control, and fault processing are considered as typical processes from the DGP. If you do, DGP-
It is just a relay point between CPUs, and control frequently sends instructions from DGP, and depending on the processing content, it must receive a reply to confirm that it has completed normally each time.
The processing that can be performed on multiple cards at the same time is limited, and when different processing is to be performed on two or more cards, in most cases C will be issued after confirming that the previous processing is completed with DGP.
There is a problem that the processing is delayed as the number of PUs increases.

[0005]

The apparatus of the present invention is provided with a plurality of central processing units each comprising a computing unit and a system control unit mounted on one card, and the diagnostics in an information processing unit in which the cards are connected in parallel. In the control device, each card is provided with a control memory for storing a routine for performing fault processing and diagnostic control, and when the fault occurs, the routine is activated to report to the diagnostic processor, and at the same time the DGP instructs the card The diagnostic control of is performed in parallel for each card.

[0006]

The present invention provides the DGP by providing the control memory.
Between CPU card and CPU card, commands such as reset, initial setting, configuration control, etc. can be continuously performed for a specific CPU, or only one process can be provided, and DGP issues necessary commands depending on the case. This is done by activating the control memory in the diagnostic control unit, and the DGP can recognize that the processing has been completed by returning the normal reply indicating that the command sent was processed normally within a fixed time.

Also, during normal operation, if some failure occurs in the CPU card, the control memory in the diagnostic control unit is activated, and the failure is a serious failure to immediately stop the system. Only by logically disconnecting it from the system, it is possible to continuously operate the system to determine whether it is a minor fault, and when it is a serious fault, the DGP
The CPU is instructed to stop, the CPU disconnected is reported in the case of a slight failure, and CPU diagnostic control is performed by command processing from the DGP.

[0008]

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 2 shows an embodiment of the present invention.
CPU card 1 with 4 CPUs each
1 to 1-4 and one card constituting the main memory 1-5 are connected by a bus, and a dedicated path is provided between each card 1-1 to 1-5 and the diagnostic processor 1-6.

The configuration of each CPU card is the same.
As shown in FIG. 4, it is composed of four CPUs 2-1 to 2-4, a system control unit 2-5, and a diagnostic control unit 2-6 having a control memory 2-7. As shown in FIG. 3, the control memory 2-7 in the diagnostic control unit 2-6 has a reset process 3-1,
Initialization processing 3-2, configuration control processing 3-3, failure processing 3
-4, memorize | store each routine of the diagnostic process 3-5. Furthermore,
The processing flow when a failure occurs in the CPU is shown in FIGS.

During normal operation, the CP in the CPU card 1-1
When a failure occurs in U2-1, the failure processing routine 3-4 in the same card 1-1 is activated, the failure occurrence is reported to the diagnostic control unit 2-6, and the control memory 2-7 in the diagnostic control unit is notified. If the system is started up and the fault that has occurred is a serious fault to stop the system, the DGP1 is stored in the control memory 2-7.
A system stop instruction is issued to -6, DGP1-6 recognizes it, and the system goes down.

On the other hand, if the fault that has occurred is a minor fault that does not hinder the continuous operation of the system by logically disconnecting only the CPU 2-1 from the system, then the control memory 2-7 outputs DGP1- The unit to be disconnected (CPU 2-1 in this case) is reported to 6. DGP1-
6 reports to the diagnostic control unit in each card that the CPU 2-1 has been disconnected from the system. In the diagnostic control unit in each card, the configuration control routine in the control storage unit 3-
3 starts and logically disconnects the interface with the CPU 2-1. Furthermore, the control memory 2-7 of the CPU card 1-1
Sends the failure information of the CPU 2-1 to the failure information storage area of the main memory 1-5.

Upon receiving the replies from all the cards, the DGP 1-6 instructs the diagnostic control unit 2-6 in the CPU card 1-1 to reset the CPU 2-1. The reset control routine 3-1 in the control memory 2-7 is activated by the diagnostic control unit 2-6 of the CPU card 1-1 to reset the CPU 2-1.

When the DGP 1-6 receives a reply from the diagnostic controller 2-6 of the CPU card 1-1, the CPU card 1
FW to CPU 2-1 for diagnostic control unit 2-6 in -1
Instruct to load. Diagnostic control unit 2 of CPU card 1-1
Initial setting processing routine in control memory 2-7 from 6
2 starts, and FW is loaded into the CPU 2-1.

When the DGP 1-6 receives a reply from the diagnostic control unit 2-6 of the CPU card 1-1, the CPU card 1
The diagnostic control unit 2-6 in -1 is instructed to start the test program to the CPU 2-1. The diagnostic control unit 2-6 of the CPU card 1-1 activates the diagnostic processing routine 3-5 in the control memory 2-7, and the CPU 2-1 executes the test program. Report the recurrence of the failure to the DGP1-6 during the execution of the test program.

DGP1-6 is CPU2-
1 is regarded as having a fixed failure, and thereafter, the operation is continued in the CPU 12-1 disconnected state. If the failure does not recur, the CPU
It is considered that 2-1 can be installed again, and the diagnosis control units 2-6 of all cards are informed of the installation of the CPU 2-1 into the system. The configuration control routine 3-3 in the control storage unit 2-7 is activated by the diagnostic control unit 2-6 in each card, and the CPU
The interface with 2-1 is logically connected. After that, the system operates in the same state as before the failure.

The processing procedure when one failure occurs has been described above with reference to the flow shown in FIG. 4, but when two failures occur simultaneously, the reset processing routine, the processing setting processing routine, and the diagnostic processing shown in FIG. The routines can be started at the same time.

[0018]

As described above, according to the present invention, the CPU for each group (card) is provided with the control memory dedicated to the diagnostic control, so that the command for the process required by the DGP is issued to the desired CPU. Only possible. Further, according to the present invention, in a system in which a plurality of CPUs are connected in parallel, when a failure occurs in a different group, the processing can be executed individually, so that the failure processing is speeded up as compared with the conventional case.

[Brief description of drawings]

FIG. 1 is a detailed view of each CPU card shown in FIG.

FIG. 2 is a block diagram of an embodiment of the present invention.

FIG. 3 is a diagram showing an example of a control routine held in the control storage unit shown in FIG.

FIG. 4 is a processing flowchart when a failure occurs in the present invention.

FIG. 5 is a processing flowchart following FIG. 4 when a failure occurs in the present invention.

[Explanation of symbols]

 1-1 to 1-4 CPU card 1-5 Main memory 1-6 Diagnostic processor (DGP) 2-1 to 2-4 CPU 2-5 System controller 2-6 Diagnostic controller 2-7 Control memory.

Claims (2)

[Claims] 1. A diagnostic control device in an information processing device, wherein a plurality of central processing units each comprising a computing unit and a system control unit are mounted on one card, and the cards are connected in parallel. And a control memory for storing a routine for performing diagnostic control, and when a failure occurs, the routine is activated to report to the diagnostic processor, and the instruction from the diagnostic processor causes the diagnostic control in the card to be performed in parallel for each card. Diagnostic control device. 2. The card determines whether or not the failure is a serious failure and reports it to the diagnostic processor. If the diagnostic processor is a serious failure, the system is stopped. 2. The diagnostic processing device according to claim 1, wherein the output of information and the instruction to disconnect the faulty processor are given to other processors.