JPS60195649A - Error reporting system of microprogram-controlled type data processor - Google Patents

Abstract

PURPOSE:To prevent an entire system from being seriously affected by faults, by causing a diagnostic processor to make the error report of faults occurring in a sub-processor through a common system bus in the place of the sub-processor. CONSTITUTION:A program routine running in a diagnostic processor (SVP)4 recognizes that an abnormal condition occurs in a specific input-output controlling device (IOP)3 from the microprogram run abnormal bit of the content of a status register in the IOP3. The SVP4 edits the error status from the content of the status register and reprots the error status to an arithmetic processor (EPU)1 through a system bus 100 in the place of the IOP3. Therefore, the software of the EPU1 can receive the fault reprot, can recognize the IOP3 in which the fault occurs, and can processed the software sequence by forcedly terminating the I/O instruction.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to an error reporting method in a microprogram controlled data processing device. In particular, the present invention relates to an error reporting method in a data processing device having an arithmetic processing unit and a plurality of microprogram-controlled subprocessors including a diagnostic processor.

(Prior Art) Generally, an error reporting method when a failure occurs in a microprogram-controlled data processing device is performed as follows.

That is, when the error detection circuit of the data processing device detects a hardware error, the microprogram sequence of the data processing device traps the error handling routine, analyzes the hardware error, resets the cause of the error, etc., and executes seven lines, and then returns to the software program. In response, a report is made that a hard error has occurred. The software program that received the report was 1. For example, if the cause of the error was the I10 boat, I would try to recover the I10 instruction by issuing an initialization command for the I10 boat, and if it was an error in the main memory, it would generate an error. Processing is performed to avoid using areas of the main memory that have been used.

However, recovery processing as described above is possible only when the microprogram sequence for error handling operates correctly, and if the microprogram itself loops or stops, it will not be possible to report the error.
Even the occurrence of a failure cannot be detected.

Recently, data processing equipment has become more complex, and in the case of systems where the data processing equipment is composed of multiple subprocessors, one subprocessor may stall due to a failure, making it impossible to report a problem. This has a significant impact on the operation of the system. Therefore, a diagnostic processor is introduced, which connects each sub-processor via a diagnostic bus, and monitors the status of each sub-processor.

According to this method, the diagnostic processor checks the status of each subprocessor and can detect whether the microprogram of the subprocessor is stopped or in a loop. However, even with this method, there is a possibility that the instruction issued to the faulty processor will not be completed, and if the software is waiting for the instruction to complete, the system operation will still be affected. This will have a significant impact.

(Objective of the Invention) The object of the present invention is to eliminate the above-mentioned conventional drawbacks, and to provide a system in which even if a sub-processor in the 7 systems stalls due to some kind of failure, this does not seriously affect the operation of the entire system. The objective is to provide an error reporting method that can avoid such problems.

(Structure of the Invention) The method of the present invention provides a data processing device having a configuration in which a plurality of micro-10 gram control type subprocessors including a diagnostic processor' are connected to a common system bus and a diagnostic bus, wherein the diagnostic processor is connected to a common system bus and a diagnostic bus. [having means for detecting an abnormal state of each of the sub-processors by reading an identifier and a status register of each of the sub-processors connected to the diagnostic bus via a bus,
When the diagnostic processor uses the means to diagnose that the faulty subprocessor is in a state where it is unable to report an error regarding a fault that has occurred in each of the subprocessors other than the diagnostic processor, the faulty subprocessor Instead, error reporting is performed via the common system bus.

(Example) Next, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. This embodiment includes an arithmetic processing unit 1 (hereinafter referred to as BPUl), a main storage unit 2 (hereinafter referred to as MMU2), and input/output control units 3-1 and 3-2.
(hereinafter l0P3-1, l0P3-2), diagnostic processor 4 (hereinafter SVP4), input/output device 5-1.5-
2..., 5-N (hereinafter referred to as DEV 5-1, 5-2...
・5-N), system bus 100 and diagnostic bus 2
Contains 00.

In addition, each l0P3 includes a microprogram execution control unit 31. System bus control unit 322 Diagnostic bus control unit 33. It has a status register 34 and a processor identifier 35.

Furthermore, as shown in FIG. 3, the 8VP4 includes a microprogram execution control section 41. It includes a system bus control section 42 and a diagnostic bus control section 43.

Now, the EPUI reads and executes one software instruction in MMUZ, and if the instruction is an input/output instruction (hereinafter referred to as an I10 instruction), the EPUI executes an I10 instruction for the specified l0P3.
This l0
End interrupt sound from P3 Reports to software. on the other hand,
When a program error occurs in an instruction inside the EPUI, a corresponding program interrupt is reported to the software. Including these processes, EPUl is also responsible for the role of a system-based processor.

Next, each l0P3 is a sub-processor to which the DEV5 of %DEV5-1 to s-N, which is in charge of itself, is connected to its I10 boat. When the I10 command from EPUl is received via the system bus 100t'', this
Analyze 10 instructions and write I10 for the specified DEV5.
A command is issued to instruct execution of this I10 instruction. This DI! ;V5 completes execution of I10 command 7th command
3, l0P3 arranges the exit status and E
Reports the completion of the I10 instruction to PU 1.

Furthermore, the 5VP4 has a function of exchanging information with the EPUl via the system bus 100 like other subprocessors. Furthermore, the 5VP4 has a function of checking the status of each sub-processor of the EPUL, MMU2, and 10P3 via a dedicated diagnostic bus 200, and performing processing as described later in accordance with the result of this check.

Now, as shown in FIG. 2, each l0P3 has an internal microprogram execution control section 31, and its operation is controlled by a microprogram routine that operates within this section. Under normal conditions, l0P3 is connected to EP via system bus 100 and system bus control unit 32.
It exchanges information with Ul, receives an instruction to execute the I10 instruction from EPUI, and reports the completion of the 110 instruction to EPUI. If a hardware error occurs inside the 10P3, a hardware processing microprogram routine is activated, and the system bus controller 32 and the system bus 100 also report the failure via 'e'.
Perform this for 1EPU1.

Based on these reports, the EPU1 software advances the processing steps or attempts to recover the I10 instructions by issuing an initialization command to the I10 boat (not shown). In this manner, when the microprogram in 10PB is operating normally, a completion report or an error report is sent to EPU1, the processing steps proceed normally, and recovery processing for the error is performed.

However, if the microprogram routine running inside l0PB stops, the above-mentioned completion report or error report cannot be made to EPU1,
For this reason, in the conventional example, as described above, there is a possibility that the operation of the entire system will be seriously affected.

In this embodiment, this problem is avoided as follows.

As shown in FIG. 2, each l0P3 is provided with a status register 34, and the current status of this l0P3 is registered in this register. One of the pieces of information in this status register 34 is information that is used when the microprogram running in the microprogram execution section 31 stops or enters an abnormal loop and is no longer able to operate normally. Contains microprogram run abnormality pits.

Each l0P3 is further provided with a processor identifier 35 in which information for identifying each sub-processor is registered. The contents of the processor identifier 35 and the status register 34 are configured to be transferred to the 5VP4 via the diagnostic bus control section 33 and the diagnostic bus 200 independently of the operation of the microprogram execution control section 31. .

Now, in 5VP4, as shown in FIG. The contents of the identifier 35 and the contents of the status register 34 from each of the above-mentioned sub-processors are checked. When the diagnostic microprogram routine identifies from the microprogram run abnormality pits in the status register 34 that a particular l0P3 is causing an abnormality in the program run,
This specific IOP3 is identified from the contents of the identifier 35, the entire error status is edited from the contents of the status register 34 instead of this IOP3, and this is sent to the EPt via the system bus control unit 42 and the system bus 100.
Report to Jl.

As a result, the EPU 1 software can receive failure reports even in this case, and can provide information on the occurrence of failures.
For example, when 0P3 that is able to recognize 0P3 and issues 110 instructions causes such a failure, the I
By forcing the 10 instructions to terminate, the software sequence can proceed.

As described above, according to the two embodiments, even if a failure occurs in the microprogram in 10P3 and it is no longer possible to report an error, 5VP4 identifies this and reports the error in place of the failed 10P3. , it is possible to avoid serious system failures.

Note that the above description shows one embodiment of the present invention, and the present invention is not limited thereto.

For example, in the above embodiment, the input/output control device (IO
Although the number of P3) is set to 2, it does not need to be limited to 2.

In addition, when these subprocessors stall, not only for the input/output side@device but also for any subprocessor that operates with a microprogram in the system, the diagnostic processor can detect the stalled subprocessor using the same method. It can also be configured to report errors on behalf of the processor.

(Effects of the Invention) As described above, according to the present invention, in a data processing device having a configuration in which a plurality of microprogram type subprocessors including a diagnostic processor are connected to a common system bus and a diagnostic bus, The diagnostic processor reads the entire contents of the identifier and status register of each sub-processor via the diagnostic bus, thereby identifying a fault in the microprogram of each sub-processor or reading the contents of this status register. When the diagnostic processor identifies that the corresponding subprocessor is in a state where it cannot report an error due to a fault, the diagnostic processor takes control of the entire system via the system bus on behalf of the faulty subprocessor. It becomes possible to report errors to the software of the arithmetic device. This makes it possible to recognize the subprocessor in which a failure has occurred; for example, when the subprocessor issuing the I10 instruction stalls, it is possible to proceed with the software sequence by forcibly terminating the I10 instruction. It is possible to recover the faulty processor by logically isolating the faulty subprocessor and performing degenerate operation, or by issuing an initialization command to the faulty subprocessor.

, This makes it possible to provide a highly reliable error reporting method in a microprogram-controlled data processing device.

[Brief explanation of drawings]

The first factor is a block diagram showing one embodiment of the present invention, FIG. 2 is a diagram showing the configuration of the input/output control device of this embodiment, and FIG. 3 is a diagram showing the configuration of the diagnostic gross length of this embodiment. be. In the figure, 1... Arithmetic processing unit @ (EPU),
2... Main memory @ (MMtJ), 3-1.
3-2... Input/output control device (IOP), 4...
...Diagnostic grosser (8VP) + 5-1 to 5-
N-.-I/O device 1l (DEV). 31.41...Microprogram execution side (incorporated) department, 32.42...System bus system 6i11
L 33, 43... Diagnostic Bus System (Foundation) Department, 3
4...Status register, 35...
Processor m brush, 100...System bus, 200...Diagnostic bus. Doa Gana 2 figures Atsushi, 3 figures

Claims (1)

[Scope of Claims] A data processing device configured such that a plurality of microprogram-controlled subprocessors including a diagnostic gross processor are connected to a common system bus and a diagnostic bus, wherein the diagnostic processor connects the diagnostic processor to a common system bus and a diagnostic bus. means for detecting an abnormal state of each of the sub-processors by reading an identifier and a status register of each of the sub-processors connected to the bus; When the diagnostic grosser uses the means to diagnose that the faulty sub-processor is in a state where it is unable to report an error, the error report is executed via the common system bus on behalf of the faulty sub-processor. An error reporting method characterized by: