JPH02244252A - One-chip multiprocessor containing bus arbiter and comparator - Google Patents

Abstract

PURPOSE:To prevent the deterioration of the overall performance due to the frequency conflicts of memory accesses due to the increase of processors by providing with a memory access arbitration means which is connected to each processor and a connection pad for the outside of a chip. CONSTITUTION:An n-to-1 selector 8 collects and selects the signals for external accesses from (n) pieces of processors 200a to 200d. An arbitration means 210 collects the external access requests from processors 200a to 200d and selects only one external request based on the priority. Then the selector 8 is controlled based on the result of the means 210 and the processor identification numbers are added at the out-of-chip accesses. Then these processor identification numbers are sent back from an external device upon response for decision of the access originator processors 200a to 200d. Thus a 1-chip multiprocessor arbitrates the external accesses given simultaneously from the processors 200a to 200d. Then the access of only one processor can be outputted to outside.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a single chip in which a plurality of processors are integrated on one chip.
The present invention relates to a chip multiprocessor, and particularly to a method suitable for efficiently performing memory access and a method suitable for realizing a one-chip processor with high data reliability.

[Conventional technology]

General approaches to increasing computer performance include increasing the speed of a single processor and increasing overall throughput by performing parallel processing using multiple processors. The former has achieved remarkable results due to the development of device technology, but in recent years, the speed-up of devices has been approaching its limit, and we are now in a situation where it is no longer possible to expect the same results as before. On the other hand, although conventional methods have been recognized as effective, they have only been applied to limited fields such as top-of-the-line general-purpose large-scale computers, partly because the processors are expensive.

However, with the development of microelectronics represented by VLSI technology, the cost of processors has become extremely low, and multiprocessors have become an effective means of improving computer performance from a cost standpoint.

Furthermore, as the degree of integration increases from VLS i to ULS i, it is easy for anyone skilled in the art to realize that by incorporating multiple processors or multiple arithmetic units into one chip, it is possible to realize a computer with higher performance and lower cost. Predictable.

As a publicly known example based on this idea, Japanese Patent Application Laid-Open No. 62-15
No. 2064 and JP-A-62-221062. In known examples, the basic idea of a one-chip multiprocessor has been presented, but no consideration has been given to how to efficiently perform memory access, which is always a problem in processors. That is, in the known example, when memory accesses from two processors conflict, an arbiter transmits the memory access from one processor to the outside of the chip and issues a processor hold signal to the other processor. After one memory access is completed, the hold signal is dropped and the other memory access is started. In this method, if the number of processors increases and memory access conflicts occur frequently, processor hold states may increase and overall performance may drop.

On the other hand, as the level of integration increases, the wiring width within LSi becomes narrower, making it more likely to break due to aging, or the contents of flip-flops becoming more likely to be reversed due to disturbances such as alpha rays.

As a result, errors occur in the calculated data, reducing data reliability. To solve this problem, large-scale computers have adopted a method of adding a parity bit to data and checking this to detect data errors at an early stage. However, this method causes a delay in the calculation path, which is not desirable for improving the performance of the processor.Therefore, in highly integrated processors, data errors are detected using another method to ensure data reliability. There is a need to.

[Problem to be solved by the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for arbitrating when external accesses from a plurality of processors occur simultaneously in a one-chip multiprocessor and outputting accesses from only one processor to the outside.

Another object of the present invention is to provide a method in which each processor can handle interrupts simultaneously in a one-chip multiprocessor.

Another object of the present invention is to output external accesses from multiple processors to the outside in a pipeline manner in a one-chip multiprocessor, and to know which processor has responded to the access. The purpose is to provide a method that can be used.

Another object of the present invention is to compare external accesses from each processor in a one-chip multiprocessor, and access outside the chip only when they match, thereby ensuring high reliability and preventing external accesses due to incorrect data. The aim is to provide processors for

Another object of the present invention is to compare external accesses from each processor in a one-chip multiprocessor, and if there is a discrepancy, stop the operation of the processor to ensure high reliability and prevent incorrect operation from continuing. The aim is to provide processors for

[Means to solve the problem]

The above purpose is to collect and select signals related to external access (eg address/data) from n processors.

An n to 1 selector and an arbitration means that collects external access requests from each processor and selects only one external request according to the priority of the processor are provided, and the selector is controlled according to the result of the arbitration means, and external access requests from outside the chip are controlled. This is achieved by adding the processor identification number when accessing the system, and having the processor return the processor identification number together with the response from the Masube device to determine the accessing processor.

Another purpose is to synchronize external access requests of the processor with signals related to external access (e.g. address/
A comparator is provided to compare the data).
This is achieved by providing a gate that outputs a signal related to external access and an external access request to an off-chip input/output bin only when the output of the comparator is positive.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is an overall configuration diagram of a multiprocessor computer. 1a is a processor element (hereinafter abbreviated as PE), which is composed of one or more microprocessors. 2a is a memory control unit (hereinafter abbreviated as MCU), and a signal line 9a
It performs address conversion, etc. of the logical address passed from PE1a to a physical address via the PE1a. 3a is a memory device (hereinafter abbreviated as MS), which stores instructions and data to be executed by the processor. 10a is a signal line that transmits address and data to MS3a.

lb, lc, and ld are processor elements of the same or different type as PE1a. 2b.

2c and 2d are memory control devices of the same or different type as the MCU 2a. 31), 3c, 3d are M S
It is the same or different type of memory device as 3a. Further, 4 is a shared memory device (hereinafter abbreviated as GM).

5 is an input/output device (hereinafter abbreviated as I10), which generally includes a disk device, a display, a keyboard, etc., but since they are not directly related to the present invention, they are shown together. Reference numeral 6 denotes an interrupt distribution device (hereinafter abbreviated as DIST) that distributes the interrupt signal 12 from the device 105 via the signal line 8. 7 is connected to each PE comrade or 0M4.7 through the MCU. This is a communication bus (hereinafter abbreviated as COMBUS) that connects 1105 and DIST6. In this example, COM
[1US7 is a bus consisting of memory address lines, data lines, and control signal lines, but it is possible to replace it with a network using metal or optical fiber. 8 collectively shows individual interrupt signal lines for each PE. 9a, 10a, and lla are signal lines mainly including address, data, and control lines *9b, 9c
, 9d and 10b, 10c.

10d, llb, llc, and lid are each 9a.

This is a signal line having the same or equivalent function as 10a and lla.

FIG. 2 shows the internal structure of PE1a.

1a, lb, lc, and ld have the same structure.

200a, 200b, 200c, and 200d are microprocessors, which read instructions from the memory 3a, etc., and execute the instructions. The signal line 220a is an external interface line for the processor 200a, and is an address/
Contains data lines and other control lines, and includes signal lines 230
A is a 3-bit interrupt signal line having an interrupt level.

These signal lines can be considered to be the same signal lines as, for example, the microprocessor MC68020 manufactured by Motorola, USA, 220b.

220c and 220d are the same as 220a and 200
b, 200c, and 200d are the same as 200a.

210 is 220a, 220b, 220c.

This is an arbitration circuit for external access performed via the signal line 9a, and only accesses from one processor are made via the signal line 9a.
It also has the function of distributing the response from 9a to any processor.

FIG. 3 shows the configuration of the general-purpose register set of processor 200a. Although the general-purpose register set consists of 16 registers with a width of 32 bits, the bit width of the registers and the number of registers are not essential issues in implementing the present invention. FIG. 4 shows the configuration of the program status word (psw) and processor identification register of processor 200a. 310 is the system status word (S
SW), S is a bit that indicates whether the processor is in system (also called supervisor, or privileged) mode or user mode; when it is 1, it is system mode, and when it is O, it is user mode. Indicates the mode. L2°Ll, LO is a code indicating the interrupt mask level; when all 0, it indicates the lowest mask level, and when all 1, it indicates the highest mask level. 311
is a condition code that indicates the operation status when the instruction is executed. 312 is a program counter (pc) indicating the address of the next instruction to be executed;
3 is a register (PID) that holds a processor element identification number indicating the PE number in FIG. 1, and is automatically set by the hardware and cannot be rewritten by a command. 314 is a register PNUM that holds a processor number for uniquely determining the processor in the PE, and is determined at the time of manufacturing the PE.
It cannot be rewritten by command.

FIG. 5 shows the internal configuration of external access arbitration circuit 210 of FIG. 2. 24o is each processor 20
External access requests 224a, 224b from 0a, 200b, 200c, 200d.

It is a startup arbiter that arbitrates between 224c and 224d, and the arbitration result is output from signal 1iA 217, and the access information (address/data, etc.) of a certain processor is output according to this.
is selected by the selector 250 and output from the signal line 215 to the outside. At this time, the number of the selected processor and the request signal are outputted via the signal line 216.

260 is a response distribution circuit that distributes a response to an external access to the accessing processor.

A response signal (DACK) 212 is used as a response signal from the outside.
, bus error signal (BERR) 213, 2-bit access source processor number (SPNUM) 211 is included, and DACK 212 and BE
RR213 to each processor as a signal llA221a.

221b, 221c, and 221d.

270 is a buffer that temporarily stores external read data sent via the signal line 214, and this read data is sent to the signal lines 222a and 222b.

222c, 222d to all processors. Next, each part of the external access arbitration circuit will be explained in detail.

First, FIG. 6 shows an example of the configuration of the startup arbiter 240. The arbiter is generally called a round-tropin system, and the priority order of the processors changes sequentially. External access request signal 224a from processor 200a
is the 2-bit processor number 2241a and the request signal 2
242a, and selectors 242a and 242a, respectively.
42b.

242c, 242d and priority encoder 241
'a, 241b, 241c, and 241d. Other processors 200b, 200c.

The same applies to the external access request signal from 200d. Here, selectors 242a, 242b, 242c.

242d is of the same type as 4 to 1, and includes priority encoders 241a, 241b, and 241c.

241d is also of the same type, and its operation is shown in Figure 7 (A
) as shown.

245 is a 4 to 1 selector. 246 is a register (B R) indicating the processor with the highest priority.
The priority order of the processor changes as shown in FIG. 7(B) depending on the value of BR. BR is incremented every time any processor performs an external access,
In memory accesses where the priorities change sequentially but are inseparable, for example, read and write using Te5tand Sat instructions, BR is not incremented even after the first read access occurs, and the same processor retains external access rights until the next write access. maintain. 243 is an OR gate which, when any processor requests access, transmits this to the outside via the signal line 216 and updates the BR.

Next, an example of the operation of the startup arbiter 240 will be described.

If the BR(7) value is 2 and the processors 20ob and 200d make access requests at the same time, the selector 245
The output of selector 242C is selected according to BR246. At this time, the selector 242C selects 224 according to the output (3 in this case) of the priority encoder 241c.
Select 1d.

Therefore, the signal line 216 issues an access request to the outside and also outputs the processor number 3. In addition, the selector 250
The selection signal 217 of the processor 200d also outputs 3.
Access information such as address/data from is output to the outside.

As another embodiment of the startup arbiter 240, a simple fixed priority method as shown in FIG. 8 may be considered. 8th
In the figure, the processor priorities are 200a, 200b
, 200c, and 200d, and when external access occurs frequently, there is a problem that it is difficult to assign access rights to 200d. It has the advantage of requiring less.

FIG. 9a shows the internal configuration of the response distribution circuit.

261 is a 2-bit decoder, and 262a.

262b, 262c, and 262d are buffer gates with output enable terminals, and the response distribution circuit is SPNu
Obtain the number of the processor that should return the response from M211,
Open the corresponding buffer and write DACK212 and BERR2
13 to the processor. At this time, if it is a read access, the signal lines 222a and 222b.

Read data transmitted via 222c and 222d is captured by the processor.

A time chart of access using the external access arbitration circuit 210 is shown in FIG. 9b, which shows the case where the value of BR246 is initially O.

In the T1 cycle, external access requests (reads in this case) are issued simultaneously from the PO, PL, and P3 processors, but the activation arbiter 240 selects the access of Po and outputs the address ADRO to the outside. In the T2 cycle, the value of BR246 is 1, arbitration is performed again between Pl and P3, and access of Pl is selected.
Address ADR1 is output to the outside.

Next, an embodiment of the memory control device i2a will be shown.
A will be described, but other memory control devices 2b, 2c, 2
d can also be realized with a similar configuration.

FIG. 10 shows the internal configuration of the MCU 2a and its peripheral parts. 400 is an address conversion device that converts a logical address from a PE into a physical address, and has a function equivalent to Motorola's MC68851. 450
is a store-through type cache memory device consisting of a cache memory and its control circuit. Therefore,
When the memory access from PE1a is a write, the MS
- Writing to the memory device is performed via BUS490. 460 is a monitoring circuit for the M5-BUS 490, and anything other than the cache memory device 450 is connected to the MS-BUS 490.
When a write access is performed on the nus46o, it is detected whether the write address hits the cache memory or not. When a hit occurs, a request to invalidate the cache memory entry is transmitted to the cache memory device @450 via the signal line 465.

MS-13US490 is a cache memory device 45
The 0° memory device i3a has a bus interface device [530] as a bus master, and its address space is the same for other MS-BUS, and is allocated as shown in FIG. In Figure 11, ConnonR
The region is an area where all memory devices have the same data redundantly, and the 5hared region is an area where each memory device shares the shared space.
The data in the Global Region is an area where data is stored in the shared memory device GM4;
The register region is an area such as hardware registers mapped onto the memory space.

Local Region is an area where each memory device has individual data. Each region is divided in advance by address as shown in Figure 11, and the region is divided by decoding the upper 4 bits of the address.
Perform on detection.

500 is an area determination circuit iJ, MS-BU
Access on S490 is in Common Region
Or ShcredRegion O or Loc
al, Region, the access is transmitted to the memory device 3a.

510 is also an area determination circuit, and MS-BUS490
The above access is 5hared Region 1,
Only when writing to 2, 3, Global Region or Common Region, access is made to Com5 via Bus-Inf530.
+unication -Inform Bus 7. Also,
Com+aunication - Access on the Bus is a write to the CommonRegion or 5
For Hared Region O or 5h
Access is communicated to MS-Bus only in the case of invalidation to regions 1, 2, and 3.

550 is an export monitor that monitors whether another PE reads data from 5hared Region O and stores the data in another cache memory;
70 is a memory that stores the address of the exported data. 570 only needs to provide one export bit for each block of cache memory, so 5hared
When Region O has a capacity of 64 MB and the cache memory block size is 16 bytes,
It is sufficient to use 4 megabit memory. 55 in Figure 12
0 and 570, and FIG. 13 shows the operation of the memory controller 2.
The overall operation of a is shown.

In Figure 13, Access 5source indicates whether access to 2a is from PEO or Commun.
It shows whether it is from another PE via i-cation-Bus.

Access Region indicates where the access target area is, Inner 5hared is SharedRegion O, and Inner 5hared is SharedRegion O.
5hared is 5hared Regionl, 2.3
means. Cache hit indicates whether the data to be accessed exists in the cache memory. Migration indicates whether the migration bit of the block to which the access target data belongs is on or off. Memory Access indicates what kind of (read/write) access is generated to which area of the memory device [3a] by the access. Cache Access determines what kind of (read/read) operations are performed on the cache memory by the access.
6 Com, Access indicates whether a write/invalidation) access is to be generated.
Communication - This shows what kind of access is generated to Bus 7.

Next, the interrupt distribution device DIsT6 will be explained. 1st
Figure 4 (A) shows the configuration of DIST6.

Status registers 7101a, 7011a, and 7013d indicate the interrupt permission state of the processor, and are allocated to Register Regions in the memory space, and their configuration is as shown in (B). i is a bit indicating whether or not the processor is in an idle state waiting for an executable processor to be generated; when it is 1, it indicates an idle state. L2. Ll.

LO is an interrupt mask level, and L2.LO in 310 in FIG. The operating system controls it so that it is the same as Ll and LO.

800 is a 3-bit interrupt with a level input from the signal line 12 (000 is no interrupt, 111 is the highest level interrupt) Processor to which an interrupt should be inserted based on the processor status stored in 7010a to 7013d It is a distributor that determines the FIG. 15 shows the configuration of the distributor 800. 8100.8115 compares the interrupt mask level of each processor and the interrupt level from Ilo, and when (input A)≦(input B), output C turns on (set to 1), 8700.8701° 8715 is a 2-bit buffer with an output enable; for example, when the enable signal 860 is turned on, the interrupt level EINT (2-0) is output to INT (2-0) and transmitted to the processor.

In this embodiment, the processor with the highest interrupt priority is
This is the processor with the lowest processor number among the processor elements with the lowest processor identification number in an idle state. When there is no idle processor, the interrupt mask PSTi (2-0) is smaller than the interrupt level EINT (2-0), and the processor has the smallest processor number among the processor elements with the smallest processor identification number.

Next, another embodiment is shown. FIG. 16 shows another configuration of the processor element, and 900 is a processor 200.
This is a comparison means for comparing external access information 220a and 220b of a and 200b.

Reference numeral 910 is an error signal line that is turned on when the comparison result is a mismatch. When the error signal 910 is turned on, the processors 200a and 200b transition to a stopped state and do not perform any further external access. FIG. 17 shows details of the comparison means. 901 is a comparator, 220a, 2
When all addresses/data included in 20b match, 903 turns on.

902 is a buffer with output enable.

The processors 200c and 200b are initialized by means not shown and start executing instructions from exactly the same state. At this time, the processor 200a is a mask, and in the case of memory read, the data accessed by the processor 200a is supplied to the processor 200b. Also, interrupts are 200a, 2
00b at the same time.

In this embodiment, the operation when a mismatch occurs in the external access information is as follows.

When the processor 200a performs a memory write, it turns on the memory access request 224a and sends an address/data etc. to the external access information 223a. At this time, comparator 901 checks whether 223a and 223b completely match, and turns off 903 if they do not match. As a result, the memory access request 216 is turned off, and the erroneous external access information 223a is not sent to the outside.

Furthermore, the error signal 910 is turned on to notify the outside of the occurrence of the mismatch and to transition the processors 200a and 200b to a stopped state.

〔Effect of the invention〕

In addition, by adding a processor number to each processor's external access, it is possible to know which processor the response from the outside is directed to, so it is necessary to retain access information such as address/data until the external access is completed. This has the effect of increasing the throughput of external access.

Further, according to the present application, even if an error such as bit inversion occurs in data inside the chip, the erroneous data will not be output to the outside, so a processor with high data reliability can be realized.

[Brief explanation of drawings]

Figure 1 is an overall configuration diagram of a multiprocessor system using a 1-chip multiprocessor, Figure 2 is a diagram of the configuration inside 1 chip, Figure 3 is the general-purpose register of each processor, and Figure 4 is the PSW and processor of each processor. Figure 5 is a configuration diagram of the fill register, Figure 5 is a configuration diagram of the external access arbitration circuit, Figure 6 is a configuration diagram of the startup arbiter, Figure 7 is a diagram showing the operation of the startup arbiter, and Figure 8 is another configuration of the startup arbiter. 9a is a configuration diagram of the response distribution circuit, FIG. 9b is an example of an external bus cycle of a processor element, FIG. 10 is a configuration diagram of a memory control device, and FIG. 11 is a diagram showing the physical address space allocation. Figure 12 is a diagram showing the operation of the export monitor, Figure 13 is a diagram showing the operation of the export monitor.
14 is a diagram showing the operation of the memory control device, FIG. 14 is a configuration diagram of the interrupt distribution circuit, FIG. 15 is a detailed diagram of the interrupt distribution unit, FIG. 16 is a diagram showing the configuration of the processor element, and FIG.
The figure is a diagram showing details of the comparison means. 1a... Processor element, 2a... Memory control device, 3a... Distributed shared memory, 4... Shared memory, 5... Peripheral device group, 6... Interrupt distribution device, 8.
...Interrupt line, 12...Interrupt line, 200a...
・Processor. 210... External address arbitration circuit, 216... External access request signal, 215... External access information (memory address, data, etc.), 241a... Priority encoder, 400... Address Conversion device, 550... Export monitor, 570... Memory for retaining export data, 510... Area determination circuit, 70
10a... Processor status register on memory space, 8100... Size comparator. Figure DETAII, OF R Figure (A) DETAIL 0F PS"8' (B) ead n1y DETAIL 0F PID REG FA) Figure Figure 9a Figure Figure Figure Access on the Bus is from + Bus-Inf Access on REIT\Is,, Jus or write from Cache Same PSTR configuration as in previous section B Fig. 13 PE B Bus-1nf Read Wr it it e it 1ss RD Read WT

Claims (1)

[Claims] 1. Reading an instruction from a memory device storing the instruction,
In a one-chip multiprocessor in which a plurality of processors that execute the instructions are integrated on the same silicon chip, memory access arbitration means is provided that is connected to each of the processors and a connection pad to the outside of the chip, and the memory access The arbitration means includes a startup arbiter that accepts only a request from a unique processor based on memory access request signals from each processor, and a startup arbiter that receives memory access information from each processor according to the output of the startup arbiter. Each processor is given a unique processor number, including a selector that selects a specified item and transmits it to a connection pad outside the chip, and memory access information sent from each processor includes a selector that selects a specified item and transmits it to a connection pad outside the chip. A one-chip multiprocessor characterized in that a number is included, and the memory access information output from the memory access arbitration means also includes information on the processor number. 2. The one-chip multiprocessor according to claim 1, wherein the memory access arbitration means, after transmitting the memory access information to the outside of the chip, performs the next arbitration without waiting for a response to the memory access. 3. Read the instructions from the memory device that stores the instructions,
In a single-chip multiprocessor in which a plurality of processors that execute the instructions are integrated on the same silicon chip, each processor uses the processor number uniquely determined for each processor as memory access information when accessing the memory. A one-chip multiprocessor characterized in that the processor number is added and the processor number is also added when the one-chip multiprocessor accesses the memory device. 4. Read the instructions from the memory device that stores the instructions,
In a one-chip multiprocessor in which a plurality of processors that execute the instructions are integrated on the same silicon chip, the first
a comparison means connected to the processor and the second processor, and the means is configured to compare the memory access information transmitted by the second processor when the first processor performs a memory access while transmitting first memory access information to the memory. A one-chip multiprocessor characterized in that the first memory access information is not sent to the outside of the chip when the first and second memory access information are different. 5. The one-chip multiprocessor according to claim 5, wherein if the comparison results are different, the first and second processors are brought to a halt state. 6. Read the instructions from the memory device that stores the instructions,
In a one-chip multiprocessor in which a plurality of processors that execute the instructions are integrated on the same silicon chip, each processor has an independent interrupt line, and each processor independently processes interrupts. 1 chip multiprocessor.