JPH0823991B2 - Address signal reproduction method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION A. Field of Industrial Application The present invention is applied to the beginning of each block of a recording medium in which a recording area is divided into a plurality of blocks such as an optical disk and an optical card. The present invention relates to a method for reproducing an address signal such as a recorded sector address.

B. Summary of the Invention The present invention is a method of reproducing an address signal recorded for each block in a recording medium divided into a plurality of blocks, and estimates the address of the current block by calculation based on the previously read reference address. Then, the set of the error detection or correction code and the estimated address obtained by encoding the estimated address is simply compared with the set of the address and the error detection or correction code of the actually read current block, and this comparison is performed. By determining that the estimated address signal is valid according to the result and outputting it, it is possible to perform highly reliable address reproduction without omitting unnecessary signal processing, for example, error correction processing, and it is necessary for decoding processing. This is to simplify the hardware configuration.

C. Conventional Technology In general, a disc-shaped optical recording medium such as an optical disc or a magneto-optical disc has concentric or spiral (spiral) tracks, and one track is divided into a plurality of sectors. There is. Further, in a card-shaped recording medium such as an optical card, for example, a band-shaped recording area is divided into a plurality of recording tracks. Each predetermined position of each recording block such as each sector or each recording track,
For example, at each head position, a so-called identification process including a synchronization pattern, an address, a CRC error detection code, etc. is performed by a so-called formatting process before starting the use of a new disc or a so-called pre-formatting process on the side of the disc or card supplier. The signal is recorded. The address information of the identification signal allows random access to the recorded data.

The identification portion of each block (sector or the like) in which this identification signal is recorded is also called an ID portion or a broadly defined address portion. For example, in an optical disc, a CRC error detection code is added to the track address and sector address. A recording unit (1 unit) of the address information is recorded in multiple writing (for example, triple writing).

D. Problems to be Solved by the Invention By the way, in such a conventional identification signal recording mode, an error detection code such as CRC has been conventionally used as an error code. It has also been proposed to add an error correction code so that it can be dealt with at times. At the time of disc access accompanying signal recording / reproduction, the operation of controlling the movement of the pickup head while reproducing the identification signal and confirming the current address is always performed. Alternatively, decoding processing such as error correction is always executed. For this reason, the signal processing at the time of address reproduction becomes complicated, and especially when multiple writing such as the above-mentioned triple writing is performed, an error check or error correction is performed on all the respective parts, and then the address by the majority logic is applied. Since the determination process must be performed, the decoding algorithm and hardware become complicated, the time required for the arithmetic processing and the like becomes long, and there is a possibility that it will be an obstacle to high-speed access.

The present invention has been made in view of such circumstances, and address reproduction can be realized with high reliability without performing decoding processing such as error detection and error correction, and the hardware configuration required for decoding is simplified. It is an object of the present invention to provide an address signal reproducing method that can be realized.

E. Means for Solving Problems In order to solve the above-mentioned problems, the address signal reproducing method according to the present invention is arranged at a predetermined position of each block in a recording medium divided into blocks such as a plurality of sectors. In a method of reproducing an address signal recorded in a form having redundancy to which an error detection or correction code is added, in a fixed position with respect to a block of a reference block address which is read and fixed from the recording medium in advance. When reproducing the address of the current position block having a relationship, the estimated address of the current position block is calculated based on the reference block address and the fixed positional relationship, and the estimated address is encoded in advance to detect an error detection or correction code. Then, the set of these estimated address and error detection or correction code and the current position block are actually obtained. A characteristic is that the estimated address is output as a valid address when these two pairs match within a certain condition, by simply comparing the obtained address and the pair of error detection or correction codes. I am trying.

F. Action By extremely simple signal processing that simply compares the estimated address of the block currently being reproduced and the error detection or correction code obtained by encoding with the actually reproduced address and error detection or correction code , Reliable address reproduction can be performed in a short time.

C. Embodiment FIG. 1 is a diagram for explaining an embodiment of the address signal reproducing method of the present invention. In FIG. 1, an optical pickup head 2 reproduces at least a signal from an optical disc 1 as an example of a recording medium. A signal from the optical pickup head 2 is sent to a signal reading circuit, a so-called reader 3, to be a digital signal, and an identification signal portion (reproduction address AD _PB and error detection or correction code ECC) of the read digital signal. _PB ) is sent to the comparison circuit 5. In the comparison circuit 5, the address (estimated address) AD _es of the block (sector) currently being reproduced, which is estimated by the calculation processing based on the reference address AD _re previously read from the disc 1 and confirmed, and this estimated address AD _es to ECC encoder 9
Encoding process (error detection or correction coding process)
The error detection or correction code ECC _es obtained by the above is supplied. In the comparison circuit 5, these reproduction addresses AD _PB
And the above code ECC _PB , the estimated address AD _es and the above code E
C _{C es} is simply compared (for example, bit by bit), and when they match within a predetermined allowable range, the address is validated.

By the way, as a specific example of the signal recording format in the sector which constitutes one block on the optical disc 1,
For example, the one shown in FIG. 2 has been proposed. In FIG. 2, one track on the optical disk 1 is linearly stretched, and the identification section of one sector (so-called ID
Part) is schematically illustrated in an enlarged manner. One track is composed of a plurality of sectors, and one sector includes, for example, a preformatted identification part IDR and a data part DTR as an area in which general sector data is recorded. And consists of. Identification part I
The clock at the beginning of DR is used for clock generation when reading data.
The synchronization signal (PLO sync) PLOS recording section for stabilizing the operation of the PLL circuit, etc. is arranged at the head, and this synchronization signal PLOS
The unit UT, which is one recording unit of the sector identification address information, is arranged so as to be triple-written in succession to the recording section of. That is, three units UT1, UT2, UT3, which are recording units of sector identification address information having the same content, are sequentially arranged following the synchronization signal PLOS, and each recording unit unit UT has a sync pattern address mark at the beginning. SPA is arranged, address AD composed of track address TA and sector address SA is arranged, and then CRC error detection code or error correction code ECC composed of, for example, BCH code is arranged. Here, as an example of the number of bits of each part, 16 bits of the track address TA and 8 bits of the sector address SA make an address AD of 24 bits in total, and the length of the error detection or correction code ECC is It is 24 bits, which is equal to the total data.

When reproducing the address signal by reading the identification section (ID section) of each sector in such a recording form, conventionally, each address AD of each unit UT1 to UT3 is detected by an error detection or correction code ECC or After correction processing, valid ones of these processed address values are compared with each other, and if these effective address values are different, the majority agreement address value (3
In the case of double writing, two of the three address values are the same). However, in such a method, the current address cannot be determined until all the addresses of the multiple-written units are decoded and compared, and the decoding process is continuously required for each of the multiple-written units. The burden on the hardware is also heavy.

Therefore, in the present embodiment, the sector currently being reproduced by the optical pivic head 2 is read based on the address AD _re of the sector which is read out from the optical disc 1 and whose reliability is ensured by the decoding process or the like. The address of this is estimated by calculation, and the estimated address AD _{es of} this current sector
Error detection or correction code ECC _es
Then, the set of the estimated address AD _es and the code ECC _es is sent to the comparison circuit 5, and is simply compared with the set of the reproduction address AD _PB and the error detection or correction code ECC _PB obtained by actual reproduction. I am trying.

This will be described in more detail with reference to FIGS. 1 and 3. Here, FIG. 3 shows, for example, a plurality of sectors SEC ₁ , SEC ₂ , SEC ₃ ...
-Shows each of these sectors SEC ₁ , SEC ₂ , SEC ₃
.. are designated as AD ₁ , AD ₂ , AD ₃ ... And corresponding error correction codes are designated as ECC ₁ , ECC ₂ , ECC ₃ ... In FIG. 3, the address of each sector and the error correction code are shown in a single write state for the sake of simplification of description, but they may be written in multiples. Further, instead of the error correction code, an error may be written. A detection code may be used.

First, with respect to the reference address AD _re , the reader 3 of FIG. ₁ reads the address AD ₁ of an arbitrary sector, for example, the sector SEC ₁ of FIG. 3, and the ECC decoder 6 performs a decoding process using the error correction code ECC _1. Thus, a highly reliable reference address AD _re is obtained and sent to the present address operation circuit (or present address estimation circuit) 8 via the selected terminal b of the changeover switch 7. Next, when reproducing the address of a sector SEC ₂ continuous to the sector, the current address calculation in the arithmetic circuit 8 an address of the sector SEC ₂ currently playing on the basis of the address AD _re serving as the reference example AD _re +1 The error correction code ECC _es is added in advance by being obtained (estimated) by being sent to the ECC encoder 9 and subjected to error correction coding processing (encoding processing), and in the comparison circuit 5, the estimated current address AD _es ( = AD _re +1) and code ECC _es
And the set of the current address AD ₂ and the error correction code ECC _{2 which} are actually reproduced. When these two sets of address and code match within a predetermined allowable range, the comparison circuit 5 sends a match output from the output terminal 11.
In response to this coincidence output, the address output from the current address operation circuit 8 is output as a valid address via the terminal 13. The effective address output from the output terminal 13 is, for example, via the input terminal 16 the selected terminal a of the changeover switch 7.
And is sent to the present address operation circuit 8 as the reference address for reproducing the address of the next sector.

Here, the arithmetic processing for estimating the present address in the present address arithmetic circuit 8 will be explained. When the address signals are reproduced from the consecutive sectors one by one as described above, the sector synchronization pulse from the optical pickup head or Each time the sector count signal based on the disk rotation detection pulse, etc. is supplied to the input terminal 17, the input terminal
The estimated address AD _es may be calculated by adding the addition data “1” from 18 to the reference address AD _re . Also,
When the address signal is reproduced for each of two or more sectors, for example, every n sectors, the addition data of the input terminal 18 is set to "n", the addition operation is performed every time n sectors are counted, and the estimated address is sent to the comparison circuit 5. You can do this.

Next, the comparison operation in the comparison circuit 5 is a simple comparison for each bit, and among the total of 48 bits of the address 24 bits and the error correction code 24 bits as in the example of FIG. When the number of a is within a (for example, a = 4), it is determined that the block (sector) being reproduced and reproduced is the block of the target address AD _t .
That is, it is determined whether or not they match with each other by using the number of bits a as a so-called allowable range or threshold value. That is, if a 24-bit BCH code is used as the error correction code ECC, the inter-code distance is 12
Since the error correction capability is 5, the error within, for example, a = 4 bits can be completely corrected, and the corrected result matches the estimated address. Therefore, the reproduction address can be confirmed with the same high reliability as when the decoding process is performed, without performing the decoding process that generally requires a complicated algorithm and a heavy hardware load.

Next, when an address and an error correction (or detection) code are multiple-written in the identification part of one sector, the address and the error correction code of each multiple-written unit are sequentially used as the estimated address and code. After simple comparison, the valid address is immediately output when the above-mentioned coincidence is detected without taking the above-described decoding process or majority decision. That is, even in the case of a multiple-written address, if the reproduction address and code of the first unit match the estimated address and code, the current address is determined without reproducing the remaining units.

According to the address signal reproducing method as described above, the decoding process and the majority decision process for the reproduced address data are unnecessary, so that the hardware configuration can be simplified and the processing time can be shortened.

It should be noted that the present invention is not limited to the above-described embodiment, and for example, k (k ≦ k) units out of n-folded addresses and units closer to the error detection or correction code.
n) When the above reproduction address and code match the estimated address and code, a comparison process may be performed to output the valid address. In this case as well, it is not necessary to wait until all the n-overwritten units are reproduced, and when k reproduced units match the estimated address and code, it is immediately determined to be a valid address and the output is output. You can do it.

Further, an allowable range or a threshold value (threshold) at the time of seeing the coincidence may be made different at the time of reproducing (reading) the signal to the disc and at the time of recording (writing). For example, when the threshold value is set to a when reproducing (reading) a signal, the threshold value b when recording (writing) a signal is set to the threshold value a.
(B <a), that is, the allowable range is narrowed and the matching condition is stricter. This is because there is a request to read data even if the address is difficult to read because the data has already been written when the signal is reproduced, whereas the block (sector) where the address is difficult to read when the signal is recorded. It is better to avoid writing data to. Note that specific examples of the above threshold include a = 4, b = 1 and the like.

H. Effect of the Invention According to the address signal reproducing method of the present invention, the address of the block (sector, etc.) currently being reproduced is estimated based on the reference address that has been previously read and confirmed, and the estimated address is encoded. By simply comparing the address with error detection or correction code with the actually reproduced address and error detection or correction code, address signal reproduction can be realized by simple signal processing without degrading reliability. The wear configuration can also be simplified.

[Brief description of drawings]

FIG. 1 is a block diagram showing an example of a circuit configuration for explaining an embodiment of the present invention, FIG. 2 is a diagram showing a signal recording format on an optical disk reproduced by the embodiment, and FIG. 3 is an optical disk. 4 is a schematic diagram showing each address and error correction code of consecutive sectors of FIG. 1 ... Optical disc 2 ... Optical pickup head 3 ... Reader 5 ... Comparison circuit 6 ... ECC decoder 8 ... Current address operation circuit (estimation circuit) 9 ... ECC encoder

Claims (1)

[Claims] 1. A method of reproducing an address signal recorded in a form in which an error detection or correction code is added to a predetermined position of each block of a recording medium in which a recording area is divided into a plurality of blocks. Calculated based on the reference block address and the fixed positional relationship when reproducing the address of the current position block that has a fixed positional relationship with the block of the reference block address read and determined from the recording medium. The set of the estimated address of the current position block and the error detection or correction code obtained by encoding the estimated address is simply the set of the address obtained by reading the current position block and the error detection or correction code. By comparing, two sets of these address and error detection or correction code are combined within a certain condition. An address signal reproducing method, characterized in that the estimated address is output as a valid address when a match occurs.