JPS62295274A - Address access method - Google Patents

Abstract

PURPOSE:To shorten processing time and to attain high speed access by comparing an object address with an address subjected to an address of n-multiple write in a block during reproduction at present one by one sequentially and using the block during reproduction at present as object address block for accessing. CONSTITUTION:In accessing a block of a desired object address to a recording medium where it is split into plural blocks and an address, an error detection or correction code are recorded by n-multiple write (n is an integer over 2), the reproduced n-multiple write address is read sequentially, compared with an object address and when the coincidence is detected, the block during reproduction at present is used as the block of the object address. Thus, the error correction decode processing is simplified without lowering the reliability and the processing time is shortend.

Description

Detailed Description of the Invention 3. Detailed Description of the Invention A. Industrial Application Field The present invention is applicable to a recording medium such as an optical disk or an optical card in which a recording area is divided into blocks such as a plurality of sectors. The present invention relates to an address access method for accessing a block of desired target addresses.

B0 Summary of the Invention The present invention provides a recording medium that is divided into a plurality of blocks and recorded with n-fold addresses and error detection or correction codes written in each block (n is an integer of 2 or more). When accessing a block of addresses, read the reproduced n1♂ address sequentially, compare it successively with the target address, and immediately access the block currently being reproduced as the target address O block when defeat is detected. Accordingly, for example, error correction decoding processing can be simplified and processing time can be shortened without reducing reliability.

C0 Conventional technology = I'l, concentric or spiral tracks are formed on disk-shaped optical recording media such as optical disks and magneto-optical disks, and one track has multiple sectors. It is divided.

In addition, in card-shaped recording media such as optical cards, for example, Obi-joki! ! The area is divided into multiple recording tracks. Each predetermined position of each recording block such as each sector or each recording track, for example, each start position, is subjected to so-called formatting processing before the start of use of a new disc, or so-called pre-printing process performed by the disc or card supplier. Synchronization patterns, addresses,
A so-called identification signal including a CRC error detection code and the like is recorded. The address information of such an identification signal allows random access to recorded data.

The identification section in which the identification signal for each block (sector, etc.) is recorded is also called an ID section or an address section in a broad sense.For example, in an optical disc, a CRC error detection code is attached to an address consisting of a track address and a sector address. One weight (one unit) of the identification information to which is added is recorded in multiple writing (for example, triple writing).

D0 Problems to be Solved by the Invention Incidentally, in such conventional identification signal recording formats, error detection codes such as CRC have been used as error codes. It has also been proposed to add an error correction code to cope with the situation. When accessing a predetermined sector on the disk due to signal recording and playback, an operation is always performed to control the movement of the binocular address while reproducing the identification signal and confirming the current address. Therefore, when this address is reproduced, the above-mentioned decoding processing such as error detection or error correction is always executed. For this reason, the No. 13 process when reproducing addresses becomes complicated, and especially when multiple writing such as the above triple writing is performed, the majority vote LAEI is applied after error checking or error correction is performed for all parts. Address determination processing must be performed, and the time required for decoding calculation processing etc. becomes longer, which may impede high-speed access.

The present invention has been made in view of the above circumstances, and is capable of performing decoding processing such as error detection and error correction without deteriorating reliability when accessing a block (sector, etc.) of a desired target address. The present invention aims to provide an address access method that can simplify the process and access a block of target addresses in a relatively short time.

Means for Solving the E1 Problem In order to solve the above-mentioned problem, the address access method according to the present invention provides a method for solving the problem described above, in which a recording medium is divided into blocks such as a plurality of sectors, and each block at a predetermined position is
In the method of accessing a desired target address by reproducing an address signal recorded with n double wording (n is an integer of 2 or more) in the form of an address signal with an error detection or correction code added, Every time one of the n-overwritten addresses of the block is read one by one, it is compared with the target address, and -
The present invention is characterized in that when a loss is detected, the block currently being played back is accessed as the block at the target address without reading the remaining playback addresses of the block or comparing it with the target address.

29 Effect n Even before all of the overwritten addresses are read, the access operation can be started immediately when a match with the target address is detected for one address.
There is no need to read the remaining addresses written in nfi, such as error correction processing, and it is possible to easily shorten processing time and achieve high-speed access.

G. Embodiment FIG. 1 is a diagram for explaining an embodiment of the address access method of the present invention. In FIG. 1, signals are recorded and reproduced on an optical disk l as an example of a recording medium by an optical pick annode 2. As shown in FIG. This signal from the optical pick amplifier head 2 is sent to an address reading circuit 3, where the address of the block (sector) currently being reproduced is read. At this time, error detection using an error detection code added to the address or error correction processing using an error correction code is performed, and as a result, an address signal determined to be free of errors (no error) is sent to the comparator circuit 5. There is.

By the way, as a specific example of a signal recording formant in a sector that is one block on the optical disk 1, the one shown in FIG. 2 has been proposed. In Fig. 2, one trunk on the optical disk 1 is stretched out linearly, and the identification part (so-called ID part) of one sector is schematically shown enlarged, and one trunk is made up of multiple sectors. , one sector consists of, for example, a preformatted identification part IDR and a data part DTP as an area in which the -most sector data is recorded. In the leading value = of the identification part IDR, a recording part of a synchronization signal (PLO sink) PL○S for stabilizing the operation of the clock generation PLL circuit etc. when reading data is placed at the beginning,
Continuing to the recording part of this synchronization signal PLO3, there are 3 UNISO) UTs, which are one recording unit of sector identification address information.
It is overwritten and arranged. That is, three units UTI, UT2, and UT3 with the same content, which are recording units of sector identification address information, are sequentially arranged following the synchronization signal PLO3, and each recording unit or unit UT has a sync pattern address at the beginning. A mark SPA is placed, an address AD consisting of a track address TA and a sector address SA is placed, and then an error correction code ECC consisting of a CRC error detection code or, for example, a BCH code is placed. Here, as an example of the number of bits in each part, the address AD has a total of 24 bits, including 16 bits for the track address TA and 8 bits for the sector address SA.
The length of the error detection or correction code ECC is 24 bits, which is equal to the total address mark.

For example, when a host computer or the like records or reproduces a data signal on the optical disc 1 having sectors (blocks) in the form 1), the block ( sector) is required. In order to access the sector of this target address, conventionally, when reading the identification part (ID part) of each sector and reproducing the address signal, an error is detected in each address AD of each unit) UTI to UT3. Alternatively, those detected or corrected using the correction code ECC and determined to be no errors are compared with each other, and if these address values are different, majority logic is used to select the address value that matches the most (in the case of triple writing, the three addresses are (two of the values that fail once) are adopted as the effective address of the current position, and this effective address is compared with the above target address, and the pinocanophenod is moved so as to approach the block of the nuclear target address. System 2
■I try to do that. However, with this method, the current address cannot be determined until all of the multiplex-written addresses of each unit are decoded Q'45, and decoding processing is required continuously, which imposes a heavy burden on the hardware.

Therefore, in this embodiment, as shown in FIG.
D, is sent to the comparison circuit 5 and compared one by one with the addresses in the reproduced signal obtained from the address reading circuit 3. If a loss is found between these addresses, it is determined that it is the target address. After making a judgment, the output of the first loss is sent to the output terminal 9.

Here, FIG. 3 is a diagram for explaining the above-mentioned comparison operation, and similarly to the recording format of FIG. An example of a reproduced signal obtained by reproduction (however, synchronization signals and the like are omitted) is shown. In this Figure 3, the above unit UTI written in triplicate
, UT2, and UT3, the sets of addresses and error correction codes that make up each of ADI, ECCl, and A
D2, ECC2, AD3, and ECC5 are reproduced in this order, and first, ADI and ECC1 are subjected to decoding processing such as error correction decoding in the address reading circuit 3. When the decoding result is determined to be no error, the address signal from the address reading circuit 3 is sent to the comparison circuit 5 and compared with the target address ADt.

Here, the first unit LIT1 of the triple-written units is reproduced, and decoding processing such as error correction processing is performed to obtain a no-error address. When compared with the target address, the - When defeat is confirmed,
What is necessary is to determine that it is the above target address without performing the above decoding process etc. for the two units UT2 and UT3, and also for the first unit tJ.
In T1, the above-defeat was not seen and the next unit/ ) U T
When the above-mentioned coincidence is confirmed by the reproduction signal of No. 2, the remaining unit UT3 may be ignored.

Next, in order to further increase the reliability, the above-mentioned coincidence was confirmed for at least 1 (1≦n) units for the reproduced signal of each unit that was written three times (generally n times). Only in this case, it may be determined that the address currently being reproduced is the above-mentioned target address.In this case as well, there is no need to wait until all of the above-mentioned units written over n times have been reproduced, and the units are reproduced sequentially. As soon as the above match is confirmed for one of the units,
It may be determined that the address currently being reproduced is the target address.

By the way, the movement control operation of the throat 2 to the optical big amplifier until reaching the above target address may be performed in the same manner as in the past.For example, in the comparator circuit 5, the address value read from the address reading circuit 3 and the above purpose The difference between the address value and the address value is determined, and the head movement drive motor 12 is driven via the head movement control circuit 11 according to this difference.
Optical pick amplifier head 2 via head support plate 13 etc.
The difference between the reproduction address and the target address may be reduced by controlling the movement of the disc in the radial direction of the disk (in the direction of arrow A). The address reading circuit 3 in this case may have the same configuration as the conventional one, but
Based on the standard address read and determined from the preceding sector of the optical disc 1, the address of the sector currently being played following the preceding sector is calculated (for example, 1
This estimated address is compared with the address obtained by actual reproduction, and when these addresses fail, the said reproduction address or the estimated address is considered as the correct confirmed address. A circuit that outputs the signal may also be used. In addition, the pre-encoded estimated address is compared with the reproduced address and a set of error detection or correction codes, and the estimated address when one loss within a predetermined allowable range is output as correct. An address reading circuit 3 may also be used.

Note that the present invention is not limited to the above-mentioned embodiments, and can be applied to card-shaped recording media such as optical cards in addition to disc-shaped recording media, and can also be applied to blocks such as sectors of discs. The recording format of the .24 separate section (ID section) is also not limited to the illustrated example.

H1 Effects of the Invention According to the address access method of the present invention, n-overwritten addresses are sequentially reproduced one by one and compared with the target address each time they are decoded, and as soon as -"& is detected,
The block currently being played back is accessed as the target address block without playing back or decoding the remaining addresses among the n-overwritten addresses, so the signal processing time is short and the reliability is high. Address access can be performed while maintaining the same address, and processing can be simplified and high-speed access can be easily realized.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of a circuit configuration for explaining an address access method according to an embodiment of the present invention, and FIG. 2 shows an example of a signal recording format on an optical disk used in the embodiment. 3A and 3B are diagrams for explaining a comparison operation between a reproduced signal obtained by reproducing the optical disc having the recording formant of FIG. 2 and a signal obtained by encoding the target address. 1... Optical disk 2... Optical pickup head 3... Address reading circuit 5... Comparison circuit 6... Target address input terminal 9... Match signal output terminal

Claims (1)

[Claims] A recording medium in which a recording area is divided into a plurality of blocks, and each block is recorded with a corresponding block address and error detection or correction code written over n times (n is an integer of 2 or more). However, in the method of accessing a block with a desired target address, the n-overwritten addresses of the block currently being played are sequentially read and compared with the target address, and when a match is detected, the block is accessed. An address access method characterized in that a block currently being played is immediately accessed as a target address block without reading the remaining addresses of the block.