JP3048616B2 - Digital playback device - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to a digital playback device, and more particularly to recording and playback of additional information.

[Prior art] DAT (Digital Audio Tape recorde) that records and plays back audio signals as a digital recording / playback device
r) is known. The details of this DAT system are described in “DAT Technology and Its Practice”, Radio Technology, March 1987, and are omitted here.

FIG. 5 is a pattern diagram showing a recording track of a conventional DAT, in which (601) is a magnetic tape, (602)
Indicates a recording track formed obliquely to the longitudinal direction of the magnetic tape (601), and (603) indicates an audio signal area (hereinafter, referred to as a PCM area) in the recording track (602).

The PCM area (603) of one track is composed of 128 blocks, and FIG. 6 is a diagram showing the signal configuration of one block. In FIG. 6, (610) is a block synchronization signal,
(611) is a block address for identifying 128 blocks, and (612) is an ID which is additional information closely related to the audio signal such as sampling frequency and presence / absence of emphasis.
A code (613) indicates a parity for detecting an error in the block address (611) and the ID code (612), and (614) indicates an area in which audio data and a parity for error correction are recorded. Consists of 36 symbols. Here, one symbol refers to 8-bit data.

The same ID code is recorded every eight blocks.

 Next, error correction will be described.

FIG. 7 shows the code configuration of one track.
No. 4 to No. 4, and one plane is double-coded (C1) and (C2) as shown in FIG. A code whose code is completed in one track is called a one-track completed code. Audio symbols are arranged in two data areas each including 28 symbols and 13 horizontal blocks.

(C1) corrects an error in the vertical direction, and generates and adds four check symbols (P) from 28 audio symbols. (C2) performs horizontal error correction. Six check symbols (Q) are generated from 26 audio symbols and added.

Thus, the vertically and horizontally doubly encoded plane 4
The number of sheets is recorded in the data + parity (614) area of 128 blocks.

The code block N _{0 in} FIG. 8 does not correspond to the block N ₀ of the 128 blocks recorded on the tape, and is a number assigned to 32 C1 codes on one code plane.

The DAT performs distributed recording on two tracks in units of data generated during one rotation period of the drum. Therefore,
The same ID is recorded in this pair track.

[Problems to be Solved by the Invention] The conventional digital recording / reproducing apparatus is configured as described above, and a dedicated area for sub-data such as ID is provided for each block, so that the redundancy is increased, Not suitable for high-density recording systems. Also, multiple multiplex writings are performed to improve reliability, and there is a problem that it is difficult to effectively use the tape.

The present invention has been made in order to solve the above problems, and can perform recording and reproduction of sub data without providing a dedicated area for sub data in each block.
Moreover, it is an object of the present invention to provide a digital reproducing apparatus capable of reproducing sub data with high reliability.

[Means for Solving the Problems] A digital reproducing apparatus according to the present invention receives, as an input, a signal formed by encoding multiplexed sub data together with main data using first and second error correction codes. ,
First error correction means for performing error correction based on the first error correction code on the main data and the sub data and adding a flag indicating that the data has not been corrected; and processing by the first error correction means. A second error correction unit for performing error correction based on the second error correction code on the main data and the sub data, and a coincidence detection unit for detecting that the sub data coincides with each other. If the second error correction means cannot correct the error and a match is detected between the sub data to which the flag is not added, the sub data is processed as correct sub data.

[Operation] According to the present invention, error correction is performed at the time of reproducing multiplexed sub data, error cannot be corrected by the second error correction means, and there is no error (or correct error) by the first error correction means. It is further detected whether or not the sub data determined to be the same) is matched, and the sub data having the pattern match is processed as correctly reproduced sub data.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

In FIGS. 7 and 8, the data area is 2912 (28
There is a recording area for (× 13 × 2 × 4) symbols. On the other hand, the number of audio symbols recorded on one track is 2,880 symbols (720 words × 2ch × 2) when the number of channels is 2, the sampling frequency is 48 KHz, and the drum rotation speed is 2,000 rpm.
There is an empty area for the symbol, which is assigned to the ID. Hereinafter, an example will be described in which there is an empty area at the same position on the planes No. 2 and No. 4 in FIG.

FIG. 1 is a diagram showing an ID recording area according to an embodiment of the present invention, and the hatched portion in FIG. 1 corresponds to an empty area. That is, symbols 26 and 2 of blocks No. 9 to 12 and 28 to 31
7 is an empty area.

There is an empty area of 16 symbols on one plane, and the total of the two planes No2 and No4 is 32 symbols. By utilizing this, the ID is recorded without providing an ID-only area. Although double encoding of (C1) and (C2) is performed, multiple writing is effective for further improving reliability. In this case, about two to four layers may be used.

As for decoding of a double code, generally, after (C1) decoding, (C2) decoding is performed using the (C1) decoding result. Therefore, if one code cannot be corrected by multiple writing at the same (C2) code sequence, that is, the same symbol No. position in FIG. 1, a correct ID is not reproduced, and the effect of multiple writing is obtained. Disappears.

Therefore, in the case of multiplex writing, reliability is improved by arranging so as to be included in different (C2) code sequences.

In this case, for example, different writing is performed on the 26th symbol and the 27th symbol of the code block No9 (C2).
This means that multiplex recording was performed on the code. However, since the (C1) code is common, if an error that cannot be corrected (C1) occurs in seven code blocks including code block No. 9, (C1)
1) In the decoding, the (C1) flag is added, but in the (C2) code, seven erasure corrections cannot be performed, so that error correction of this plane cannot be performed. Therefore, correct ID reproduction becomes impossible.

The same ID is multiplex-recorded on different code planes, for example, plane No.
By performing multiplex recording on No. 2 and No. 4, the above inconvenience can be avoided.

Next, the configuration of an apparatus for realizing the above-described method will be described.

FIG. 2 is a block diagram showing a configuration of a recording system of the digital recording / reproducing apparatus. In FIG. 2, (101) is an input terminal of a digitized audio signal, (102) is a memory circuit, and (103) is the above. An address generation circuit for controlling an address of the memory circuit (102); (104) a terminal for inputting information necessary for ID generation; and (105) a ID for recording based on information supplied from the terminal (104). ID generation circuit.

(106) is an encoding circuit that performs encoding for error correction, and (107) is an encoded audio symbol and ID.
Are shown. Incidentally, (108) is a clock generation circuit for generating various clocks of the system.

 Next, the operation of the recording system having the above configuration will be described.

The audio signal input from the terminal (101) is temporarily stored in the memory circuit (102). The ID generated by the ID generation circuit (105) is also temporarily stored in the memory circuit (102).

The memory map as shown in FIG. 7 can be realized by controlling with a total of 12-bit addresses of 5 bits, 5 bits, and the plane No. 2 bits.

The audio data is stored in the data areas of the code planes No1 and No3 and the data areas of the code planes No2 and No4 except for the hatched parts in FIG. 1, and the ID is stored in the code planes No2 and No. 4 in the hatched parts of FIG. You.

Next, the (C1) and (C2) encoding are performed by the encoding circuit (10
After being performed in 6), the data is read out from the terminal (107) in a predetermined order, modulated by a modulation circuit (not shown), and recorded on a tape.

FIG. 3 is a block diagram showing the configuration of a reproducing system of the digital recording / reproducing apparatus. In FIG. 3, (117) denotes an input terminal for audio data and ID reproduced by the head,
(112) is a memory circuit, (113) is the memory circuit (11
2) A memory address generation circuit for controlling an address, and (110) is an output terminal of reproduced audio data.

(116) is an error correction circuit for correcting errors in the reproduced audio data and ID, and (115) takes in the ID stored in the memory circuit (112), performs a predetermined process, and sends it to the terminal (114). An ID decoding circuit for outputting an ID, and (118) is a clock generation circuit for generating various clocks of the system.

 Next, the operation of the reproducing system having the above configuration will be described.

The audio data and ID reproduced by the head are temporarily stored in the memory circuit (112) as shown in FIGS. 7 and 1 based on the memory address output from the address generation circuit (113). Next, error correction is performed by an error correction circuit (116). Here, if correction is impossible, a flag is added. After the correction processing is performed, the audio data is output from the terminal (110). The ID and the flag in the memory circuit (112) are taken into the ID decoding circuit (115), and the ID and the flag having high reliability are selected and output to the terminal (114). Control of the system or display of the ID is performed by the reproduced ID.

Next, an embodiment of the ID decoding circuit (115) will be described.

The same ID is the second of the code block No9 of the plane No2 and No4.
An example in which six symbols are recorded at four locations of the 26th symbol of the code block No. 28 will be described below.

Hereinafter, the 26th symbol of the code block No9 of the plane No2 is D1
0, the 26th symbol of the code block No28 of the plane No2 is D11,
26th symbol of code block No9 of plane No4 is D20, plane N
The 26th symbol of the code block No. 28 of o4 is D21. In this example, D10 and D11 are included in the same C2 code, and D11 and D20 are also included in the same code.

FIG. 4 is a block diagram showing a configuration example of the ID decode circuit (115). In FIG. 4, (401) denotes a memory circuit (1).
12) Input terminal of reproduction ID data and error correction result flag output from 12), (403) C including D10 and D11
F1 register for storing a flag indicating the correction result of the two codes (hereinafter, referred to as F1 flag), and (404) D20 and D21
Is an F2 register that stores a flag (hereinafter, referred to as an F2 flag) indicating a correction result of the C2 code including “.

(405) to (408) are registers for storing D10, D11, D20, and D21, respectively. (409) a match detection circuit that receives D10, D11, D20, and D21 as input, compares patterns of two input signals, detects whether or not they match, and outputs the result;
(410) is an output 409a of the match detection circuit (409) and a signal for selecting which of D10, D11, D20, and D21 is to be output as an ID recorded on one track with the F1 and F2 flags as inputs. The selection signal generation circuit to be generated, (411) is A to
A selector for selecting one of the four inputs of D, (402)
Is a circuit for processing an ID reproduced from one of the paired tracks (hereinafter, referred to as an A track), and (414) is an ID
A circuit for processing an ID reproduced from the other track of the paired track (hereinafter, referred to as a B track) with the same circuit configuration as the processing circuit (402). A circuit (412) transmits an ID reliability determination signal of each track. As input, track A ID and track B
A determination circuit for determining which ID of the IDs to select, (41
3) is a selector, and (415) is a register.

Next, the operation of the ID decoding circuit will be described.

The selection signal generation circuit (410) checks the F1 and F2 flags, and outputs the matched pattern as the track A ID when the two data patterns included in the correctly corrected code sequence match. Select signal (41
0a).

That is, if the F1 flag is correct, the pattern matching of D10 and D11 is verified, and if the F2 flag is correct, the pattern matching of D20 and D21 is verified. If they match, a selection signal for selecting the pattern as the output of the selector (411) (410
a) is output, and the selection result signal (410b) indicating whether or not the correct signal of the track A has been selected is set to the enabled state (= 0). If all the corrections are impossible and the flags are set for both F1 and F2, or if the corrections have been made but the patterns do not match, the selection result signal (410b) is set to an unusable state (= 1).

In general, in the case of error correction, when a large number of errors exceeding the capability of an error correction code are input, erroneous correction (herein referred to as erroneous correction) or determination that there is no error (herein referred to as overlooked) rarely occurs. . In such a case, audio data is reproduced based on the incorrect ID data, which causes noise. However, such inconvenience can be avoided by verifying pattern matching.

The determination circuit (412) receives the selection result of both the A and B tracks and outputs a selection signal for selecting the ID of the track indicating 0 by the selector (413). That is, the input A or B is selected. If the selection result of any of the tracks is 1, the determination circuit (412) selects the C input of the selector (413) so as to output the previously selected correct ID stored in the register (415). ) Selects the selection signal.

The above example is an example in which only the C2 decoding result is used.If the C1 decoding cannot correct the symbol, the symbol with the correct C1 decoding result is output as correct data, and only the symbol for which the C1 and C2 decoding cannot be corrected is corrected. There is a decoding algorithm of a double code that cannot be used.

For example, if the code blocks No. 9 to No. 19 of the plane No. 2 are erroneous, the C1 decoding adds a C1 flag to these blocks. In the C2 decoding, all errors in the plane cannot be corrected because the C1 flag exceeds 6 which is the capability of the C2 code, but the code blocks No. 28 to 31 determine that the C1 decoding result has no error. The ID is played as correct.

In the case of such a decoding algorithm, since the flag differs depending on the symbol, symbols D10, D11, D2 are used instead of the F1 register (403) and the F2 register (404) in FIG.
This can be realized by providing a flag register corresponding to each of 0 and D21.

Also, with the above algorithm, if there is an ID that has been corrected by C2 decoding or determined to be error-free,
Output as it is without performing match detection, otherwise C2
Decoding is not possible, but if the C1 flag is not added and the pattern of the competitors matches, the matching pattern is output as ID, otherwise the previously output ID is output again. However, there is no practical problem in terms of reliability.

In the above, an example in which the same ID is recorded in two tracks has been described. However, in the case where the ID is recorded in units of each track, it can be realized by using the output of the selector (411).

In the above embodiment, the audio signal is used as the main data, and the ID is used as the sub-data. However, other signals such as video may be used as the main data, and the ID is not related to the main data. The effect is obtained.

Further, in FIG. 4, although the coincidence detection is performed irrespective of the flag, the same effect as in the above embodiment can be obtained even if the configuration is such that the coincidence detection is performed only for the symbol to which the flag is not added.

[Effects of the Invention] It is assumed that error correction is performed at the time of reproducing multiplexed sub data, error correction cannot be performed by the second error correction means, and there is no error (or correctly corrected) by the first error correction means. It is further detected whether or not the matched sub-data matches each other, and the sub-data having the pattern match is processed as correctly reproduced sub-data, so that highly reliable sub-data can be reproduced.

[Brief description of the drawings]

FIG. 1 is a diagram showing an ID recording area according to an embodiment of the present invention, FIG. 2 is a block diagram showing a recording system configuration of a digital recording / reproducing apparatus according to an embodiment of the present invention, and FIG. FIG. 4 is a block diagram showing the configuration of a reproducing system of a digital recording / reproducing apparatus according to an embodiment of the present invention.
FIG. 5 is a block diagram showing an example of the configuration of a decoding circuit, FIG. 5 is a pattern diagram showing recording tracks of a conventional digital recording / reproducing apparatus, FIG. 6 is a signal configuration diagram of one block, and FIG.
FIG. 8 is a diagram showing a code configuration of a track, and FIG. 8 is a diagram showing a code configuration of one code plane. (112) ... memory circuit, (113) ... address generation circuit, (115) ... ID decoding circuit, (116) ... error correction circuit, (403) to (408) ... register, (409) ... ... Pattern match detection circuit, (410) ... Selection signal generation circuit,
(411), (413) ... selector, (412) ... determination circuit. The same reference numerals in the drawings indicate the same or corresponding parts.

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int. Cl. ⁷ , DB name) G11B 20/18 G11B 20/12

Claims (1)

(57) [Claims] 1. A signal formed by encoding sub-data to be multiplexed and transmitted with first and second error correction codes together with main data is input to the main data and the sub-data. First error correction means for performing error correction based on the error correction code and adding a flag indicating that the error data has not been corrected; and the main data and the sub data processed by the first error correction means. A second error correction means for performing error correction based on a second error correction code, and a coincidence detection means for detecting that the sub data has coincided with each other, wherein the second error correction means cannot correct the error; A digital reproducing apparatus characterized in that when a match is detected between sub-data to which the flag is not added, the sub-data is processed as correct sub-data.