JPH08106727A - Disk reproducing device - Google Patents

Abstract

PURPOSE: To shorten the time until the reproduction of a data is started at the time of a track jump in a reproducer conducting CLV control. CONSTITUTION: A clock generating circuit 11 outputs a clock 39 generated by a crystal clock generating circuit 37 as an operation clock 18 when the linear velocity of an optical disk 1 is kept constant, and generates the operation clock 18 synchronized with a read signal 27 from the optical disk 1 amplified by a preamplifier 9 generated on the inside at the time of a track jump. A reproduction clock generating circuit 59 forms the reproduction clock 27 synchronized with a signal amplified by the preamplifier 9. A data processing circuit 28 reproduces a data from the read signal 27 by using the operation clock 18 and the reproduction clock 27.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reproducing apparatus for a recording disk such as an optical disk, and more particularly to a technique for improving the reproducing speed in an optical disk reproducing apparatus in which a digital signal is recorded at a constant linear velocity.

[0002]

2. Description of the Related Art As an optical disc for recording digital data, there is, for example, a compact disc (CD) used for recording audio signals such as music. C like this
In D, digital data obtained by converting an audio signal is recorded at a constant linear density. A CD that plays such a CD
As described in Japanese Unexamined Patent Publication No. 59-185071, the player performs the CLV control for controlling the rotation of the optical disc so that the linear velocity becomes constant, while converting the recorded digital signal into a signal of a constant frequency. Playing.

As an optical disk for recording digital data, there is also known a CD-ROM which uses a CD as a storage medium of an external storage device of a computer. Such a CD-ROM reproducing device is required to have a high access speed in view of its role as an external storage device of the computer.

In the reproducing apparatus for performing the CLV control described above, when accessing an optical disk, the head for reading digital data from the optical disk is moved (track jump) to the track to be accessed, and the number of revolutions is changed to access. The linear velocity of the track is fixedly set to a predetermined velocity, then the track is accessed, and whether or not the track is the target track is recorded in data called subcode recorded on the track. Based on the confirmation, if the target track can be confirmed, the digital signal is reproduced from the track. However, when there is a difference between the number of revolutions at which the linear velocity of the track on which the head is moved becomes a fixed fixed velocity and the number of revolutions before the movement, the number of revolutions depends on the linear velocity of the track to be accessed. It takes a relatively long time until the number of revolutions reaches a fixedly fixed speed. During this time, the optical disc cannot be accessed. That is, the CLV control has a problem in increasing the access speed. The ratio of the number of revolutions for reproducing the innermost circumference of the optical disc to the number of revolutions for reproducing the outermost circumference is about 2.3.

On the other hand, as a technique for improving the access speed of such an optical disc in which digital signals are recorded at a constant linear density, an optical disc in which digital signals are recorded at a constant linear density has a constant rotational speed. The technique described in Japanese Unexamined Patent Publication No. 5-250804, which is controlled and accessed by CAV control for controlling the rotation of the optical disc, and an optical disc on which digital signals are recorded at a constant linear density,
CLV control is performed when sequentially accessing and reproducing, and when performing discontinuous access in the radial direction of the optical disc, control is performed so as not to change the rotational speed to access the optical disc. The technique described in the publication is known.

[0006]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
When performing CAV control as in the technique described in Japanese Patent No. 4, it is necessary to provide a mechanism for detecting the number of rotations of the motor in order to control the motor for rotating the optical disk at a constant number of rotations. Further, if the control like the technique described in Japanese Patent Laid-Open No. 6-89506 is attempted, the circuit for controlling the rotation speed becomes complicated.

Therefore, an object of the present invention is to shorten the time required for reproducing data at the time of track jump in an optical disk reproducing apparatus which performs CLV control.

[0008]

[Means for Solving the Problems] To achieve the above object,
The present invention is a disc reproducing apparatus for reproducing a recording disc having a plurality of tracks on which signals are recorded at a constant linear density while rotating, and a signal recorded on the track is recorded from each track of the rotating recording disc. CLV for controlling the number of revolutions of the recording disk according to the speed of the signal read by the pickup so that the linear speed of the pickup for reading and the track for reading the signal by the pickup always becomes a predetermined linear speed. A control means, a reproduction clock generation means for generating a reproduction clock which is a clock synchronized with the signal read by the pickup, a basic clock generation means for generating a basic clock which is a clock of a predetermined frequency, and an operation clock. The operation clock generating means for generating and the pickup read out A data processing unit for sampling a signal by the reproduction clock and reproducing the data represented by the signal from the sampled signal by using the operation clock, and a track jump for switching the track for moving the pickup and reading the signal by the pickup. At this time, the CLV control means outputs a switching signal until the linear velocity of the track for reading a signal by the pickup after the track jump reaches the predetermined linear velocity, and the operation clock generating means. Means for generating a synchronous clock that is a clock synchronized with the signal read by the pickup, and the operation clock according to the synchronous clock when the switching signal is being output, If not output It said basic clock to provide a disk reproducing apparatus, characterized in that it comprises a switching means for generating as the operating clock.

[0009]

According to the disk reproducing apparatus of the present invention, at the time of a track jump, the operation clock generating means generates the synchronous clock which is a clock synchronized with the signal read by the pickup, and the switching signal. A clock corresponding to the synchronous clock is generated as the operation clock when being output, and the basic clock is generated as the operation clock when the switching signal is not being output. Not only the reproduction clock generation means, but also the operation clock generation means generates a reproduction clock and an operation clock synchronized with the signal read from the recording disk. Therefore, even when the linear velocity is set to a predetermined value at the time of track jump, the sub-code is reproduced and it is possible to judge from this whether or not the pickup has moved to the target track. Therefore, when the track velocity is set to a predetermined value during the track jump,
The time until the data is reproduced is shortened as compared with the conventional case in which it is determined whether or not the pickup is moved to the target track by reproducing the data.

[0010]

EXAMPLE An optical disc reproducing apparatus according to the present invention will be described below.
The case of applying to a CD reproducing apparatus will be described as an example.

First, the first embodiment will be described.

FIG. 1 shows the configuration of an optical disk reproducing apparatus according to the first embodiment.

In the figure, 1 is an optical disk on which data is recorded at a constant linear density, 2 is a disk motor for rotating the optical disk, 4 is a drive circuit for driving the disk motor 2, and 5 is a signal recorded on the optical disk 1. Is a feed mechanism for moving the pickup 5 in the radial direction of the optical disk, and 7 is a pickup servo circuit for controlling the feed mechanism 6 for moving the pickup 5.

Reference numeral 9 is a preamplifier for amplifying the signal read by the pickup 5, and 28 is a data processing circuit for reproducing data from the signal 10 amplified by the preamplifier 9. The data processing circuit 28 is connected to the RAM via the bus 29.
Play the data while using 30 to store the data. A RAM control circuit 31 controls the reading and writing of data in the RAM 30. The data processing circuit 28 also outputs a signal 33 representing the linear velocity of the optical disc 1 and a subcode 32 detected from the signals amplified by the preamplifier 9, as will be described later.

Next, the crystal system clock generation circuit 37 generates a fixed frequency clock 38 and a fixed frequency clock 39 by dividing the clock output from the crystal oscillator 36.
The reproduction clock generation circuit 59 generates the reproduction clock 27 synchronized with the signal amplified by the preamplifier 9. Further, the clock generation circuit 11 outputs one of the clock synchronized with the signal amplified by the preamplifier 9 generated internally or the clock 39 generated by the crystal system clock generation circuit 37 according to the control of the CLV speed control circuit 34. It is output as the operation clock 18.

The CLV speed control circuit 34 controls the drive circuit 4 via the low-pass filter 42 according to the signal 33 representing the linear velocity of the optical disk 1 to apply a voltage to the motor 2 for rotation. CLV control is performed to control the number so that the linear velocity of the optical disk is constant.

System control microcomputer 50
Controls the pickup servo 7 and the pickup 5,
For example, it moves to a target track designated from the outside (track jump), and it is determined whether or not the pickup 5 is positioned on the target track according to the contents of the subcode 32 output from the data processing circuit 28. When the pickup 5 is not positioned on the target track, the pickup servo 7 is further controlled to move the pickup 5 (track jump) to determine whether or not the pickup 5 is positioned on the target track. To do. The pickup servo 7 also performs tracking control for controlling the position of the pickup 5 based on the signal output from the preamplifier 9 so that the pickup 5 traces correctly on the track.

The access control 41 controls the operations of the CLV speed control circuit 24 and the clock generation circuit 11 during the track jump of the pickup 5.

In such a configuration, the CLV speed control circuit 34 operates by using the fixed frequency clock 38 generated by the crystal system clock generation circuit 37, and the RAM control circuit 31 operates by the operation clock 1 generated by the clock generation circuit 11.
8 to work.

When the linear velocity of the optical disk 1 is constant, the frequency of the reproduction clock 27 generated by the reproduction clock generation circuit 59 is 4.3218 M, for example.
It becomes Hz. Further, since the reproduction clock generation circuit 59 always generates the reproduction clock synchronized with the signal 10 amplified by the preamplifier 9, during the track jump, until the linear velocity becomes constant under the control of the CLV velocity control circuit 34.
A reproduced clock having a frequency that follows the linear velocity at that time is generated. Details of the reproduced clock generation circuit 59 will be described later.

On the other hand, when the linear velocity of the optical disk 1 is constant, the clock generation circuit 11 generates the clock generated by the crystal system clock generation circuit 37, for example, 4.2336M.
A clock 39 having a frequency of Hz is output as the operation clock 18, and at the time of a track jump, the operation clock 1 synchronized with the signal 10 amplified by the internally generated preamplifier 9
Generate 8. Therefore, CL at the time of track jump
Until the linear velocity becomes constant under the control of the V velocity control circuit 34, the operation clock 18 having a frequency that follows the linear velocity at that time is generated. However, the frequency of the operation clock 18 generated during the track jump until the linear velocity becomes constant under the control of the CLV speed control circuit 34 is the reproduction clock 27 generated during the track jump.
It is still 4.2336 / 4.3218 times the frequency of.

Next, FIG. 2 shows the internal structure of the data processing circuit.

In the figure, reference numeral 200 is a sampling circuit for sampling the signal 10 amplified by the preamplifier 9 using the reproduction clock 27 generated by the reproduction clock generation circuit 59 and converting it into data. A demodulation circuit 201 demodulates the data sampled by the sampling circuit 200. The data demodulated by the demodulation circuit 201 is written under the control of the RAM control circuit 31 into the RAM 30 via the bus 29 so that the data are arranged in a predetermined order. The data written in the RAM 30 is then read out by the control of the RAM control circuit 31, input to the error correction circuit 202, subjected to error correction processing, and then the interpolation circuit 203 interpolates the data for the voice signal and the like. After being processed, it is output as reproduced data. The RAM control circuit 31 also monitors the overflow and underflow of the RAM 30.

The RAM control circuit 31 operates by the operation clock 18 output from the clock generation circuit 11, and RA
Both the writing and reading of M30 are controlled. Therefore, there is no overflow or underflow of the RAM 30 due to the difference in the operating clock speed between writing and reading.

Next, the sub-code detection circuit 204 detects the sub-code from the demodulated data by the operation clock 18 output from the clock generation circuit 11, and as the sub-code 32, the system microcomputer 50. Output to. The sub-code is a code recorded before the data in order to manage the data recorded on the optical disc.
It is Further, the linear velocity detection circuit 205 outputs a signal 33 having a value corresponding to the linear velocity of the optical disc 1 to the CLV velocity control circuit 34 from the signal 10 amplified by the preamplifier 9. Further, the synchronization detection circuit 206 detects the synchronization signal included in the signal 10 amplified by the preamplifier 9 using the reproduction clock 27, and outputs the signal 64 representing the detection result to the reproduction clock generation circuit 59.

In such a configuration, as described above, both the reproduction clock 27 and the operation clock 18 have the linear velocity of the optical disk, that is, the data, at each time until the linear velocity becomes constant at the time of the track jump. Follow the reading speed of. Therefore, the subcode can be detected and the data can be reproduced without any trouble until the linear velocity becomes constant during the track jump.

Next, CL performed by the CLV speed control circuit 34
The V control will be described.

System control microcomputer 50
Outputs a command to move the pickup 5 to the pickup servo 7 when performing a track jump, and informs the access control circuit 40 that the track jump is to be performed and the contents of the track jump. The access control circuit controls the clock generation circuit 11 and the CLV speed control circuit 34 accordingly. At this time, the CLV speed control circuit 34 is subjected to predictive control according to the contents of the track jump. That is, the contents of the track jump are
In the case of the movement of the pickup 5 from the outer circumference to the inner circumference, which requires the rotation speed to be increased in order to keep the linear velocity constant, an acceleration voltage for accelerating the disk motor 2 is applied to the disk motor 2. Unconditionally,
The CLV speed control circuit 34 is controlled so as to output for a period corresponding to the distance or position where the pickup 5 moves by the track jump. On the contrary, when the content of the track jump is the movement of the pickup 5 from the inner circumference to the outer circumference, which requires the rotation speed to be slowed, an acceleration voltage for decelerating the disk motor 2 is applied. The CLV speed control circuit 34 is controlled so as to unconditionally output the output applied to the pickup 5 for a period corresponding to the distance or position where the pickup 5 moves by the track jump.

FIG. 3 shows the voltage applied to the disk motor 2 when the pickup is moved from the outer circumference to the inner circumference.

The CLV speed control circuit 34, as shown in FIG. 3, includes a period during which such predictive control is performed, and
After that, the signal 33 representing the linear velocity of the optical disk 1 is roughly controlled until the target linear velocity is established to some extent, and the linear velocity is controlled to be rough and the signal 60 is rough-servoed. After that, the value indicating that the precision servo is performed is performed while the control for precisely controlling the linear velocity is performed.

Next, details of the clock generation circuit 11 will be described.

FIG. 4 shows the internal structure of the clock generation circuit 11.

In the figure, 15 is a phase comparator, 12 is a loop filter, 13 is a voltage controlled oscillator, 14 is a frequency divider, and 17 is a switching circuit.

Reference numeral 15 is a phase comparator, 12 is a loop filter, 13 is a voltage controlled oscillator, and 14 is a frequency divider, which constitutes a PLL circuit for generating a clock synchronized with the signal 10 amplified by the preamplifier 9. Signal 1 amplified by preamplifier 9
Since the velocity of 0 represents the linear velocity of the optical disc 1, this clock is a clock that follows changes in the linear velocity. The switching circuit 17a normally outputs the clock 39 generated by the crystal system operation clock generation circuit 37 as the operation clock 18, but outputs it as the operation clock 18 according to the control of the access control circuit 40 at the start of the track jump. The clock to be used is switched to the clock generated by the PLL. Further, when the signal 60 from the CLV speed control circuit 34 changes from a value representing a rough servo to a value representing a precision servo, the crystal system operation clock generation circuit 37 again generates a clock to be output as the operation clock 18. Clock 3
Switch to 9. However, the switching circuit 17 outputs the clock output as the operation clock 18 when the signal 60 from the CLV speed control circuit 34 changes from the value representing the precision servo to the value representing the rough servo at the start of the track jump. You may make it switch to the clock generated by PLL.

Next, details of the reproduced clock generation circuit 59 will be described.

FIG. 5 shows the internal structure of the recovered clock generating circuit 59.

In the figure, 21 is a loop filter, 22 is a voltage controlled oscillator, 23 is a frequency divider, 24 is a phase comparator a, 25.
Is a phase comparator b, and 26 is an adder.

Loop filter 21, voltage controlled oscillator 2
2, the frequency divider 23, and the phase comparator a24 are PLLs that generate a clock synchronized with the signal 10 amplified by the preamplifier 9.
Make up the circuit. The phase comparator b and the adder 26 play a role of assisting the phase comparator a during a track jump.
That is, in the reproduced clock generation circuit 59, the signal output from the phase comparator b is added to the signal output from the phase comparator a24 by the adder 26, so that the reproduced clock 27 output from the PLL at the time of track jump. Of the frequency and phase of the signal 10 to the speed and phase of the signal 10 is accelerated. Here, the frequency divider 23 gives the phase comparator a24 a clock having a higher frequency than the clock given to the phase comparator 25. That is, the phase comparator a24 performs more precise phase comparison than the phase comparator b25, and the phase comparator b2
5 performs rougher phase comparison than the phase comparator a24.

FIG. 6 shows the internal structure of the phase comparator b25.

In FIG. 6, 70 is a pulse width detection circuit,
71 is a lock position detection circuit, 72 is an addition circuit, and 73 is "
0 "level generation circuit, 74 is a switching circuit, 75 is a cumulative addition circuit, and 76 is a PWM (Pulse Width Modulation) circuit.

The pulse width detection circuit 70 detects the pulse width of the signal 10 from the preamplifier 9 using the clock 61 divided by the frequency division circuit 23, and oscillates the voltage controlled oscillator 22 detected from this pulse width. A signal representing the difference between the frequency and the frequency of the signal 10 is output.

The "0" level generation circuit 73 outputs a signal having the same value as the value output by the pulse width detection circuit 70 when there is no deviation between the oscillation frequency of the voltage controlled oscillator 22 and the frequency of the signal 10.

The switching circuit 74 includes the data processing circuit 28.
When the signal 64 output from the synchronization detection circuit 206 of 1 indicates that the synchronization signal included in the reproduction clock 27 and the signal 10 amplified by the preamplifier 9 can be detected.
The signal output from the 0 "level generation circuit 73 is selected and output, and when the signal 64 indicates that the synchronization signal cannot be detected, the signal output from the pulse width detection circuit 70 is selected and output. The switching circuit 74 may switch the signal to be selected, for example, in accordance with whether or not the subcode could be detected by the subcode detection circuit 204.

The lock position detecting circuit 71 detects the phase difference between the edges of the pulse of the signal 10 and the pulse of the clock of the divided signal 62 by the signal 10 amplified by the preamplifier 9 and the divided signal 62. Pulse and divided signal 6
A signal having a magnitude necessary to make the phase difference between the edges of the pulses of the two clocks the specified phase difference is output.

The adder 72 adds the signal output from the switching circuit 74 and the signal output from the lock position detection circuit 71. The added signals are sequentially added by the cumulative addition circuit 75. The result of addition in the cumulative addition circuit 75 is
After the PWM conversion by the PWM conversion circuit 76, the adder 2
6 and is added to the output signal of the phase comparator a24 as described above.

As a result, when the reproduction clock 27 and the signal 10 amplified by the preamplifier 9 are not synchronized, a signal representing the frequency difference between the reproduction clock 27 and the signal 10 amplified by the preamplifier 9 detected by the pulse width detection circuit 70. Is added to the voltage controlled oscillator 22 via the loop filter 21.
Therefore, at the time of the track jump, the signal 10 of the frequency and phase of the reproduction clock 27 output from the PLL is output.
The speed and followability of the phase can be accelerated. Further, when the reproduction clock 27 and the signal 10 amplified by the preamplifier 9 are synchronized, the signal indicating the frequency shift detected by the pulse width detection circuit 70 is not added, so that the PLL exhibits an excessive response during the non-track jump. Nothing. However, depending on the performance required for the PLL, the reproduction clock 27
Even when the signal 10 amplified by the preamplifier 9 is synchronized, the signal indicating the frequency shift detected by the pulse width detection circuit 70 may be added.

FIG. 7 shows the internal structure of the pulse width detection circuit 70.

In the figure, 80 is a pulse width counting circuit, and 81
Is an L-side maximum value holding circuit, 82 is an H-side maximum value holding circuit, 8
3 is an L / H averaging circuit.

The pulse width counting circuit 80 has a High level pulse width of the signal 10 from the preamplifier 9 and Lo.
A signal 6 obtained by dividing the w-level pulse width by the frequency dividing circuit 23.
Count the pulse width using 1.

The L-side maximum value holding circuit 81 holds the maximum value of the pulse width at the Low level, and the H-side maximum value holding circuit 82 holds the maximum value of the pulse width at the High level. This is realized by holding the current pulse width instead of the current value when a pulse width larger than the current pulse width is counted. L / H maximum value averaging circuit 8
3, the value held in the L-side maximum value holding circuit 81 and H
The average of the values held in the side maximum value holding circuit 82 is calculated, and this is compared with an expected maximum pulse width value when the linear velocity is constant, which is stored in advance, and the difference is output. This difference represents a deviation from the normal relationship between the oscillation frequency of the voltage controlled oscillator 22 and the frequency of the signal 10.

Incidentally, instead of the maximum value of the pulse width, the oscillation frequency of the voltage controlled oscillator 22 and the frequency of the signal 10 are similarly set according to the minimum value of the pulse width and the frequency of occurrence of pulses of each pulse width. The above-mentioned shift can be detected.

Next, FIG. 8 shows the internal structure of the lock position detection circuit 71.

In the figure, 90 is an edge detection circuit, 91 is a phase lead counting circuit, 92 is a phase delay counting circuit, and 93.
Is a count value comparison circuit, and 94 is a lock position correction value generation circuit.

The edge detection circuit 90 outputs whether the phase of the edge of the pulse of the signal 10 from the preamplifier 9 is advanced or delayed with respect to the edge of the clock signal 63 divided by the frequency division circuit 23. If the phase is advanced, the phase advance counting circuit 91 counts, and if the phase is delayed, the phase delay counting circuit 92 counts. The respective count values are compared by the comparison circuit 93, and depending on whether the results are substantially equal or which is larger, whether the phase of the divided generated signal 63 with respect to the input signal 10 is in phase or in advance, Detect if you are late.

Then, based on the detection result, the lock position correction value generation circuit 94 generates a correction value so as to obtain the specified phase and outputs it to the adder 72.

The first embodiment of the present invention has been described above.

The second embodiment will be described below.

FIG. 9 shows the structure of the reproducing apparatus in the second embodiment.

The reproducing apparatus according to the second embodiment is the same as the first embodiment.
The difference from the reproducing apparatus according to the embodiment (see FIG. 1) is that the data processing circuit 28 includes a pulse width detecting circuit 70, a "0" level generating circuit 73, and a switching circuit 74 of the reproducing clock generating circuit 11 for data processing. This is the point provided in the circuit 28. Reference numeral 35 in the figure represents the output of the switching circuit 74.

When the reproducing apparatus according to the first or second embodiment described above is integrated as an LSI or the like, as shown in FIG. 10, a RAM 30, a reproduced clock generating circuit 59, a RAM control circuit. The CLV speed control circuit 34, the CLV speed control circuit 34, and the access control circuit 40 may be integrated with the data processing circuit 28. Further, the clock generation circuit 11 may be integrated together. However, also in this case, the crystal oscillator 36 is connected to the outside of the LSI in which these are integrated.

Further, as shown in FIG. 11, the RAM 30 is not integrated with other circuits, but the data processing circuit and CLV are not integrated.
You may make it connect to the exterior of LSI in which the speed control circuit 34 etc. were integrated.

As shown in FIG. 12, the system control microcomputer 50 may be configured to perform the control performed by the access control circuit 40 in each of the above embodiments.

As described above, according to the optical disc reproducing apparatus in each embodiment, the CLV speed control circuit 3 is used.
As described above, the predictive control is performed in accordance with No. 4, so that the time required to set the linear velocity to a predetermined value at the time of track jump can be shortened.

At the time of track jump, the reproduction clock generation circuit 59 and the clock generation circuit 11 both generate the reproduction clock 27 and the operation clock 18 which are synchronized with the signal read from the optical disk 10, and as shown in FIG. Even when the linear velocity is set to a predetermined value at the time of track jump, the sub-code is reproduced and it is possible to judge from this whether or not the pickup has moved to the target track. Therefore, when the track velocity is set to a predetermined value at the time of a track jump, the subcode is played back to determine whether or not the pickup has moved to the target track. Shortened.
Further, the overflow and underflow of the RAM 30 due to the difference in the read clock write clock of the RAM 30 does not occur. Data can be reproduced in the same manner as the sub-code until the linear velocity is set to a predetermined value at the time of track jump. However, audio signal CD
For data that needs to be played back at a constant speed, such as audio data in (1), the linear velocity is set to a predetermined value before being played back. The CD to be played is an audio signal CD
Whether it is a CD-ROM that stores data used by a computer can be determined from the subcode information in the data.

Since the CLV control circuit 34 always operates with a stable and high-speed clock output from the crystal system clock generation circuit 38, the rotation speed is controlled stably and at high speed so as to obtain a predetermined linear velocity. can do.

[0066]

As described above, according to the present invention, CLV
In the optical disc reproducing apparatus that performs control, it is possible to shorten the time required until the data is reproduced at the time of track jump.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an optical disk reproducing apparatus according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a reproducing device of the data processing circuit according to the first embodiment of the present invention.

FIG. 3 is a timing chart showing the operation of the reproducing apparatus of the data processing circuit according to the first embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a reproduction device of the clock generation circuit according to the first embodiment of the present invention.

FIG. 5 is a block diagram showing a configuration of a reproducing apparatus of the reproduced clock generating circuit according to the first embodiment of the present invention.

FIG. 6 is a block diagram showing a configuration of a phase comparator b according to the first exemplary embodiment of the present invention.

FIG. 7 is a block diagram showing a configuration of a reproducing device of the pulse width detecting circuit according to the first embodiment of the present invention.

FIG. 8 is a block diagram showing a configuration of a lock position detection circuit according to the first embodiment of the present invention.

FIG. 9 is a block diagram showing a configuration of an optical disk reproducing apparatus according to a second embodiment of the present invention.

FIG. 10 is a block diagram showing an integration point when integrating the optical disk reproduction apparatus according to the embodiment of the present invention.

FIG. 11 is a block diagram showing an integration point when integrating the optical disc reproducing apparatus according to the embodiment of the present invention.

FIG. 12 is a block diagram showing another configuration example of the optical disc reproducing apparatus in the example of the present invention.

[Explanation of symbols]

 1 optical disk 2 disk motor 4 drive circuit 5 pickup 6 feed mechanism 7 pickup servo circuit 9 preamplifier 11 clock generation circuit 28 data processing circuit 29 bus 30 RAM 31 RAM control circuit 31 34 CLV control circuit 36 crystal oscillator 37 crystal system clock generation circuit 41 access control circuit 59 recovered clock generation circuit 50 system control microcomputer

Claims (6)

[Claims] 1. A disc reproducing apparatus for reproducing while rotating a recording disc having a plurality of tracks on which signals are recorded at a constant linear density, wherein a signal recorded on each track of the rotating recording disc. And a pickup for reading the signal, the rotation speed of the recording disk is controlled according to the speed of the signal read by the pickup so that the linear speed of the track for reading the signal is always a predetermined linear speed. CLV control means, reproduction clock generation means for generating a reproduction clock that is a clock synchronized with the signal read by the pickup, basic clock generation means for generating a basic clock that is a clock of a predetermined frequency, and operating clock And an operation clock generating means for generating A data processing unit that samples the output signal by the reproduction clock and reproduces the data represented by the signal from the sampled signal by using the operation clock; and a track that switches the pickup and reads the signal by the pickup. At the time of track jump, the CLV control means outputs a switching signal until the linear velocity of the track at which a signal is read by a pickup after the track jump reaches the predetermined linear velocity, and the operation clock generation means. Means for generating a synchronization clock that is a clock synchronized with the signal read by the pickup, and for generating the operation clock according to the synchronization clock when the switching signal is being output, and performing the switching. Signal is being output And a switching means for generating the basic clock as the operation clock when there is no such disc. 2. The disc reproducing apparatus according to claim 1, wherein the data processing means demodulates the sampled signal into data by a predetermined demodulation method, and a memory for temporarily storing the demodulated data. Means, error correction means for the data read from the storage means, writing the demodulated data into the storage means in synchronization with the operation clock, and the data stored in the storage means A disk reproducing apparatus comprising: storage control means for controlling reading in synchronization with an operation clock. 3. The disc reproducing apparatus according to claim 1, further comprising a synchronization detecting unit that detects whether or not the signal read by the pickup and the reproducing clock are synchronized. The clock generation means includes a PLL circuit that generates a reproduction clock that is a clock synchronized with the signal read by the pickup,
The response characteristics of the PLL circuit when the synchronization detecting means does not detect that the signal read by the pickup and the reproduction clock are in synchronization with each other. , And means for changing so as to follow up more quickly. 4. The disk reproducing apparatus according to claim 1 or 2, wherein the reproduction clock generating means generates an oscillation clock which is a clock having a frequency according to a value of a given clock control signal. A first phase difference detecting means for detecting a phase difference between the oscillation clock and a signal read by the pickup; and a definition of a difference between the frequency of the oscillation clock and the frequency of the signal read by the pickup. A frequency deviation detecting means for detecting a deviation from a frequency difference value, and a phase difference deviation detecting means for detecting a deviation of the phase difference between the phase of the oscillation clock and the signal read by the pickup from a prescribed phase difference value. A signal having a value indicating the magnitude of the frequency shift detected by the frequency difference detection means and the phase detected by the phase shift detection means. A second phase difference detecting means having a first adding means for adding a signal having a value representing the magnitude thereof at a predetermined ratio, and a value representing the phase difference detected by the first phase difference detecting means. With a signal, and the second
Second addition means for adding the signals added by the first addition means of the phase difference detection means at a predetermined ratio, and the clock control signal is generated according to the value added by the second addition means. A disc reproducing apparatus having means. 5. The disc reproducing apparatus according to claim 4, wherein the frequency shift detecting means determines a pulse width of a pulse included in a signal read by the pickup,
A disc reproducing apparatus characterized in that the frequency shift is detected by measuring the oscillation clock as a reference and measuring a shift of the measured pulse width from a prescribed pulse width. 6. The disc reproducing apparatus according to claim 4 or 5, further comprising a synchronization detecting means for detecting whether or not the signal read by the pickup and the reproduction clock are in synchronization with each other, The addition means 2 adds the magnitude of the frequency deviation detected by the frequency deviation detecting means only when the synchronization detecting means does not detect that the signal read by the pickup and the reproduction clock are in synchronization with each other. A disc reproducing apparatus characterized by adding a signal having a value representing