JPH05166306A - Digital audio signal regenerating device - Google Patents

Abstract

PURPOSE:To enable changing the reproduction speed in a digital audio regenerat ing device without changing the clock frequency of a driving system. CONSTITUTION:The driving system for a CLV servo circuit 108, a signal processing circuit 115, etc., operate synchronizing with the system clock of a fixed frequency sent from a system clock oscillation circuit 121. The audio data given from the circuit 115 are written into the data memory of a reproduction speed converting circuit 123 synchronously with the system clock and then successively read out synchronously with the reproduction clock of a variable frequency from a reproduction clock oscillation circuit 122. Then these read data are outputted to an L/R separating circuit 116. When the data written in the data memory reach a prescribed level, the driving system is set in a pause state by a pause control signal. This pause state is released and returned to a reproduction state when the data memory has a margin. The circuit 123 interrupts the fetching of the audio data in a period when the error signal sent from the circuit 115 is kept active. Meanwhile the output of the audio data is carried out to the circuit 116 and the circuit 123 absorbs the data errors.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital audio reproducing apparatus capable of changing a reproducing speed.

[0002]

2. Description of the Related Art For example, when playing an electronic musical instrument in tune with music played by audio reproduction such as a CD (compact disc), especially in the case of a beginner, the playing tempo of the CD cannot be followed by a keyboard operation and is reproduced. Often you want to slow down. In addition, there is a case where it is desired to adjust the reproduction speed of the CD according to the taste and to play according to the reproduced sound. In such a case, it would be convenient if the reproduction speed of the CD player could be adjusted.

FIG. 7 shows a conventional CD whose playback speed can be changed.
It is a block diagram of a circuit block of the player. CD101
Is set in a holder part (not shown) of the CD circuit block.

The system control circuit 113 is, for example, a microprocessor, and drives CLV (C
The servo control signal is output to the on-stant linear velocity servo circuit 108, the focus servo circuit 104, the feed servo circuit 107, and the tracking servo circuit 105.

Further, the system control circuit 113 controls the clock selection circuit 119 according to the setting content of the reproduction speed in the CD operating section 114. As a result, the clock selection circuit 119 causes the CLV servo circuit 108 and the signal processing circuit 1 to operate.
An oscillator for generating a clock pulse used in 15 or the like is selected from a plurality of oscillators # 1 to # 3, for example, and a master clock output from the oscillator is supplied to each circuit.

Next, the CLV servo circuit 108 uses the CD1
The rotational speed of the spindle motor 102 for rotating 01 is controlled so that the linear velocity of each track of the CD 101 becomes constant.

Further, the focus servo circuit 104 detects a focus error from the state of the reflected light of the laser beam, and based on the focus error, the optical pickup 1
The objective lens in 03 is controlled and driven in the optical axis direction. Further, the feed servo circuit 107 moves the optical pickup 103 in the radial direction by the feed motor 106 while detecting the deviation of the laser beam from the center of the track of the CD 101. In addition, the tracking servo circuit 105 causes the optical pickup 103 itself to follow a track in response to a fast movement due to eccentricity of the disk.

As described above, the optical pickup 10 is controlled by the feed servo circuit 107 and the tracking servo circuit 105.
The laser beam emitted from 3 is controlled so as to be accurately emitted to the center of the track of the CD 101. This C
A protrusion called a pit is engraved on the side of the D101 irradiated with the laser beam, and a digital signal is recorded by this. Then, the optical pickup 107
Detects the presence / absence of a pit based on the amount of reflected light of the emitted laser beam, and a digital signal corresponding to the presence / absence of the pit and its length is read and input to the data extraction circuit 110 as a reproduction signal. ..

This reproduction signal is a kind of pulse train, and its pulse width varies in length from 3 to 11. Therefore, when this pulse is differentiated, it becomes a discontinuous pulse train in which some pulses are omitted. .. Therefore, the data extraction circuit 110
A clock extracting PLL (not shown) provided inside
A bit clock is extracted by converting the non-continuous pulse train of the reproduction signal into a continuous pulse train using (Phase Locked Loop).

Here, although not particularly shown, one frame of the CD signal is composed of a bit clock of 588 bits, and a frame synchronization signal is provided at the beginning of each frame. In addition, 6 samples (12
Since one sample data word) enters one frame, the time of one frame is 1 / fs × 6 (sec) (fs: sampling frequency), and this frequency is 7.35 KHz. Above 1
The frame consists of 588 bits, and the read bit clock is 7.35KHz × 588 = 4.3218MHz. However, this is the case where the CD reproduction speed described later is the standard speed. This 7.35 KHz clock is used for detection of the frame synchronization signal in the next frame synchronization circuit 111.

Subsequently, the frame synchronization circuit 111 detects the frame synchronization signal using the bit clock output from the data extraction circuit 110. Furthermore, by using the detected frame synchronization signal, EFM (Eight
to Fourteen Modulation 1
The 4-bit digital data (subcode, audio data, etc.) is demodulated by the EFM demodulation circuit 112.

Here, it is not known with what probability the logic "1" and logic "0" of each bit of digital data occur. The optical pickup 103 is the CD 10
When digital data is detected as an electric signal from the pit above 1, if one of logic "1" or "0" continues for a long time, a DC component is generated and bit interval information is interrupted. Such a state causes a malfunction in the focus servo circuit 104 and other servo circuits that perform a control operation based on the output of the optical pickup 103.

Therefore, in order to remove such a direct current component as much as possible, data conversion is performed so that one of logic "1" or "0" does not last long in consecutive bits of digital data to be recorded on the CD 105. , CD101
Recorded in. This is called EFM modulation. In this way, in order to reproduce the EFM-modulated signal recorded on the CD 101, the EFM demodulation circuit 112 performs a demodulation process reverse to the above-mentioned modulation process.

Of the EFM-demodulated data as described above, the audio data is sent to the signal processing circuit 115.
The subcode is input to the system control circuit 113. Since the subcode is not particularly relevant to the present invention, its explanation is omitted.

The signal processing circuit 115 is an EFM demodulation circuit 1
The audio data input from 12 is converted to CIRC (Cro
Error correction processing is performed based on a code called ss Interleaved Reed-Solomon Code), and deinterleave processing is performed to restore each sample of 16-bit digital audio data in frame units.

Thereafter, each sample of 16-bit digital audio data is separated into a stereo left channel output L and a right channel output R by an L / R separation circuit 124,
After being converted into analog signals by the D / A converters 117L and 117R, they are output as analog audio data to a sound system (not shown) or the like via the LPFs 118L and 118R.

As described above, the system control circuit 113
Controls the clock selection circuit 119 according to the setting content of the reproduction speed in the CD operating unit 114, and selects one of the plurality of oscillators 120 of # 1 to # 3, for example.

For example, when the standard reproduction speed is selected in the CD operating section 114, the system control circuit 1
13 is, for example, the first
The 7.35 KHz clock signal output from the oscillator 120 (# 1) is selected, and this master clock is used as the CLV servo circuit 108, the signal processing circuit 115, and the L / R separation circuit 1.
16 and D / A converters 117L and 117R.

Here, the CLV servo circuit 108, the spindle motor 102, the CD 101, and the data extraction circuit 110.
Clock extraction PLL and frequency divider 10 provided inside
The portion composed of 9 constitutes a PLL and performs CLV servo operation. Of these circuits, the CLV servo circuit 108 corresponds to the phase comparator of the PLL and performs phase comparison between the divided clock output from the frequency divider 109 and the master clock output from the clock selection circuit 119. The error voltage generated by this phase comparison operation is output to the spindle motor 102 and controls the motor drive voltage there. Then, the spindle motor 102, C
The clock extraction PLL provided in the D101 and the data extraction circuit 110 is a V including a loop fill of the PLL.
The drive voltage, which has the role of CO and is controlled based on the error voltage from the CLV servo circuit 108 described above, drives the spindle motor 102 and determines the frequency of the bit clock extracted from the digital extraction circuit 110.

From the frequency divider 109 to CL as described above.
The frequency of the divided clock input to the V servo circuit 108 is 7.35 KHz of the master clock input from the first oscillator 120 (# 1) through the clock selection circuit 119 when the reproduction speed of the CD is the standard speed. Fully locked to the frequency of. At this time, the frequency of the bit clock input to the frequency divider 109 is 7.35kHz × 588 = 4.3218MHz. Then, this bit clock has accuracy and stability comparable to the frequency of the crystal oscillator used as a reference. Of course, the linear velocity of each track of the CD 101 during reproduction is always kept constant.

Further, in synchronization with the control of the drive system described above, the master clock from the first oscillator 120 (# 1) corresponding to the standard reproduction speed is supplied to the signal processing circuit 115, the L / R separation circuit 116 and D. By being supplied to the / A converters 117L and 117R, the reproduction processing of the digital audio signal accurately corresponding to the standard reproduction speed is executed.

On the other hand, when the reproduction speed is changed in the CD operating unit 114, another clock output from the other second or third oscillator 120 (# 2 or # 3) to the clock selection circuit 119. Lets you select a clock signal that has a frequency,
This master clock changes the processing speed of each circuit.

That is, normally, the lock range of the PLL is about a few percent of the input frequency of the phase comparator, but if this input frequency is changed, the output frequency of the PLL in the locked state becomes It can be changed arbitrarily. Therefore, by changing the clock frequency of the master clock to the CLV servo circuit 108, the reproduction speed of the CD can be changed while maintaining the locked state.

In synchronization with the control of the drive system described above, the second or third oscillator 120 (# 2
Or the master clock from # 3) is the signal processing circuit 11
5, L / R separation circuit 116 and D / A converter 117L,
By being supplied to 117R, the reproduction processing of the digital audio signal accurately corresponding to the changed reproduction speed is executed.

[0025]

As described above, conventionally, when changing the reproduction speed of a CD player or the like, C
The reproduction speed is changed by changing the frequency of the clock supplied to the LV servo circuit and the signal processing circuit.

As described above, the CD drive system is C
Since it is controlled by the PLL centering around the LV servo circuit 108, each part of the circuit must be adjusted in advance for each clock frequency so that a desired reproduction speed can be obtained when the clock frequency is changed. There is a problem that the configuration becomes complicated.

When the clock frequency is slowed,
Servo operation in the CLV servo circuit 108, fast-forwarding, fast-returning, or tuning operation may be delayed, and the performance of the device may be deteriorated.

On the other hand, the CD player, in particular, has a weak point that the optical pickup causes needle jumping due to a physical vibration such as a shock from the outside, and the reproduction of music is disturbed or interrupted. Although this weakness has been improved to some extent by the improvement of the damper member and the like, the needle jump could not be completely absorbed.

An object of the present invention is to make it possible to change the reproduction speed of a digital audio signal without changing the clock frequency of the drive system, and at the same time, to absorb the detection error of audio data such as a needle jump. is there.

[0030]

SUMMARY OF THE INVENTION The present invention provides a digital audio device such as a compact disc player, a digital audio tape recorder or a mini disc player which has a reading means for reading audio data from a recording medium at a predetermined speed while performing digital signal processing. A signal reproduction device is assumed.

The first aspect of the present invention has the following configuration. First, it has first and second buffer storage means for temporarily storing audio data.

First, it has the following buffer control means. That is, the buffer control means writes the audio data read at the above-mentioned predetermined speed to either one of the first and second buffer storage means at the above-mentioned predetermined speed and writes the audio data to the other buffer storage means. A control operation is performed to sequentially read out and output the audio data that has been written in the order in which the audio data was written at an arbitrary reproduction speed that is equal to or lower than the predetermined speed. At this time, the buffer control means, when executing the above-described control operation, outputs the audio data from the recording medium to the reading means when the amount of audio data written in the buffer storage means on the writing side exceeds a predetermined amount. Suspend the read operation. Further, the buffer control means causes the reading means to resume the operation of reading the audio data from the recording medium at the time when all the audio data has been read from the reading side buffer storage means, and at the same time, the writing side buffer storage means. And the buffer storage means on the read side are exchanged, and the above-mentioned write operation and read operation for each buffer storage means are restarted. At the same time as these operations, the buffer control means
During the period when an error is detected in the reading means when reading the audio data from the recording medium, the control for interrupting the writing operation of the audio data to the buffer storage means on the writing side is performed.

Next, when the reading means returns to the normal state after an error is detected during the reading of the audio data from the recording medium, the reading means reads the recording medium from the recording medium from the reading position at the time when the error is detected. It has an interruption / resumption control means for instructing a read operation of audio data. The means is a circuit for holding the absolute time data in the sub-code at the time of error occurrence and for instructing the reading means to start and restart the reproduction by the absolute time data when the normal state is restored.

The second aspect of the present invention has the following configuration. First, it has a buffer storage means for temporarily storing audio data. Next, it has the following buffer control means.

That is, the buffer control means writes the audio data read at the above-mentioned predetermined speed into the buffer storage means at the above-mentioned predetermined speed, and writes the audio data written in the buffer storage means. In order, the control operation of sequentially reading and outputting at an arbitrary reproduction speed equal to or lower than the predetermined speed is performed. At this time, the buffer control means, when executing the control operation described above,
When the amount of audio data stored in the buffer storage means exceeds a predetermined amount, the reading means temporarily suspends the operation of reading the audio data from the recording medium. Further, the buffer control means causes the reading means to restart the operation of reading the audio data from the recording medium when the amount of audio data stored in the buffer storage means falls below a predetermined amount. Simultaneously with these operations, the buffer control means controls to interrupt the operation of writing the audio data to the buffer storage means during the period when the reading means reads an audio data from the recording medium and an error is detected.

Then, it has an interruption / resumption control means similar to that of the first aspect of the present invention. Each of the above-described aspects of the present invention can be configured to further include a reproduction speed setting means for setting the reproduction speed.

[0037]

The speed at which the audio data is read from the recording medium by the reading means is fixed to a predetermined speed corresponding to, for example, twice the standard reproduction speed of the recording medium. As a result, the servo control by the drive system can be stabilized and the circuit configuration can be simplified.

In this case, since the audio data is reproduced at an arbitrary reproduction speed equal to or lower than the above-mentioned predetermined speed, the audio data read from the recording medium by the reading means is prevented from overflowing. In addition, the speed conversion of the audio data is performed by using one or two buffer storage means, and when the storage capacity of the buffer storage means is exhausted, the audio data from the recording medium is sent to the reading means. Of the audio data can be reproduced at an arbitrary reproduction speed by temporarily stopping the reading operation of No. 1 and controlling the reading unit to restart the operation of reading the audio data from the recording medium when a margin is generated again. ..

Simultaneously with the above control operation, the buffer control means suspends the operation of writing the audio data to the buffer storage means during the period when the reading means reads an audio data from the recording medium and an error is detected. In addition, the interruption resuming control means instructs the reading means to perform an operation of reading the audio data from the recording medium from the reading position at the time of error detection at the time of resuming the interruption.

By this operation, even if an audio data detection error such as a needle jump occurs on the way, the audio data will be interrupted if the normal state is restored within the time corresponding to the storage capacity of the buffer storage means. It can be played continuously without.

[0041]

Embodiments of the present invention will now be described in detail with reference to the drawings. Overall Configuration and Principle Operation FIG. 1 is a configuration diagram of a circuit block of a CD player capable of changing a reproduction speed according to the present invention.

As a difference from the conventional example of FIG. 7, first, CL
As the master clock supplied to the V servo circuit 108, a system clock having a frequency corresponding to twice the standard reproduction speed of the CD from the system clock oscillation circuit 121 is supplied. Therefore, the drive system of the CD operates at a speed corresponding to twice the standard reproduction speed.

Similarly to the drive system, the signal processing circuit 115 also performs error correction processing and de-interleaving processing in synchronization with the system clock from the system clock oscillation circuit 121 to restore each sample of audio data. .. Therefore, the output audio data is also synchronized with the system clock.

Next, the audio data output from the signal processing circuit 115 is input to the reproduction speed control circuit 123 before being sent to the L / R separation circuit 116. The reproduction speed conversion circuit 123 writes the audio data in the internal data memory in synchronization with the system clock from the system clock oscillation circuit 121, and reproduces the audio data thus written in the data memory. The L / R separation circuit 1 is sequentially read in synchronization with the frequency-variable reproduction clock from the clock oscillation circuit 123.
Output to 16. Then, the L / R separation circuit 116 and D
The / A converters 117L and 117R sequentially convert stereo audio data into analog audio data in synchronization with the reproduction clock from the reproduction clock oscillation circuit 123, and output the analog audio data. Therefore, the reproduction speed of the finally obtained audio data is synchronized with the frequency-variable reproduction clock.

Here, since the frequency of the reproduction clock is set so as not to be higher than the frequency of the system clock, in the reproduction speed control circuit 123, the signal processing circuit 115 is synchronized with the system clock per unit time.
The number of audio data written from the data memory to the data memory is equal to or more than the number of audio data read from the data memory to the L / R separation circuit 116 in synchronization with the reproduction clock per the same unit time.

Therefore, in order to prevent data overflow on the write side of the internal data memory, the reproduction speed control circuit 123, when the number of data written in the data memory reaches a predetermined number, the system control circuit 1
A pause instruction is given by the pause control signal output to the signal processing circuit 13 and the signal processing circuit 115. As a result, the system control circuit 113 puts the drive system in the pause state, and the output of audio data from the signal processing circuit 115 is temporarily stopped.

After that, the reproduction speed control circuit 123 cancels the pause instruction by the pause control signal output to the system control circuit 113 and the signal processing circuit 115 when the number of data in the internal data memory becomes large. As a result, the system control circuit 113 returns the drive system from the pause state to the reproduction state, and the output of the audio data from the signal processing circuit 115 is restarted.

On the other hand, the signal processing circuit 115 includes the CD 101.
If the audio data cannot be continuously played back due to shock to the system, the system control circuit 11
3 and the error signal output to the reproduction speed control circuit 123 are activated. As a result, the system control circuit 113
Stores the playback position at the time when the error occurred. This reproduction position is set at the EFM demodulation circuit 1 when an error occurs.
It can be recognized as the absolute time data in the subcode output from 12. In addition, the reproduction speed control circuit 123
Interrupts the operation of writing the audio data from the signal processing circuit 115 to the data memory. However, the reproduction speed control circuit 123 continues to read the audio data from the data memory.

Then, in the signal processing circuit 115, when the signal processing state returns from the error state to the normal state,
The signal processing circuit 115 returns the error signal to a logic level corresponding to a normal state. In response to this, the system control circuit 113 performs cue control based on the held information on the reproduction position at the time of occurrence of the error, and restarts reproduction of the audio data from that position. At the same time, the reproduction speed control circuit 123 restarts the writing of the audio data input from the signal processing circuit 115 from the reproduction restart position into the data memory.

As described above, in this embodiment, the reproduction speed of the audio data is changed from the reproduction clock oscillation circuit 123 while the drive speed of the CD drive system is kept at the speed corresponding to the standard reproduction speed. It can be synchronized with the recovered clock. Therefore, the frequency of the reproduction clock in the reproduction clock oscillation circuit 123 can be changed from the CD operating unit 114 via the system control circuit 113, so that the user can easily change the reproduction speed of the CD. Further, even if an audio data detection error such as a needle jump occurs in the middle, the reproduction speed control circuit 123
If the normal state is restored within the time range corresponding to the storage capacity of the internal data memory, the audio data can be continuously reproduced without interruption. Detailed Configuration and Specific Operation FIG. 2 is a detailed circuit configuration diagram of a portion centered on the reproduction speed control circuit 123 of FIG.

The reproduction speed control circuit 123 has the data memory 201 and the address counter 202 as main parts # 1 and # 2.
There are two audio data storage systems.
Then, in synchronization with the system clock from the system clock oscillator circuit 121, when the audio data from the signal processing circuit 115 is written in one storage system in synchronization with the system clock, the audio data from the other storage system is written. It is read in synchronization with the reproduction clock and is output to the L / R separation circuit 116.

Then, when the address designated by the address counter 202 reaches the address corresponding to the maximum storage capacity of the data memory 201 in the storage system on the write side, the system control circuit 113 and the signal processing circuit 115 are subjected to high-level pause control. The signal is output. Even in this state, the read-out storage system continues to read the audio data in synchronization with the reproduction clock.

After that, when the address designated by the address counter 202 reaches the address corresponding to the maximum storage capacity of the data memory 201 in the memory system on the read side, the pause control signal is returned to the low level and the writing is performed. The storage system to be read and the storage system to be read are exchanged. As a result, following the above-mentioned read operation, audio data is read from the data memory 201 of the memory system on the write side until now in synchronization with the reproduction clock.

The storage system to be written and the storage system to be read are the mode switching circuit 22.
The output from 1 is also determined by the mode switching signal. On the other hand, when the signal processing circuit 115 detects an error during signal processing of audio data, the signal processing circuit 115 sets the error signal ERR output to the system control circuit 113 and the reproduction speed control circuit 123 to a high level. As a result, the write side address counter 202 suspends the counting operation of the address data ADRS. Therefore, the writing operation of the audio data from the signal processing circuit 115 to the data memory 201 is interrupted. However, the address counter 20 on the read side
2 continues the count operation of the address data ADRS, and the read operation of the audio data from the read side data memory 201 is continuously performed.

Then, in the signal processing circuit 115, when the signal processing state returns from the error state to the normal state,
The signal processing circuit 115 returns the error signal ERR to the low level. In response to this, the address counter 2 on the writing side
02 restarts the counting operation of the address data ADRS from the interrupted value. Therefore, the data memory 20 of the audio data whose input from the signal processing circuit 115 is restarted
The write operation to 1 is restarted.

A more detailed operation for realizing the above general operation will be described below. First, when a reproduction start switch (play switch) (not shown) is pressed in the CD operating unit 114, the system control circuit 113 outputs a reset signal that is at a high level for a certain period of time. The time for which the reset signal is at the high level is preset to a time longer than the time for stabilizing the rotation of the spindle motor 102, for example.

This reset signal is input to the signal processing circuit 115 at the timing when it rises from the low level to the high level to reset the internal data processing RAM and the like, and also to each of the data memories # 1 and # 2. 201, # 1 and
Reset each content of each address counter 202 of # 2,
Further, the flip-flop circuits (F / F, hereafter the same) 207 of # 1 and # 2 are reset via the OR circuit 219.

In this state, the mode switching circuit 221 outputs a low level mode switching signal. This low level mode switching signal turns off the gates 203 of # 1 and # 2,
Turn on the gates 204 of # 1 and # 2. Gates 203 and 20
Reference numeral 4 denotes a system clock W1CK output from the system clock oscillation circuit 121 and a reproduction clock R1CK output from the reproduction clock oscillation circuit 123.
Is a circuit for allocating whether to output the # 1 storage system or the # 2 storage system. Now, gate 2 of # 1 and # 2
03 is turned off and the gates 204 of # 1 and # 2 are turned on,
The write control clock W1CK from the system clock oscillator 121 is the AND gate 209 of the # 2 storage system.
And the read control clock R1CK from the reproduction clock oscillation circuit 123 is output to the AND gate 209 of the storage system # 1.

When the reset signal at the start of the CD reproducing operation is returned to the low level, each AND gate 2 of # 1 and # 2
09, a low level reset signal is sent to the inverter 21.
The high-level signal inverted by 0 and the low-level output signal from the F / F 207 are input by the high-level signal inverted by the inverter 208.

On the other hand, since the error signal ERR output from the signal processing circuit 115 is at a low level in a state where no error is detected, the AND gates 222 of # 1 and # 2 are turned off and the output thereof is output. The outputs EA and EB inverted by the inverter 223 both become high level. EA
The signal is input to the AND gate 209 of # 1 and the EB signal is input to the AND gate 209 of # 2.

As a result, each AND gate 209 of # 1 and # 2
Is turned on, the read control clock R1CK is input to the # 1 storage system address counter 202, and is input to the write control clock W1CK # 2 storage system address counter 202.

Therefore, after the time t ₀ when the reset signal returns to the low level as shown in FIG. 3A, the signal processing circuit 115 does not detect an error and the EA signal and the EB signal are shown in FIG. 3C and
If it is at a high level as in (f), the # 1 address counter 202 outputs the # 1 address data ADRS for read control whose value sequentially increases as shown in FIG. 3 (d),
The address counter 202 of # 2 has the address data ADR of # 2 for write control whose value is sequentially increased as shown in FIG. 3 (g).
Output S.

On the other hand, the low level mode switching signal is # 1.
The gates 205 of # 1 and # 2 are turned off, and the gates 206 of # 1 and # 2 are turned on. The gates 205 and 206 are the signal processing circuit 11
The audio data output from 5 and the storage system of # 1 and # 2
Which data memory 201 is to be written to, and the audio data is read from either the data memory 201 of the storage system of # 1 or the storage system of # 2 to obtain the L / R separation circuit. This is a circuit for deciding whether to output to 116. Now, the gate 205 of # 1 and # 2
Is turned off and the gates 206 of # 1 and # 2 are turned on, the audio data from the signal processing circuit 115 is written in the data memory 201 of # 2 and the audio data output to the L / R separation circuit 116 is #. The audio data is read from the first data memory 201.

The low level mode switching signal is inverted by the inverter 215 and the high level EB signal turns on the AND gate 214 of # 2, and the low level mode switching signal is inverted by the inverter 215. The AND gate 214 of 1 is turned on. Therefore, the clock W2CK, which is the system clock output from the system clock oscillator circuit 121, is input to the # 2 data memory 201 as a write clock, and the recovered clock oscillator circuit 123 is used.
The clock R2CK, which is the reproduction clock output from, is input to the # 1 data memory 201 as a read clock.

The clock W1CK, the address data ADRS for write control which increases in synchronization with the clock W1CK, and the clock W
The relationship of 2CK is shown in FIGS. 4 (a), (b) and (d), and the relationship between the clock R1CK and the address data ADRS for read control which increases in synchronization with it and the clock R2CK is shown in FIG. g) and (h). W1 as shown in FIG.
The phases of CK and W2CK and R1CK and R2CK are each shifted by 180 degrees.

Therefore, at the timing when the clock W1CK rises from the low level to the high level, the address data ADRS increases like n-1, n, n + 1, n + 2, ... Audio data is written to the data memory 201 at the timing when W2CK rises from low level to high level. Similarly, at the timing when the clock R1CK rises from the low level to the high level, the address data ADRS is m-1, m, m + 1, m + 2, ...
As described above, the audio data is read from the data memory 201 at the timing when the clock R2CK in which each address data is fixed and rises from the low level to the high level.

As a result of the above operation, after the time t ₀ when the reset signal returns to the low level as shown in FIG. 3A, the audio data group A from the signal processing circuit 115 is shown in FIG. 3G. As shown in FIG. 3 (j), the data is sequentially written in the data memory 201 of # 2 based on the address data ADRS of # 2 which is sequentially increased in synchronization with the clock W1CK from the system clock oscillation circuit 121. go. In parallel with this, from the # 1 data memory 201, FIG.
As shown in (d), the audio data group of silence (amplitude 0) is generated based on the address data ADRS of # 1 which is sequentially increased in synchronization with the clock R1CK from the reproduction clock oscillation circuit 123, as shown in FIG. Are sequentially read and output to the L / R separation circuit 116.

The above operation continues, and the address counter 202 of # 2 designates in the storage system on the write side of # 2.
# 2 address data ADRS has # 2 data memory 201
Upon reaching the time t ₁ indicating an address corresponding to the maximum storage capacity of the carry CR from # 2 address counter 202 as shown in FIG. 3 (h) is output. The carry CR is input to the AND gate 211 of # 2, and the high level signal obtained by inverting the low level mode switching signal by the inverter 217 is input. As a result, # 2 F / F
207 is set, and its output rises from low level to high level. This signal is output to the system control circuit 113 and the signal processing circuit 115 via the OR circuit 220 as a pause control signal as shown in FIG.

As a result, after the time t ₁ , the system control circuit 113 puts the drive system into the pause state, and the output of the audio data from the signal processing circuit 115 is temporarily stopped as shown in FIG. 3 (j).

The output of the F / F 207 of # 2, which has changed to the high level at time t ₁ , is inverted by the inverter 208 of # 2, and the low level signal obtained as a result turns off the AND gate 209 of # 2. As a result, the # 2 address counter 202 outputs the carry CR, changes to the reset state by itself, and then enters a state in which the count-up operation is stopped as shown in FIG. 3 (g).

On the other hand, in the storage system on the read side of # 1, the time is
Even after t ₁ , since the address data ADRS of # 1 has not reached the address corresponding to the maximum storage capacity of the data memory 201 of # 1, audio data read operation from the data memory 201 of # 1 is continued. ing.

After that, in the storage system on the read side of # 1, the time t _{2 at} which the address data ADRS of # 1 designated by the address counter 202 of # 1 indicates the address corresponding to the maximum storage capacity of the data memory 201 of # 1. Figure 3
As shown in (e), the carry CR is output from the # 1 address counter 202. The carry CR is input to the AND gate 212 of # 1, and the high level signal obtained by inverting the low level mode switching signal by the inverter 216 is input. As a result, the # 1 AND gate 21
2 is turned on, the output raised to the high level resets the F / F 207 of # 2 in the set state via the OR circuits 218 and 219, and the output falls from the high level to the low level. Therefore, the pause control signal output from the OR circuit 220 to the system control circuit 113 and the signal processing circuit 115 also returns to the low level as shown in FIG. 3 (i).

As a result, after the time t ₂ , the system control circuit 113 returns the drive system from the pause state to the reproduction state, and the output of the audio data from the signal processing circuit 115 is restarted as shown in FIG. 3 (j). To be done.

On the other hand, at time t ₂ , the mode switching circuit 2
Reference numeral 21 raises the mode switching signal from low level to high level in synchronization with the rising of the output of the OR circuit 218, as shown in FIG. 3 (b).

This high level mode switching signal is
The gate 203 of # 2 is turned on, and the gates 204 of # 1 and # 2 are turned off. As a result, contrary to the state before time t _2, the write control clock W1CK from the system clock oscillator 121 is input to the # 1 address counter 202 via the AND gate 209 of the # 1 storage system. , A clock R1 for controlling reading from the reproduction clock oscillation circuit 123
CK is input to the # 2 address counter 202 through the AND gate 209 of the # 2 storage system.

As a result, after the time t ₂ , the # 1 address counter 202 outputs the # 1 address data ADRS for writing control whose value sequentially increases as shown in FIG. The counter 202 outputs # 2 address data ADRS for read control whose value sequentially increases as shown in FIG. 3 (g).

On the other hand, the high level mode switching signal is
The gate 205 of # 2 and # 2 is turned on, and the gate 206 of # 1 and # 2 is turned off. As a result, contrary to the state before time t ₂ , the audio data from the signal processing circuit 115 is written in the data memory 201 of # 1, and the L / R separation circuit 11
Audio data output to 6 is # 2 data memory 2
The audio data is read from 01.

The high-level mode switching signal and the high-level EA signal turn on the # 1 AND gate 213, and the high-level mode switching signal turns on the # 2 AND gate 213. Therefore, the clock W2CK, which is the system clock output from the system clock oscillator circuit 121, is input to the # 1 data memory 201 as the write clock, and the clock R2CK, which is the recovered clock output from the recovered clock oscillator circuit 123, is the read clock. Is input to the data memory 201 of # 2.

As a result of the above operation, after time t ₂ , the audio data group B from the signal processing circuit 115 is sequentially synchronized with the clock W1CK from the system clock oscillation circuit 121 as shown in FIG. 3 (d). Based on the increasing # 1 address data ADRS and, as shown in FIG. 3 (j), they are sequentially written in the # 1 data memory 201.
In parallel with this, from the data memory 201 of # 2, FIG.
As shown in (g), based on the address data ADRS of # 2 which sequentially increases in synchronization with the clock R1CK from the reproduction clock oscillation circuit 123, the audio data group A written before the time t ₂ is shown in FIG. As shown in (k), they are sequentially read and output to the L / R separation circuit 116.

The above operation continues, and the # 1 address counter 202 designates the # 1 write side storage system.
# 1 address data ADRS has # 1 data memory 201
Upon reaching the time t ₃ when indicating the address corresponding to the maximum storage capacity of the carry CR # 1 of the address counter 202 as shown in FIG. 3 (e) is output. The carry CR and the high-level mode switching signal are input to the AND gate 211 of # 1. As a result, the F / F 207 of # 1 is set and its output rises from low level to high level. This signal is output to the system control circuit 113 and the signal processing circuit 115 via the OR circuit 220 as a pause control signal as shown in FIG.

As a result, after the time t ₃ , the system control circuit 113 puts the drive system into the pause state again, and the output of the audio data from the signal processing circuit 115 is temporarily stopped again as shown in FIG. 3 (j). It

The output of the F / F 207 of # 1 which has changed to the high level at time t ₃ is inverted by the inverter 208 of # 1, and the low level signal obtained as a result turns off the AND gate 209 of # 1. As a result, the # 1 address counter 202 outputs the carry CR and changes to the reset state by itself, and then becomes a state in which the count-up operation is stopped as shown in FIG. 3 (d).

On the other hand, in the storage system on the reading side of # 2, the time
Even after t ₃ , since the address data ADRS of # 2 has not reached the address corresponding to the maximum storage capacity of the data memory 201 of # 2, the read operation of the audio data from the data memory 201 of # 2 is continued. ing.

After that, in the storage system on the read side of # 2, the time t _{4 at} which the address data ADRS of # 2 designated by the address counter 202 of # 2 indicates the address corresponding to the maximum storage capacity of the data memory 201 of # 2. Figure 3
As shown in (h), the carry CR is output from the # 2 address counter 202. The carry CR and the high-level mode switching signal are input to the AND gate 212 of # 2. As a result, the AND gate 212 of # 2 is turned on, and the output which has risen to the high level resets the F / F 207 of # 1 in the set state via the OR circuits 218 and 219, and the output thereof changes from the high level to the low level. Get down to the level. Therefore, the OR circuit 22
From 0 to system control circuit 113 and signal processing circuit 115
The pause control signal output to (3) also returns to the low level as shown in FIG. 3 (i).

As a result, after the time t ₄ , the system control circuit 113 returns the drive system from the pause state to the reproduction state, and the output of the audio data from the signal processing circuit 115 is restarted as shown in FIG. 3 (j). To be done.

On the other hand, at time t ₄ , the mode switching circuit 2
Reference numeral 21 returns the mode switching signal from the high level to the low level in synchronization with the rising of the output of the OR circuit 218, as shown in FIG. 3 (b).

This low level mode switching signal is
The gate 203 of # 2 is turned off, and the gates 204 of # 1 and # 2 are turned on. Therefore, after time t ₄ , the state is the same as that after time t ₀ , and the audio data group C from the signal processing circuit 115 receives the clock W1CK from the system clock oscillation circuit 121 as shown in FIG. 3 (g). As shown in FIG. 3 (j), based on the address data ADRS of # 2 and sequentially increasing in synchronization with
Will be written in sequence. In parallel with this, from the # 1 data memory 201, based on the # 1 address data ADRS, which sequentially increases in synchronization with the clock R1CK from the reproduction clock oscillation circuit 123, as shown in FIG. 3 (d). , The audio data group B written before time t ₄ is sequentially read out as shown in FIG.
It is output to the separation circuit 116.

By the operation described above, the reproduction clock oscillation circuit 1 is operated by the operation of the CD operating section 114 while the speed of the drive system is kept at the speed corresponding to the standard reproduction speed.
By changing the clocks R1CK and R2CK output from 23, it is possible to arbitrarily change the reproduction speed of the audio data. In this case, the speed of the drive system is C
The playback speed of the audio data can be set to a speed corresponding to twice the standard playback speed of D, and the playback speed of the audio data can be set to a range equal to or lower than the standard playback speed of the CD. It can be set to a wide range from above the standard playback speed to below the standard playback speed.

Next, the operation when an error is detected in the signal processing of the audio data in the signal processing circuit 115 will be described. First, the control mechanism for outputting the pause control signal from the reproduction speed control circuit 123 to the system control circuit 113 and the signal processing circuit 115 is exactly the same as when the above error is not detected.

Now, after the time t _{0 in} FIG. 5, the signal processing circuit 11
The audio data from 5 sequentially increases in synchronization with the clock W1CK from the system clock oscillation circuit 121.
Based on the address data ADRS of # 2 and are sequentially written in the data memory 201, the recovered clock oscillation circuit 12
The data memory 2 of # 1 based on the address data ADRS of # 1 which sequentially increases in synchronization with the clock R1CK from 3
When the audio signal is sequentially read from 01 and is output to the L / R separation circuit 116 at time t ₁ , the signal processing circuit 115 outputs a high-level error signal ERR. The switching signal and the signal inverted by the inverter 224 turn on the AND gate 222 of # 2, and the EB signal becomes low level as shown in FIG. 5 (f).

As a result, the AND gate 209 of # 2 is turned off, and the address counter 202 of # 2 interrupts the counting operation of the address data ADRS of # 2 at the same time, as shown in FIG. 5 (g). The AND gate 214 of # 2 is turned off, and as shown in FIG. 5 (j), the writing operation of the audio data group A to the data memory 201 of # 2 is interrupted. On the other hand, since the EA signal remains high level,
The AND gate 209 of # 1 remains ON, as shown in FIG. 5 (d).
As shown in, the # 1 address counter 202 continues the counting operation of the # 1 address data ADRS, and at the same time, R2CK is continuously input to the # 1 data memory 201 through the # 1 AND gate 214. As shown in FIG. 5 (k), the audio data is continuously read from the # 1 data memory 201.

After that, at time t ₂ , when the error signal ERR returns to the low level from the signal processing circuit 115, the AND gate 222 of # 2 returns to OFF, and the EB signal goes high as shown in FIG. 5 (f). Return to the level.

As a result, the AND gate 209 of # 2 returns to ON, and the address counter 202 of # 2 restarts the counting operation of the address data ADRS of # 2 at the same time as shown in FIG. 5 (g). The AND gate 214 of # 2 also returns to the ON state, and the writing operation of the audio data group A to the data memory 201 of # 2 is restarted, as shown in FIG. 5 (j).

In parallel with the operation of the reproduction speed control circuit 123 as described above, the system control circuit 113 executes the control operation shown in the operation flowchart of FIG. It should be noted that this operation flowchart is based on the system control circuit 11
3 is realized as an operation for executing a control program stored in a ROM (not shown).

First, the system control circuit 113 monitors the state of the error signal ERR from the signal processing circuit 115 in step S1. If the error signal ERR is low level and no error has occurred, the determination in step S1 is made. Is N
When it becomes O, the process proceeds to step S2, and the absolute time data ABS in the sub-code currently output from the EFM demodulation circuit 112 is stored in the register T not shown here.

Next, when an error occurs at time t ₁ in FIG. 5 and the error signal ERR becomes high level, the determination at step S1 becomes YES and the process proceeds to step S3, at which the error is waited for release. Becomes

Then, at time t ₂ in FIG. 5, when the error signal ERR returns to the normal state and the error signal ERR returns to the low level, the determination in step S3 becomes YES and the process proceeds to step S4, where the register T is held. The cue control of the CD is performed by the absolute time data ABS corresponding to the interrupted reproduction position, and the reproduction of the CD is restarted.

By the control operation as described above, at time t ₂
At the time when the writing operation of the audio data group A to the data memory 201 of # 2 is restarted, continuous audio data from the time when the reproduction is interrupted at time t ₁
It will be written to consecutive addresses on 01.

In the error period between the times t ₃ and t ₄ , the same control operation is performed as in the error period between the times t ₁ and t ₂ . On the other hand, after time t _{5 in} FIG. 5, the audio data from the signal processing circuit 115 is changed to the system clock oscillation circuit 121.
Data memory 20 based on the address data ADRS of # 1 which sequentially increases in synchronization with the clock W1CK from
1 is sequentially written, and audio data is sequentially read from the # 2 data memory 201 based on the # 2 address data ADRS which is sequentially increased in synchronization with the clock R1CK from the reproduction clock oscillation circuit 123, and the L / R separation circuit 11
At a time t 6 during the output to ₆ , the signal processing circuit 115 outputs a high level error signal ERR, and the AND gate 222 of # 1 is turned on by this signal and the high level mode switching signal, As shown in FIG. 5 (c), the EA signal becomes low level.

As a result, the AND gate 209 of # 1 is turned off, and the address counter 202 of # 1 interrupts the counting operation of the address data ADRS of # 1 at the same time as shown in FIG. 5 (d). The AND gate 213 of # 1 is turned off, and as shown in FIG. 5 (j), the writing operation of the audio data group B to the data memory 201 of # 1 is interrupted. On the other hand, since the EB signal remains high level,
The AND gate 209 of # 2 remains ON, as shown in FIG. 5 (g).
As shown in, the # 2 address counter 202 continues the counting operation of the # 2 address data ADRS, and at the same time, R2CK is continuously input to the # 2 data memory 201 via the # 2 AND gate 213. As shown in FIG. 5 (k), the reading of the audio data group A from the # 2 data memory 201 is continued.

After that, at time t ₇ , when the error signal ERR returns from the signal processing circuit 115 to the low level, the AND gate 222 of # 1 returns to OFF, and the EA signal goes high as shown in FIG. 5 (c). Return to the level.

As a result, the AND gate 209 of # 1 returns to the ON state, and the address counter 202 of # 1 restarts the counting operation of the address data ADRS of # 1 at the same time as shown in FIG. 5 (d). The AND gate 214 of # 1 also returns to the ON state, and as shown in FIG. 5 (j), the writing operation of the audio data group B to the data memory 201 of # 1 is restarted.

The operation of the system control circuit 113 at this time is exactly the same as the operation in the error period between the times t ₁ and t ₂ described above. As can be understood from the above description,
Even if an audio data detection error such as a needle jump occurs during reproduction, the time until the address data ADRS on the write side reaches the address corresponding to the maximum storage capacity of the data memory 201 after returning to the normal state, As long as the read side address data ADRS does not exceed the time required to reach the address corresponding to the maximum storage capacity, the reproduction speed of the audio data can be arbitrarily changed, and at the same time, the audio data can be continuously changed without interruption. Can be played. Other Embodiments In the above-described embodiments, although the reproduction speed control circuit 123 is provided with two systems of storage mechanisms, if a data memory of a type capable of simultaneously writing and reading data is used, one system is provided. With this storage mechanism, the same function as in the case of the above-described embodiment can be realized. In this case, the drive system may be instructed to pause when the amount of audio data stored in the data memory exceeds a predetermined amount, and the pause may be canceled when the amount of audio data falls below the predetermined amount. .

Although the above-described embodiment is an embodiment in which the present invention is applied to a compact disc player, the present invention is not limited to this, and a digital audio tape recorder (DAT) and current standardization are proceeding. The present invention can be widely applied to digital audio signal reproducing devices such as existing mini disc players.

[0105]

According to the present invention, the speed at which the reading means reads the audio data from the recording medium can be fixed to a predetermined speed, so that the servo control by the drive system can be stabilized and the circuit can be stabilized. It is also possible to simplify the configuration.

In this case, when reproducing the audio data,
The control operation for temporarily suspending or resuming the operation of reading the audio data from the recording medium to the reading means can be realized as a control operation for giving a normal pause instruction or a pause release instruction to a CD or the like.
It is possible to realize a reproduction speed conversion mechanism without significantly changing the circuit configuration of the device or the like.

Further, in the present invention, even if an audio data detection error such as a needle jump occurs during the process, if the audio data is restored to the normal state within the time range corresponding to the storage capacity of the buffer storage means, the audio data will not be output. It can be played continuously without interruption.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an embodiment of a CD circuit block according to the present invention.

FIG. 2 is a detailed circuit configuration diagram of a portion centered on a reproduction speed control circuit.

FIG. 3 is an operation timing chart (No. 1) of the reproduction speed control circuit.

FIG. 4 is an operation timing chart (No. 2) of the reproduction speed control circuit.

FIG. 5 is an operation timing chart (No. 3) of the reproduction speed control circuit.

FIG. 6 is an operation flowchart of a system control circuit.

FIG. 7 is a block diagram of a conventional CD circuit block.

[Explanation of symbols]

101 CD 102 Spindle Motor 103 Optical Pickup 104 Focus Servo Circuit 105 Tracking Servo Circuit 106 Feed Motor 107 Feed Servo Circuit 108 CLV Servo Circuit 109 Frequency Divider 110 Data Extraction Circuit 111 Frame Synchronization Circuit 112 EFM Demodulation Circuit 113 System Control Circuit 115 Signal Processing Circuit 116 L / R separation circuit 117L, 117R D / A converter 118L, 118R Low pass filter (LPF) 121 System clock oscillation circuit 122 Regenerated clock oscillation circuit 123 Reproduction speed control circuit 201 Data memory 202 Address counter 203, 204, 205, 206 gate 207 flip-flop circuit (F / F) 208, 210, 215, 216, 217, 223, 2
24 Inverters 209, 211, 212, 213, 214, 222
AND gates 218, 219, 220 OR circuit 221 Mode switching circuit 221

Claims (3)

[Claims] 1. A digital audio signal reproducing apparatus having a reading means for reading audio data from a recording medium at a predetermined speed while performing digital signal processing, wherein first and second buffer memories are provided for temporarily storing the audio data. Means for writing audio data read at the predetermined speed to either one of the first or second buffer storage means at the predetermined speed and the audio data written to the other buffer storage means. Is performed in the order in which it is written, and the control operation is performed to sequentially read and output at an arbitrary reproduction speed that is equal to or lower than the predetermined speed, and when the control operation is executed, the amount of the audio data written in the buffer storage unit on the writing side. At a time when the value exceeds a predetermined amount, the reading means reads the recording medium from the recording medium. The audio data read operation is temporarily stopped, and when all the audio data is read from the read side buffer storage means, the read means restarts the audio data read operation from the recording medium and the write operation is performed. Side buffer storage means and the read side buffer storage means are exchanged to perform control to restart the write operation and the read operation for each of the buffer storage means, and at the same time, the read means reads the audio data from the recording medium. Of the audio data from the recording medium in the reading means, the buffer control means performing control for interrupting the writing operation of the audio data to the buffer storage means on the writing side during a period in which an error is detected during reading. An error was detected during reading And an interruption / resumption control means for instructing the reading means to read the audio data from the recording medium from the read position at the time of error detection when the reading means returns to the normal state later. Digital audio signal playback device. 2. A digital audio signal reproducing apparatus having a reading means for reading audio data from a recording medium at a predetermined speed while performing digital signal processing, a buffer storage means for temporarily storing the audio data, and the predetermined memory. While writing the audio data read at a speed to the buffer storage means at the predetermined speed,
A control operation of sequentially reading and outputting the audio data written in the buffer storage means in the order in which the audio data is written at an arbitrary reproduction speed equal to or lower than the predetermined speed is performed, and the buffer storage is executed when the control operation is executed. When the amount of the audio data stored in the means exceeds a predetermined amount, the reading means temporarily suspends the operation of reading the audio data from the recording medium, and is stored in the buffer storage means. When the amount of the audio data falls below a predetermined amount, the reading means is controlled to restart the operation of reading the audio data from the recording medium, and at the same time, the audio data from the recording medium is read in the reading means. When an error is detected during the reading of the Buffer control means for controlling to interrupt the writing operation of audio data, and to the reading means when the reading means returns to a normal state after an error is detected when reading the audio data from the recording medium. An interruption / resumption control means for instructing an operation of reading the audio data from the recording medium from a read position when an error is detected, a digital audio signal reproducing apparatus. 3. The digital audio signal reproducing apparatus according to claim 1, further comprising a reproducing speed setting means for setting the reproducing speed.