JPH0786863B2 - Processor access control device for multi-processor system - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to multiprocessors, and more particularly to an apparatus for controlling access to a processor in a multiprocessor system.

BACKGROUND OF THE INVENTION A multiprocessor system typically consists of multiple interconnected processors cooperating to accomplish a data manipulation job. As a result, a large number of data messages are interchanged among the processors on a compliant basis. It has long been recognized that this interprocessor communication is a bottleneck that wastes computing time in the system and reduces the ability to process computational jobs. By convention, data transfer between two processors is initiated by the processor preparing to send a data message.
The transmitting processor first requests access to a common bus interconnecting the system processors and then transmits the message on the bus with the identity of the intended receiving processor after bus access is granted. A great deal of effort is devoted to solving bus access problems, and some technical solutions are known to deal with bus access requests on a priority basis which minimizes access delays resulting from competing access requests. Has been. Some bus access devices guarantee "fair" access to the bus, where they provide access on a priority basis, but low priority processors are not allowed to be excluded for unusually long periods of time. Has become. However, the prior art has not been successful in the problem of fair access to the receiving processor after access to the bus has been gained by the message sending processor. A transmitting processor in a multiprocessor system may find that the receiving processor cannot receive the data message after waiting for access to the bus. In prior art systems, the transmitting processor would then have to reattempt to gain access to the bus and again be denied access to the receiving processor. If this happens often, it may prevent a particular processor from accomplishing its task for an abnormally long time and potentially permanently. This repeated rejection is a system problem and reduces the system's ability to handle data.

SUMMARY OF THE INVENTION This problem is solved by the present invention. In the present invention, data communication between processors in a multiprocessor system records the identity of a data sending processor that has been denied access to a data receiving processor, and other access to the receiving processor of the denied sending processor. Better by allowing prior to competing processors. According to one aspect of the invention, the identities of each of the processors for which data transfer access to the intended receiving processor is denied are recorded in the address buffer in the order in which the data transfer access attempts are made. A request for retransmission is sent to the first processor whose identity is identified in the address buffer when the receiving processor is available to receive additional data messages.
Upon completion of receiving data messages from rejected processors, resends of message requests are sent to other processors identified by address in a buffer in the order in which they were stored.

Preferably, the device is granted access on a priority basis to provide an interprocessor device in which data transfer access to the intended receiving processor is guaranteed within a reasonable period of processor acquisition access to the bus. Can be used in multiprocessor systems employing a single interconnect bus.

In a particular embodiment of the invention, the processors of a multiprocessor system are interconnected by means of buses which are granted access on a priority basis. When the data is transferred by one of the processors connected to the bus, the data is accompanied by the origin address as well as the destination address. Each receiving processor of a multi-processor system receives data from the bus and by the processor with an address buffer for sequentially accumulating the identity of each of the other processors whose data transfer access has been denied by the intended receiving processor. It has an associated receive buffer that is emptied. If the receive buffer is full or an entry appears in the target receiver's address buffer, no further data messages will be accepted. Under that circumstance, a negative acknowledgment is sent to each processor that cannot send an accepted message and the address of each such processor is filled in the address buffer. If the receive buffer becomes empty while the rejected processor's identity remains in the address buffer, the intended receiver of the original message will request access to the bus, and its grant access will grab the bus. . The message request resend will be sent via the captured bus to the processor identified by the youngest outstanding entry in the address buffer. The processor that receives the message then sends the data on the bus it grabbed.

Preferably, in the system according to the invention, the data processing capacity of the multiprocessor system is significantly increased. Calculations have shown that in a system having 10 or more processors handling tasks requiring 2 or more processors, the apparatus of the present invention provides an approximately 20% improvement in the data handling capacity of the system.

Description of Embodiments FIG. 1 shows a processor 1 connected to an interprocessor bus 150 via bus interface circuits 110 and 145, respectively.
Shows 01 and 140. FIG. 2 shows corresponding devices in which processors 201 and 240 are connected to bus 150 by processor interface circuits 210 and 245, respectively. For purposes of explaining the principles of the invention, only four processors and corresponding interconnection circuitry are shown connected to bus 150. For example, multiple processors of ten or more may be connected to the bus using the bus interface circuits described herein to interface each of the processors with the interconnect bus. Processors 101, 201 and other processors can be any number of different processor systems capable of communicating with bus 150 via circuits such as the bus interface circuits described herein.

The interface circuits 110, 145, 245 and 210 are said to be identical. Interface 11 as shown in FIG.
Each of the 0 blocks is an interface circuit 210 of FIG.
Correspondingly named blocks in will be described as being identical and performing corresponding functions. The interface circuit 110 has a reception FIFO 121 and a transmission FIFO.
It includes a data buffer unit 120 composed of 123.
Interface circuit 110 or control unit 114, control register 113, status register 116 and end of packet (EO
P) Includes register 117. These devices are processor 101
Used in communication between the interface circuit 110 and the interface circuit 110. Processor 101 is transmit FIFO 123, control register 11
3 and write access to the EOP register 117, and read access to the status register 116 and the receive FIFO 121. Devices such as the FIFO and the three registers are in the address space of the processor and can be addressed via its memory address bus. In that case, the processor bus 103 of FIG. 1 is simply an extension of the memory bus of the processor 101. Alternative bus arrangements, for example using a processor peripheral bus, can likewise easily be envisaged. Control unit 11
4 is (a) reception FIFO121 or transmission FIFO123, or (b)
A read or write strobe from the processor 101 will be received via the connection to the bus 115 when the status register 116, or (a) the control register 113, or (d) the EOP register 117 is addressed. Control unit 114 examines the two preselected bits of the address and selects one of the four addressables to control access from processor 101 to the addressed device in a standard manner known in the art. Finite state machine P may be used by similar logic to implement separate control of FIFO and state, control and read and write access to the FOP register. The circuits and logic for accomplishing these operations are well known and will not be described in detail here. The control units 114 and 214 include a field programmable logic array (EPLA) and a field programmable logic shift register (FPLS) for implementing the decoder and finite state machine required to encode the address information. All of these devices are commercially available and their use to achieve the desired function is well known.

When processor 101 attempts to send a data packet to another processor, it writes the data word of the packet to transmit FIFO 123, referred to herein as the transmit buffer. The last word of the packet is sent to the EOP register 117 which marks the end of the packet. The data word in this exemplary system consists of 32 bits and the transmit buffer as well as the receive buffer are 32 bits wide. Well-known data latch 13
Zero is provided between the transmit buffer and the bus to compensate for the timing difference between the buffer and the bus. But EOP
Register 117 and send buffer 123 are 33 bits wide and the contents of the EOP register are transferred to send buffer 123 with an extra bit indicating the end of the packet. EOP register 117
Also indicates that the end of the packet has been written
Generate the EOPW output signal. This signal informs the control unit 114 that the last word of the packet has been received. In addition, the EOPW signal is sent to the control unit 114 via the PR gate 129 to initiate contention for the interconnect bus 150. With the transmission of the data packet to the transmit FIFO 123, the processor 101 also sends a 7-bit identity code to the control register 113. This is the identity or address of the processor to which the packet should be sent. Once access is obtained to bus 150, the contents of control register 113 are placed on bus 150 as the destination address along with the data word obtained from transmit FIFO 123 and the source address obtained from ID register 112. This last named register contains a 7-bit identity code for the bus interface circuit 110. The data word is transmitted on the 32-bit DATA bus 152, the destination address is transmitted on the 7-bit ID bus 153 and the origin address is transmitted on the 7-bit FROM bus 156. All of these buses are part of bus 150.

When another processor, such as processor 201, transfers the data word to processor 101, the data word is received by the FIF.
It is stored in O121. The last word of the packet is the EOP lead 154 of bus 150 with which it is stored in the receive FIFO 121.
With the above signal. The processor 101 will read the data from the receive FIFO 121 and the control unit 114 will make a corresponding entry in the status register 116 when the last word of the packet is read. The control unit 114 will inhibit further reading of the receive buffer until the processor 101 reads the status register.

As shown in FIGS. 1 and 2, the interconnection bus 15
0 includes a multi-bit PRIORITY bus 151 to which an arbitration circuit is connected in each of the interface circuits 110, 210 and in other interface circuits that may be connected to the bus. Bus arbitration can be accomplished by any of several well-known bus arbitration schemes that allow bus access on a priority basis. One known bus device is the standardized S-100 bus, for which an arbitration protocol has been defined. The arbitration circuits 111, 211 can be well-known arbitration circuits such as those defined on the S-100 bus, or similar circuits that select several competitors and give a grant signal to the highest priority competitor. The PRIORITY bus 151 is a 7-bit bus having 7 priority reads. Such a device is S-10
Regarding 127 different processors using 0 arbitration circuit
It can be logically used to define 127 different priorities. The arbitration circuits 111, 211 and those in other interface circuits such as interfaces 140, 240 are PRIORI
Connects to all seven leads of the TY (Priority) bus.
The arbitration circuit 111 receives a unique 7-bit identity word from the ID register 112. This identity word defines the identities of processor 101 and bus interface circuit 110 as well as the priority for the purpose of bus access. The arbitration circuit is a PRIO via an open collector logic gate or the like.
Some of the RITY leads are held in a pre-defined logic state (eg logic zero) to define the priority of the associated processor 101. The arbitration circuit 111 grants an appropriate grant signal to the control unit 114 to grant access to the DATA bus 152 only if there is no higher priority processor defined by the status of the priority read.

The control unit of each bus interface circuit includes a finite state machine that controls the reading or receiving of data from the bus and a finite state machine that controls the writing or sending of data to the bus. A transmitting processor, such as the processor 201, may send DAT through its bus interface circuit 210.
Get access to the A bus 152 and for example the processor 101
Data with the identity of the receiving processor and the identity of the originating processor 201. In the bus interface circuit 101, the ID matching circuit 122 monitors the ID bus 153 and compares it with the address defined in the ID register 112. When the address of the processor 101 is recognized, the data latch 125 is energized by the match signal from the match circuit 122 and the enable signal from the control unit 114 to transfer the data from the bus to the receive buffer 121.

FIG. 5 shows the states of the finite state machine that controls the bus receive operation as embodied in the control unit (114, 214) of each of the bus interface circuits connected to the bus 150. The operation is a bus interface circuit
Only with respect to 110, the operation is similar in the interface circuit 210 and others. The initial state of the finite state machine is the open receive state 510. In this state, the energizing signal is provided to the data latch 125 and the data transfer from the bus to the receive FIFO 121 is done on the ID bus 153.
It occurs as long as the address above matches the contents of the ID register 112. Under conditions other than buffer overflow,
No change from the open receive state is required. FIFO12
1 and 123 are standard market-acceptable FIFOs, which end-of-packet with the usual "buffer full" and "buffer empty" indications and receive buffer full status.
It is provided before the reception of a signal is interpreted as an overflow condition. The control unit 114, in the open reception state 510, reads the reception buffer 121 and the EOP of the bus 150
Monitor 154 for "buffer full" and "buffer empty" indications. In normal operation, the processor 101 reads a data word from the receive FIFO 121 at a slower rate than the transfer rate of the data bus 152 and describes the receive buffer overflow condition in the processor 101, which may be in the absence of an abnormal condition. In the figure, the control unit 114
The lead which provides the buffer level status signal to is shown as the output from the buffer unit 120 for simplicity. The control unit 114 also makes an appropriate entry in the status register 116 which reflects the status of the buffer pointer. The occurrence of the receive buffer full indication before the EOP signal for the associated packet has been received on EOP lead 154 indicates that all or part of the packet has not been successfully accumulated in the receive buffer. In that case, the finite state machine remains in the open receive state, but the negative acknowledgment signal SNACK is sent by the control unit 114 onto the SNACK lead 155 of the bus 150. This SNACK signal will be received by the data transmission circuit, eg 210. Each of the bus interface units is labeled RFGF
It consists of FIFO. This is indicated by block 118 in FIG. 1 and block 218 in FIG. RFGF FIFO like any other FIFO used in the system
Is a standard market-acceptable device which produces standard "buffer full", "buffer empty" status signals. Data latches (127,227,131,231) are provided to compensate for the timing difference between the FIFO and the bus. In this exemplary system, the processor transmitting the data packet is
The destination address is sent on the ID bus 153, and the origin address for identifying the transmitting processor is sent on the FROM bus 156. When a receive buffer overflow condition is detected, the control unit 114 activates the RFGF FIFO 118 to store the originating address on the FROM bus 156, as indicated by the receive buffer full indication. Referring to FIG. 5, the FIFO is transmitted along with the transmission of the SNACK signal.
The accumulation of the contents of the inside FROM bus occurs in the open receive state 510. Upon completion of this action, a transition is made to RFG state 512 with the RFGF buffer not empty. RFG status 512
At, the control unit 114 monitors the receive buffer status read with the output of the matching circuit 122. When the matching circuit 122 indicates the occurrence of the identity of the processor 101 on the ID bus 153 in state 512, the control unit 114 again energizes the RFGF FIFO 118 to FRO.
Store the originating address on M Bus 156 and SNACK
Send a signal. This occurs as many times as another processor attempts to transfer data to processor 101 while the bus receive finite state machine is in RFGF state 512.

When the receive FIFO 121 is empty and the RFGF FIFO 118 is not empty, AND gate 128 is activated and its output is OR gate 12
It is transmitted via 9 to generate the IWANT signal. This signal is sent from the controller 114 to the arbitrator 111, which initiates a race for access to the bus on the next opportunity to cause the controller 114 to send a retransmission request to the first processor identified in the RFGF buffer. In this exemplary system, the arbitration device is such that any arbitration device competing for the bus in any one bus cycle will be activated in subsequent bus cycles before the arbitration device is allowed to seize the bus. Is configured to provide fair access to the bus in a manner. An apparatus for implementing such a bus rate system is disclosed in U.S. Pat. No. 4,514,728, which is referred to as a "storage group bus rate system." In the sense of exemplifying the invention, any suitable standard arbitration scheme may be employed. With the so-called fair access plan,
The interface circuits in the connection to the bus are bus 15
Claims 0 BST lead 160. This lasts for a few bus cycles and other circuits will not try to compete for the bus as long as the BST lead is claimed. It is CONTEND lead 161 when the bus interface circuit is in competing process
HOLD reed 159 is asserted when the bus is seized.

Both control units 114 and 214 embody the bus transmit finite state machine shown in FIG. 4 along with the bus receive finite state machine in FIG. The sequence shown in FIG. 4 is used to transfer data from the transmit buffers 123,223 to the bus. It is also used to control the transmission of a resend request to a processor, such as processor 201, for which the data transfer access of another processor, such as processor 101, has been denied. The transmission of this message from processor 101 will be described. Similar actions will occur with other bus interface circuits under similar conditions. IWA at the output of OR gate 129 above
Upon the generation of the NT signal, the finite state machine moves from its IDLE state 401 to the READY state 402. This last named state is used as the sync state because the IWANT signal is not synchronized with the timing of the control unit 114 synchronized with the bus 150. If the BST lead asserts that one or more other arbitrators are competing for the bus, the transition is a READY state 402
From WAIT-1 state 403. If the finite state machine is in READY state 402 or WAIT
If the BST lead is not asserted while in the -1 state 403, the transition moves to the CONTEND-1 state 404. The arbitrators 111, 211 and others connected to the bus provide their identities to the PRIORITY bus 151 and the identities of the higher priority arbitrators are PRIO.
When it is on the RITY bus 151, the priority is decided by withdrawing it. In such a device, depending on the electrical delay of the physical circuit, it may take one or more bus cycles to resolve the connection to the bus, perhaps 3-5 bus cycles. In Figure 4, this is CO
A dotted line is shown between NTEND-1 state 404 and CONTEND-N state 414. The actual number of CONTEND states is a matter of design choice depending on the physical parameters of the system. In any case, if the arbitration device 111 did not send a WON signal to the control unit 114 indicating that access was granted, by the time normally required to resolve the contention on the bus, the transition would be WAIT-2. Will be made to the state. The control unit 114 monitors the CONTEND lead 161 of the bus 150, and when this lead is no longer asserted, the transition will be made from the WAIT-2 state 405 to the CONTEND-1 state 404. In the sequence through the CONTEND state and the WAIT-2 state, the arbitration device 111 sends a WO to the control unit 114.
It will be repeated until the N signal is given. Control unit 114
Will also monitor HOLD lead 159 on bus 150. This lead has been claimed by the bus interface circuit that has gained access to the bus and is sending data. As long as the HOLD lead continues to be asserted after the WON signal has been received, the bus transmit finite state machine will CONT
It will remain in END-N state 414. A transition will be made to the SEND state 406 when the HOLD lead 159 is opened. In this state, the control unit 114 will assert the HOLD lead 159 of the bus 150 which indicates the grip of the bus.

In the previous example, data was transferred from processor 201 to processor 101 and a buffer overflow was encountered. As a result, the address of processor 201 is RFG.
Stored in the F-buffer 118 and the buffer provided the control unit with the RFGF signal to indicate the non-empty state of the buffer.
Under these conditions, the transition is from SEND state 406 to RFGF state 410.
It will be done. In this state, the control unit 11
4 energizes RFGF buffer 118 to send the first address in the FIFO to ID bus 153 via data latch 127 and FIF
Delete the entry from O. At the same time, control unit 114 will send a resend request by asserting SENDRQ lead 157 on bus 150. This Reed's assertion will be recognized as a resend request by other processor interface circuitry, such as 214. After one cycle in state 410, the transition will be made to IDLE state 401 and HOLD lead 159 will no longer be asserted. As described below,
Bus grabbing by controller 114 will be understood by the controller (eg, 214) receiving the resend request. Therefore, the processors denied access earlier in the interface circuit 110 need not separately contend for bus access after receiving the resend request.

The control unit 214 of the bus interface circuit 210 shown in FIG. 2 contains the same finite state machines as those of the control unit 114. In the example above, processor 201 was sending a data message to processor 101. A buffer overflow condition was encountered in the interface circuit and a negative acknowledge signal SNACK was sent to interface circuit 210 on lead 155 of bus 150. Processor 201
In sending the original data message from the associated interface control unit 214 has progressed from the IDLE state 401 of the bus transmit finite state machine shown in FIG. 4 to the SEND state 406. The transition from the IDLE state is caused by the IWANT signal generated by OR gate 229. When data is to be sent from processor 201 to processor 101, the data packet will have the last word of the packet in EOP register 2
It is transferred to 17 and stored in the transmission FIFO 223. EOP
The register provides the OR gate 229 with an end of packet signal EOPW so that the IWANT signal is generated. In response to the IWANT signal, the bus transmit finite state machine of controller 214 as shown in FIG.
Will move to the READY state 402 and then through the CONTEND state to the SEND state 406. This action is the same as that described above with respect to FIG. 4 and the bus conflict and bus grasp action of the control unit 114.

The control unit 214 will transfer the data word from the transmit FIFO 223 to the data bus 152 in the SEND state 406. It also transfers the destination identity on ID bus 153 and the origin identity on FROM bus 156. Control unit 214 is bus 150
SNACK lead 155, and when the data receive interface circuit (eg 110) asserts this lead, the bus transmit finite state machine changes from SEND state to SNACK state 407 and stops further transmission of data from FIFO 223. To do. That is, the time period will elapse between when the SNACK signal is sent by the receive bus interface 110 and when the retransmission request is initiated. The bus transmit finite state machine in control unit 214 is the SEN of bus 150 during this time period.
DRQ lead 157 will remain in state 407 until asserted by the processor sending the SNACK signal. This SENDRQ signal generated by the control unit 114 described above contains RFGF
Accompanied by the destination address on ID bus 153 obtained from buffer 118 and the origin address on FROM bus 156. In interface circuit 210, matching circuit 222 will provide a DEMATCH output signal to data latch 225 and control unit 214 when the identity on bus 153 matches the contents of ID register 212, which stores the identity of processor 201. . Similarly,
The matching circuit 226 controls the address on the FROM bus to the control register 213.
Would compare to the address in. Note that the control register contains either the contents of the transmit buffer or the address of the processor that was originally transmitted. This comparison therefore gives a check of the address at which the retransmission is initiated. ORMA
When the TCH signal is matched, it is given to the control unit 213. This information, with the claims of SENDRQ Lead 152,
Transition from SNACK state 407 to SEND in control unit 214
Causes a return to state 406. Data latch 2 in this state
25 is activated from control unit 214 and the contents of transmit FIFO 223 are sent to data bus 152. When the last word of the packet being transmitted reaches the data bus, it will be accompanied by an EOP bit indicating end of packet (end of packet). This bit is sent from the data register 225 as the 33rd bit, the 32-bit data word is sent on the data bus 152 and the EOP bit is sent on the EOP lead 154. This EOP bit is the control unit 214
Transition is made to the LAST state 408. It will be appreciated that if the SNACK signal is detected before EOP, the return to SNACK state is made again. LA
In the ST state, the transmit FIFO 223 and data latch 225 are de-energized by the control unit 214. The transition from the LAST state is made to the CLEAR state where the contents are cleared from the transmit FIFO 223.
A connection (124,224) is provided from the output of the transmit FIFO so that the contents of the FIFO are cycled during the transmit operation. This allows the packet to be transmitted to be saved if a negative acknowledgment SNACK signal is received during transmission. The FIFO is cleared in the CLEAR state when a complete packet has been successfully sent. A return from the CLEAR state is made to the IDLE state 401.

In the example above, processor 201 is denied access to processor 101 for sending data packets due to the receive buffer overflow condition at bus interface unit 110. Control unit 11 with reference to FIG.
As pointed out above in the description of the behavior of 4, a buffer overflow condition results in a change from OPEN RECEIVE state 501 to RFG state 512 and the identity of the processor sending the packet causing the overflow condition is to the RFGF buffer (118,218). It will be filled in. As described above, when the retransmission request causes the reception buffer to become empty, the control unit 114
It is sent on ENDRQ lead 157 and the address is stored in the RFGF buffer. This occurs under the control of the bus transmit finite state machine (FIG. 4) embodied in control unit 114. By the way, the bus reception finite state machine (FIG. 5) in the control unit 114 is in the RFG state 512. In this state, the data latch 125 controlling the transfer of data from the bus to the receive buffer 121 is deactivated. RFG state 512 in the bus receive finite state machine of control unit 114 when SENDRQ lead 157 is asserted by processor 114.
To RFG RECEIVE state 514. In this state, the data latch 125 receives data from the bus F
The control unit 114 is once again de-energized for sending to the IFO 121. Therefore, when the packet is retransmitted from the interface circuit 210 with the proper identification on the bus 153 identifying the processor 101, the output of the matching circuit 122 is ANDed with the energization from the control unit 114 in the register 125. Receive information present on the data bus when
Causes the data register to pass through the FIFO 121. As mentioned above, the bus receive finite state machine will be RFGRE until the EOP lead 154 is asserted by the interface unit 210.
Remain in CEIVE state 514. EOP instruction is control unit 114
From the RFG RECEIVE state 514 to the RFG state 512 in the read finite state machine at.

As long as there is at least one processor address left unhandled in the RFG FIFO 118, another transmit request is generated from the interface circuit 110 in the manner described above, and the bus receive finite state machine (Fig. 5) is again RFG RE.
The sequence is repeated with no transition to CEIVE state 514 and receipt of additional packets to return to RFG state 512. RFG FI
When FO118 is empty, a transition is made to the OPEN RECEIVE state 510, as indicated by the RFGFE signal. The Bus Receive Finite State Machine will remain in this state for normal bus read operations.

As mentioned above, the interface circuits 110 and 210 are said to be identical, and a functional description of the blocks of FIG. 1 applies equally to the similarly named blocks of FIG. 2 and vice versa. Similarly, control units 114 and 214 include the same finite state machine. The bus transmit finite state machine shown in FIG. 4 and the bus receive finite state machine shown in FIG. 5 are accomplished identically in both control units. In the above description, an example of packet transmission from the processor 201 to the processor 101 has been selected, and the operation of various units in the figure will be described. The blocks of FIG. 1 will perform the functions described with respect to similarly named blocks of FIG. 2, and the blocks of FIG. 2 will perform the functions described with respect to similarly named blocks of FIG. The device described is an illustration of the principles of the invention, and various other devices may be devised by those skilled in the art within the scope of the invention.

[Brief description of drawings]

FIGS. 1 and 2 are diagrams showing a multiprocessor system showing an access control device of the present invention by blocks, FIG. 3 is a diagram showing the arrangement of FIGS. 1 and 2, and FIGS. 4 and 5 FIG. 3 is a flow diagram of a finite state machine included in the access control device of FIGS. 1 and 2. [Explanation of symbols for main parts] Processor: 101,201 Interface circuit: 110,210 Bus: 150

Claims (10)

[Claims] 1. An apparatus for interconnecting a plurality of processors in a multiprocessor system, the interconnect bus transferring origin and destination addresses, data words and control messages and each connected to said bus, each of which is of a multiprocessor system. A plurality of bus interface circuits connectable to the processor, each bus interface circuit having a unique identity address associated therewith, with a destination address corresponding to the associated address occurring on the bus. A receive buffer for storing a data message and generating a receive buffer status signal, an address buffer for storing an identity address and generating an address buffer status signal, a receive buffer status signal indicating an overload condition and the associated ones on the bus Destination address corresponding to the address Store an origin address occurring on the bus in the address buffer in response to the generation, and the receive buffer status signal in response to the receive buffer and address buffer status signal, the receive buffer receiving an additional data word. Send the address fetched from the address buffer along with a resend request control message when it indicates that it is ready and when the address buffer status signal indicates that the address is present in the address buffer. An interconnect device including a bus interface circuit comprising a control means. 2. The interconnection device according to claim 1, wherein the device further comprises a further bus interface, the further bus interface circuit comprising a data message and an origin and destination on the bus. An interconnection device comprising means for transferring an address word and resending a preferentially transferred data message in response to an address transferred and fetched on the bus and the control message occurring on the bus. 3. The interconnection device according to claim 2, wherein said control means further sends a status control message on said bus in response to said receive buffer status signal indicating an overload condition, The retransmitting means in the other bus interface circuit is responsive to the status control message generated in the bus to prohibit the transmission of the data message onto the bus. 4. An apparatus for interconnecting a plurality of processors, comprising a first bus interface circuit connectable to a first processor, a second bus interface circuit connectable to a second processor, and the interface circuit. Bus means for interconnecting each of the interface circuits, each interface circuit having a unique address associated therewith, the first bus interface circuit comprising: Means for receiving a message and a destination address, and means for transmitting the received data message and destination address on the bus with a source address corresponding to the address associated with the first bus interface circuit, The second bus interface circuit receives the data message and stores it. A buffer for generating a status signal indicating the load status of the reception buffer, address storage means, and the status signal receiving additional data in response to the transmitted destination address and the status signal. Ready to store the origin address in the address storage means and to further recover the address from the address storage means in response to the status signal when the status signal indicates unprepared. The first bus interface circuit includes means for sending the recovered address and a send request message on the bus when indicating that the request message and the recovered address are sent on the bus. An interconnect device which retransmits a message preferentially transmitted on the data bus in response to the message. 5. A plurality of processors, a plurality of corresponding bus interface circuits, each connected to an associated processor, and interconnecting the bus interface circuits, with origin and destination address information and data and control messages between the interface circuits. In a multiprocessor system including a multi-conductor communication bus for transferring data, a transmission buffer for storing data and transferring data to the bus in response to a transmission control signal, a starting point and a destination address for storing data, and At least one of the plurality of bus interface circuits includes a first receiving buffer for storing data, the means for transferring the stored origin and destination addresses to the bus, and the controlling means for generating the transmission control signal. A receive buffer for generating a load status indication and a second receive buffer load status indication signal, Means for transferring data from the bus to the receiving buffer in response to destination address information generated on the bus, address buffer means for storing the address information and generating an address buffer load state instruction signal, and the first receiving buffer load Responsive to the state, storing origin address information occurring on the bus in the address buffer means and responsive to the second receive buffer load status indication signal and the address buffer load status indication signal from the address buffer means. Control means for recovering the address information and transmitting the recovered address information as destination address information on the bus together with a transmission request message, wherein the control means of the first plurality of interface circuits are configured to operate on the bus. Generate the transmission control signal in response to the resend request message and the destination address information Multi-processor system that is sending the data on the bus. 6. A multiprocessor system according to claim 5, further comprising bus priority location assigning means, each of said interface circuits being assigned a unique predetermined priority and said at least one. The at least one controller in one bus interface circuit
A multiprocessor system in which one interface circuit holds the bus and transmits the restored address information on the bus only when the bus access is permitted by the allocating means. 7. The multiprocessor system according to claim 6, wherein the control means of the first plurality of interface circuits are responsive to the retransmission request message and the destination address information. A multiprocessor system that is sending data on a captured bus. 8. A multiprocessor system according to claim 5, wherein said address buffer means includes a plurality of locations, and said at least one interface circuit has said predetermined address information on said bus. Means for recognizing predetermined destination address information and generating a match signal when the match signal is generated in response to the first receive buffer load status indication signal. A multiprocessor system in which the origin address information generated on the bus in the address buffer means is written every time the occurrence occurs. 9. A multiprocessor system including a plurality of processors and bus means for transferring data messages between the processors, comprising a device for ensuring access from a data sending processor to a data receiving processor, the device comprising the receiving processor. Means for sending an access denial signal when the device cannot accept a data message from the sending processor, means for recording the address identity of each data sending processor to which the access denial signal is sent, and said address identity means for recording the address identity means. And a means for transmitting a resend request signal to each of the processors whose address identities are recorded in said address identities recording means in a time sequence recorded in. 10. A multiprocessor system comprising a plurality of processors each having a unique address identity and bus means interconnecting the processors, the apparatus ensuring access from a plurality of data sending processors to a data receiving processor. Means for recording the address identities of the data sending processors from which the receiving processor cannot accept data messages therefrom, in the order in which the data message transfer attempts are made; the addresses recorded in the recording means. In each of the means for transmitting a resend request signal to each of the processors identified by the identities in the order in which the address identities are stored in the recording means, and in each of the sending processors for resending a data message in response to the resend request signal. Means for providing to the receiving processor A multiprocessor system in which access is guaranteed to multiple sending processors and provided in the order in which unsuccessful attempts to send to the receiving processors are made.