JPS60179837A - Buffer circuit of receiving data - Google Patents

Abstract

PURPOSE:To prevent a receiving side from the reduction of data processing efficiency by requesting the stop of transmission of data to a transmitting side before the fullness of a buffer memory for temporarily storing receiving data. CONSTITUTION:Outputs from a write address counter 1 and a read address counter 2 are switched by an address selector 5 synchronously with a timing pulse TP2 and supplied to an address of the buffer memory 8. The received data is read out from a read buffer 10 in the writing order in a write buffer 9 and an output from a data counter 3 shows the number of data left in the buffer memory 8. The output of the data counter 3 is inputted to a data counting value detecting circuit 4 and a data existence DTE, a data full signal FULL and signals S1, S2 indicating the existence of excess of a threshold are obtained from the circuit 4. On the basis of these signals, data transmission stop or data transmission restart are designated to the transmitting side.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a reception data buffer circuit that makes it possible to easily monitor the amount of data in a data buffer that temporarily stores received data in a data reception system.

[Technical background of the invention and its problems]

In a data receiving system, there are cases where the transmission speed of transmitted data is faster than the processing speed of the receiving system, or where the transmitted data is processed after a delay time. At this time, the receiving system must suspend processing, and a data buffer memory is required to temporarily store the received data. This includes a FIF that allows data to be read in the order in which it was input.
It is effective to use O (first-in, first-out) memory.

However, conventional buffers using FIFO memory only have signals for determining the presence or absence of data in the buffer and whether the buffer is full. For this reason, FI
If FO memory is used as a reception buffer, even if the buffer is full and the data sending side is notified to stop data, there will be a one-hour lag, and the data will still be sent, so it will not be possible to retrieve the data. I miss it. Therefore, there is a problem in that a buffer that can separately store data to be received thereafter is required.

Also, at the timing of instructing the sending side to resume data transmission after once instructing to stop.

I guess they used a signal to notify the presence or absence of a buffer.

Since restart is instructed after the buffer is once empty, the receiving system has no data to process during this time. Therefore, there are disadvantages in that time is wasted, data cannot be received smoothly, and data processing is inefficient.

[Purpose of the invention]

The present invention provides a reception data buffer circuit that can stop data transmission before a data buffer that temporarily stores reception data is filled, and can obtain timing to issue a signal to the transmission side to resume data transmission before the buffer runs out of data. The purpose is to provide

[Summary of the invention]

In this invention, the write address setting means and the read address setting means specify the data access address for the buffer memory that temporarily stores received data, and the data count means specifies the number of data in the buffer memory. The amount of data is monitored by counting the amount of data. moreover.

Upper and lower thresholds are set for the capacity of the buffer memory, and when the count value of the data counting means exceeds the upper threshold, the data sending side is requested to stop transmitting data, and the data The above objective is achieved by requesting the data transmitting side to resume data transmission when the count value of the counter becomes less than the lower threshold.

[Embodiments of the invention]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a received data quantity filter circuit according to the present invention will be described below with reference to the drawings.

In FIG. 1 showing the outline of this embodiment, (8) is a buffer memory 'Jul) for temporarily storing data, a write address counter (2) for specifying an address to write data to the buffer memory (8), and (2) ) is a read address counter for specifying the address to read data stored in the sofa memory (8), (3) is a data counter that counts the number of data stored in the balance memory (8), (4) (5) is a data count value detection circuit that detects the data from the number of data output by the data counter (3); no DTE, full FULL, presence or absence of SI exceeding the L threshold, etc. (5) )
The address selector (9) is used to selectively switch the write and read addresses of the buffer memory (8
00) is a timing pulse for writing data read from the buffer memory (8) to the glue (8) for temporary storage, and the write address counter (1 ) and a write timing pulse generation circuit that generates a write timing pulse WP which is a timing pulse for counting up the data counter (3). ) and the read address counter (2).
(11) is a read timing pulse generation circuit that generates a read timing pulse BP which is a timing pulse for counting up the data counter (11).
3) is a countdown pulse generation circuit that generates a countdown pulse DP for counting down.

The operation of this embodiment having the above configuration will be described below. Any buffer memory (8) can be used depending on the amount of data that requires buffering. Here, to simplify the explanation, the data is 8 pits.

Assume a memory with a capacity of IK bytes and a 10-bit address line.

Write address counter (1) and read address force 1/
1 (2) l'i, it is necessary to indicate the same count value in order to access the same address in the initial state, and in this embodiment, the reset pulse R8T
At this time, the number of data in the buffer memory (8) is counted and the data counter (3) is reset at the same time.
) is also reset to 0". In this state, the data count value detection circuit (4) detects the output of each output of the data counter (3) and outputs the signal DTE indicating the presence or absence of data in the buffer memory (8). (Fig. 2 i): - Outputs the state of no data. The outputs of the write address counter (1) and read address counter (2) are outputted by the address selector (5) to the timing pulse TP2 (Fig. 2 b). )
The data is switched in synchronization with the data and supplied to the address of the buffer memory (8). As a result, even if data write and read requests to the buffer memory (8) occur at the same time, access to the buffer memory (January 8) is performed selectively, and data collisions can be prevented.

First, received data is input in 8 bits from the data input bus DI, and is latched into the write buffer (9) by the write pulse WR (FIG. 2, C). Write buffer (9)
The output of is controlled in three states, and the internal bus I-B is connected to the buffer memory (8) only during the write period when the timing pulse TP2 shown in Fig. 2 is H''.
We are trying to supply data to the US.

The write pulse is also supplied to a write timing pulse generation circuit (6). Furthermore, there is always a timing pulse TPI (Fig. 2a), ! :TP2 (FIG. 2b) is supplied. This write timing generation circuit (6
) uses these timing pulses TPt and TP2,
The structure is such that the write timing pulse WP (Fig. 2 d) is generated only when the timing pulse TP2, which is the next write period after the write pulse ■ is input, is H''. In the Yoshiba Sofa Memo January 8), data in the write buffer (9) is written to the address indicated by the write address counter (1).

The details of this write timing pulse generation circuit (6) will be explained with reference to FIG. 3. The write pulse WR is used as a trigger pulse for the flip-flop (61).

Then, the output of these 7 lip-flops (61) is latched with a timing pulse TP2 in a flip-flop (62), and this output is gated with a timing pulse TP1 in a Nant gate (63), thereby generating a write timing pulse WP. .

The write timing pulse WP is also supplied to the write address counter (1) and data counter (3) at the same time.

As a result, the light address counter (1) is
> is counted up and indicates the address of the buffer memo 8) when the next data is written. The data counter (3) is also counted up in the same way. By inputting data one after another to the write buffer (9) in this way, the write address counter (1) counts up to 0.1.2.3. ...(decimal) is output. And the buffer memory specified by this count value (
The data stored in the write buffer (9) is sequentially written to the address 8). Note that this write address counter (1) counts cyclically, with the next count value after 1023 being 0. Also, data counter (
3) is similarly counted up sequentially by the write timing pulse WP.

Indicates the number of data stored in the buffer memory (8).

When data is written to the buffer memory (8), the signal DTE indicating the presence or absence of data output from the data count value detection circuit (4) is sent to the output of the data counter (3) as shown in Figure 2 (i). change in sync. This signal DT
E does not change until the value of the data counter (3) returns to 0''.

To read the data stored in the buffer memory (8), a read pulse RD (Fig. 2 e) is applied to the read buffer 00).
) is used to open the output of the 3-state. However, before inputting this read pulse RD, data to be read from the buffer memory (8) must be latched in this read buffer. However, after inputting the read pulse RD, the next data to be read is from the read buffer α from the buffer memory (8).
Since it is latched to Q, the first data read is meaningless without preprocessing, and subsequent data is 1
They will be read out in a shifted format. Therefore, in order to avoid the above-mentioned problem, the data written when the number of data in the buffer memory (8) is zero is stored in the read buffer a before there is a read request, that is, before read pulses R and D are input. [It is necessary to latch and advance the value of the read address counter (2) by one.

Therefore, as described above, when data is written to the buffer memory (8) when the value of the data counter (3) is 10'', the period when the primary timing pulse TP2 is L'',
That is, in the next read period, the written data is latched from the buffer memory (8) to the read buffer a, and the read timing pulse generation circuit (7) generates a read timing pulse RP that counts up the read address counter (2). ) will be explained with reference to FIG.

This read timing pulse generation circuit (7) not only generates a serial read pulse RD through an OR gate (70) and an AND gate (72), but also generates a data counter (3) whose value is 10''.
The timing pulse RP is generated using the write timing pulse WP at the time as a trigger pulse. That is, when data exists in the buffer memo 8), the signal D is output.
Since TE is "H", the output of the AND gate (72) depends on the read pulse RD, and the read pulse RD is not a trigger pulse.On the other hand, when there is no data, the output of the AND gate (72) is the trigger pulse.
Since E is "L" and the read pulse RD is 1H", the output line write timing pulse W of the AND gate (72)
Depending on P, the write timing pulse WP serves as the trigger pulse. Therefore, this read timing/</l/s generation circuit σ) is configured to generate the next timing when the write timing pulse WP is input and when the read pulse FLD is input in a state where no data exists in the buffer memory (8). During the read period, a read timing pulse RP shown in FIG. 2(f) is generated and supplied to the read buffer (10) and read address counter (2).

This read timing pulse RP causes the value indicated by the read address counter (2) at this time, ie.

The data read from the buffer 7 margin (8) according to the address of the data to be read next is latched to the serial read buffer (1) by opening the 3-state output.The read timing pulse RP is simultaneously , is input to the read address counter (2) to cause the read address counter (2) to count up.Therefore, every time data is read from the read balance buffer Q0, the read address counter (2) counts up, and 0, 1, 2. .3・
...The buffer memory indicated by the address (in decimal) (
8) will be sequentially read out.

Further, the read pulse RD is input to the countdown pulse generation circuit αυ, and is used as a countdown clock for the data callan/(3). The details of this countdown pulse generation circuit (11) are shown in FIG. 5. This countdown pulse generation circuit I has the same configuration as the above-mentioned write timing pulse generation circuit (6). Pulse TPI, TP
Since the countdown pulse DP is obtained by changing to 2, the explanation will be omitted. This countdown pulse generation circuit (11) is used.

The count value of the data counter (3) is counted down by the number of data read out, and indicates the number of data remaining in the buffer memory (8). The data received in this way can be read from the read buffer (10) in the order written to the write buffer (9), and the output of the data counter (3) is sent to the buffer memory (8).
Indicates the number of data remaining.

The output of this data counter (3) is inputted to the data count value detection circuit (4) to determine the presence or absence of data DTE, the presence or absence of data FULL, and the presence or absence of exceeding the L threshold s1. Signals such as s2 are obtained. Next, this data count value detection circuit (
The details of 4) are shown in FIG. 6 and will be explained. In the figure (
41) is an OR gate that detects the presence or absence of data DTE, 0
4 is AN that detects FULI when the data buffer is full.
This is the D gate. Here, for simplicity, we set the threshold to 51.
Setting the data to 2 bytes and 256 bytes, the timing of exceeding 512 bytes is captured at the rising edge of 81, and the timing of falling below 256 bytes is captured at the rising edge of 82. The data presence/absence signal DTE is obtained by detecting the case where the outputs of the data counter (3) are all ``0'' using the OR gate (41). In addition, the data full signal FUL
L is (4 AND gate data counter (3)
It is obtained by detecting the case where all the outputs of are 1". (4
3 and (44), the number of data in buffer memory (8) is 51
This detects when the number exceeds 2 bytes. When the data counter (3) is 512 bytes, that is, all the bits except the most significant bit Q are "1", when the 513th byte of the first order is written, a pulse equal to the width of the write timing pulse VVPO is generated (of the AND gate of 43). Appears in the output.

Therefore, if the 0-bit Noritsubu flop is reset by the pulse CLR and the output Q is set to @0'' in advance, the output (11→) changes from ``θ'' to ``1'' by this pulse. The output signal s1 has obtained the timing to instruct the transmitting side to stop transmitting the data.Here, since the write timing pulse WP is used as the input signal to G3, it changes from the state exceeding 512 bytes to below 512 bytes. When the address counter (3) changes, the output of the AND gate (4) does not change, so the signal S1 also does not change.
) changes only when the number of data exceeds 512 bytes. 0■, 06), the threshold value is set to 256 bytes in the same way. However, here, the countdown pulse DP is used instead of the write timing pulse WP for the input of the AND gate (4Q). Therefore, at 256 bytes, the signal S2 changes only when the number of data crosses 256 bytes and falls below. This signal S2 provides the timing to instruct the transmitting side to resume data transmission.In addition, the signal CLR input to the flip-flops G14) and (4G) resets the once changed signals 81 and 82. This is a signal for returning to the ON state. In this way, by obtaining the timing when the number of data exceeds 512 bytes and when it falls below 256 bytes, it is possible to easily stop and restart data transmission without having to manage the number of data in one normal buffer memory (8). The sender has obtained the timing to give instructions.

As explained above, according to this embodiment, the buffer memory (
The upper threshold is set to 512 bytes, which is half of the capacity of buffer memory (8), and when the number of data in the buffer memory (8) exceeds this upper threshold, the sending side can be requested to stop sending data. The buffer memory (8) never becomes full and no spare buffer memory is required. Still 25
Set 6 bytes as the lower threshold and use the buffer memory (
If the number of data in 8) falls below the lower threshold, the sending side can be requested to resume data transmission, so the buffer memory (8) will not become empty and the data processing efficiency on the receiving side will decrease. Never. Furthermore, by controlling the transmitting side using the above-mentioned request to stop and restart data transmission, the number of data in the buffer memory (8) can be easily monitored.

Note that here we set the data amount threshold to 512 bytes and 2
Although it is set to 56 bytes, the outputs Q and -Q of the data counter (3) are input to the AND gate and G.

It is clear that the threshold value can be changed arbitrarily by selecting either the inverted or non-inverted signal.

〔Effect of the invention〕

According to the present invention, it is possible to request the sending side to stop transmitting data before the buffer memory that temporarily stores received data is full, so the buffer memory does not become full and the spare backup memory is Not necessary. Also,
Since the sending side can be requested to resume data transmission before the buffer memory becomes empty, the buffer memory never becomes empty and data processing efficiency on the receiving side does not deteriorate.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the received data buffer circuit of the present invention, and FIG. 2 is a circuit diagram showing the details of FIG. 1. 1... Write address counter 2... Read address counter 3... Data counter 4... Data count value detection circuit 5... Address selector 6... Write timing pulse generation circuit 7... Read timing Pulse generation circuit 8...Buffer memory 9...Write buffer 10...Read buffer 11...Countdown pulse generation circuit Agent Patent attorney Noriyuki Chika (and 1 other person) Figure 2 (1) D-dou E 311'? 1 Shi------J Hayabusa figure 4

Claims (1)

[Claims] A buffer memory that temporarily stores data sent from a data sending side. writing means for writing data to be stored in the buffer memory into the buffer memory; write address setting means for setting an address at which the data writing means writes data into the buffer memory; and data stored in the buffer memory. data reading means for reading out the data from the buffer memory; read address setting means for setting an address from which data is read from the buffer memory by the data reading means; When data is written into the buffer memory by the data writing means, addition is performed. and data counting means for counting the number of data stored in the buffer memory by subtracting the data when the data is read from the buffer memory by the data reading means. When the counted value of the data counting means exceeds a predetermined upper threshold for the capacity of the buffer memory, outputting a data transmission stop signal to the data transmitting side;
On the other hand, the data count value detecting means outputs a data transmission restart signal to the data transmitting side when the counted value of the data counting means becomes less than a predetermined lower limit threshold. Receive data buffer circuit.