JPH0675796A - Parity error recording device - Google Patents

Abstract

PURPOSE:To acquire information on position where a parity error occurs concerning the parity error recording device in a system detecting a data error by means of a parity bit added to a bus. CONSTITUTION:A parity check means 103 performs the parity check, for example, in a byte unit based on the parity bit added to a bus 102 in a byte unit. The check result is recorded on a parity error recording means 104 at the required time and outputted to the outside respectively. A recording content fix means 105 fixes the recording content at the point of the time when the recording content of the means 104 is changed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parity error recording device in a system for detecting a data error by a parity bit added to a bus.

[0002]

2. Description of the Related Art With the spread of computer systems in recent years, a method of adding a parity bit to a bus in the system to detect a parity error of data is generally used in order to minimize damage caused by system malfunction. Has been used.

When a parity error occurs, if the circuit in which the error has occurred can be limited and specified, useful information can be obtained in circuit improvement, program debugging, and the like. Conventionally, when a parity error is detected, the device that detects the parity error notifies the CPU of the parity error by an interrupt or the like.

[0004]

However, in the above-mentioned conventional example, although it can be detected that a parity error has occurred, information on which byte of the bus caused the error and where in the IC the parity error occurred. Could not be obtained.

Therefore, there is a problem in that it takes time to investigate the cause of the data error.
The present invention aims to enable acquisition of information regarding the position where a parity error has occurred.

[0006]

FIG. 1 is a block diagram of the present invention. First, the present invention has a plurality of parity check means 103 for performing a parity check in a predetermined unit based on a parity bit added in a predetermined unit to the bus 102 inside the integrated circuit 101.

Next, there is a parity error recording means 104 composed of a flip-flop for recording each parity check result of the plurality of parity check means 103 and outputting each to the outside.

In addition to the above-mentioned configuration of the present invention, a recording content fixing means 105 for fixing the recording content of the parity error recording means 104 when the recording content of the parity error recording means 104 changes can be further provided. This means is a circuit for fixing the logic of the input clock to the flip-flop, which is the parity error recording means 104, after the output of the flip-flop has changed.

[0009]

The parity check means 103 performs a parity check in byte units based on the parity bit added to the bus 102 in byte units, and the check result is recorded in the parity error recording means 104 as needed. Therefore, it is possible to know at which data position of the bus 102 the error occurred when the parity error occurred.

In addition, the above-mentioned series of constructions is applied to the integrated circuit 101.
If provided for each of the plurality of buses 102, it is possible to know on which bus the parity error has occurred. Further, the recording content fixing means 105 is provided with the parity error recording means 104.
By fixing the recorded content at the time when the recorded content changes, the record at the time when the parity error first occurs can be held.

[0011]

Embodiments of the present invention will now be described in detail with reference to the drawings. In the following embodiments, the circuit configuration for recording the parity error in the bus connected to the I / O controller 315 in the message communication device 103 of FIG. 3 described later is most relevant to the present invention. <Overall Configuration of Embodiment of the Present Invention> FIG. 2 is a configuration diagram of a network to which the embodiment of the present invention is applied.

A network 201 having an optical fiber ring 206 as a center has a plurality of nodes 202 (see FIG. 2).
Are indicated by numbers such as # 000, # ***, # %%%, etc.)
Are connected.

At node 202, processor bus 2
A plurality of processors 204 are connected to 05, and the processor bus 205 is accommodated in the message communication device 203. The message communication device 203 includes the processor bus 20.
5, the processor 204 processes the message data transmitted or received, and also processes the frame in which the message data input to or output from the optical fiber ring 206 is stored.

Next, FIG. 3 is a block diagram of the message communication device 203 in the node 202 of FIG. 2 in the embodiment of the present invention. The real memory 307 functions as a communication buffer that temporarily holds message data.

The control memory 308, for each virtual page address in the virtual storage space used for message communication, if the virtual page address is allocated to the real page address in the real memory 307, the real page. The address and data indicating the page state (communication state) of the virtual page address are stored.

The processor bus interface 312 is
2 is connected to the external bus 301 and accommodates the message data and the like input from the processor 204 of FIG. 2 via the processor bus 205 via the external bus 301 and the virtual memory controller 309. 307 and vice versa, the message data and the like input from the real memory 307 via the virtual memory controller 309 and the external bus 301 are output to the processor 204 via the processor bus 205.

Further, the processor bus interface 31
2 exchanges communication control data with the CPU 313 via the external bus 301, the bus coupling unit 311, and the CPU bus 302.

Although not explicitly shown in FIG. 2, in FIG. 3, two processor buses 205 are provided for each node. Therefore, the processor bus interface 312 also
Two # 0 and # 1 are provided corresponding to each processor bus 205. Then, the # 0 processor bus interface 312 uses the control line 319 to perform contention control when the # 0 and # 1 processor bus interfaces 312 access the external bus 301. Further, the # 0 processor bus interface 312 is connected to the control lines 321 and 322.
Via a CPU bus arbiter 314 and I /
While exchanging control data regarding bus use with the O controller 315, competition control of the external bus 301 is performed, and opening / closing control of the bus coupling unit 311 is performed via the control line 320 when necessary.

The network control circuit 310 sends a frame from the CPU 313 to the CPU bus 302, I when transmitting a frame.
A control memory 308 via a control memory access bus 306 based on a transmission command input via the I / O controller 315 and the network command / result bus 303.
While accessing, read message data to be transmitted from the real memory 307 via the virtual memory controller 309 and the network data transmission bus 305, construct a transmission frame including the message data, and send it to the optical fiber ring 206. The transmission result is sent to the network command / result bus 303 and the I / O controller 31.
5 and the CPU 313 via the CPU bus 302.

The network control circuit 310 also receives a frame from the optical fiber ring 206 via the control memory access bus 306.
Access the received frame to another node 2
Relay to 02. Alternatively, the message data in the received frame is extracted and the network data reception bus 30
4 to the real memory 307 via the virtual memory controller 309, and the reception result is notified to the CPU 313 via the network command / result bus 303, the I / O controller 315, and the CPU bus 302.

The CPU 313 is connected to the CPU bus 302, and is connected to the CPU bus 302 at the start of operation.
It operates according to a control program written from the PROM 316 to the program RAM 317 connected to the CPU bus 302.

The CPU 313 has a CPU bus 302,
Communication control data is exchanged with the processor bus interface 312 via the bus coupling unit 311 and the external bus 301.

Further, the CPU 313, when transmitting a frame, uses the CPU bus 302, the I / O controller 315,
And output a send command to the network control circuit 310 via the network command / result bus 303, and thereafter
From the network control circuit 310, a network command /
Result bus 303, I / O controller 315, and CP
The transmission result notification is received via the U bus 302. Conversely, the CPU 313 receives from the network control circuit 310 the network command / result bus 303, the I / O controller 315, and the CPU bus 3 when receiving a frame.
A reception result notification is received via 02.

Further, the CPU 313 has a CPU bus 302.
The page state data (data indicating the communication state) of each virtual page address in the control memory 308 is accessed via the CPU memory 302 and the virtual page address of each virtual page address in the control memory 308 is accessed via the CPU bus 302 and the virtual memory controller 309. The page address data and the real memory 307 are accessed.

The I / O controller 315 is connected to the CPU bus 302 and houses a peripheral device bus 318 to which external peripheral devices are connected. In addition, I / O controller 3
As described above, the relay unit 15 relays the transmission command, the transmission result notification, or the reception result notification exchanged between the CPU 313 and the network control circuit 310 via the CPU bus 302 and the network command / result bus 303. In this case, the circuit configuration (FIGS. 5 to 7 described later) for recording the parity error in the bus (for example, the CPU bus 302) connected to the I / O controller 315 is most relevant to the present invention.

Further, the I / O controller 315 is a CP
The address that U313 uses to access the external bus 301 is C
When specified for the PU bus 302, the control line 322
To the processor bus interface 312 of # 0 via
Outputs an external bus access request.

The CPU bus arbiter 314 is a C bus from the processor bus interface 312 via the control line 321.
When the PU bus access request (bus grant request) is received, the bus use request (bus grant request) is output to the CPU 313 via the control line 323, and the CPU 3
13 receives a bus use permission (bus grant acknowledge) from the control line 323 through the control line 323, and based on that, the CPU
Bus access permission (bus grant acknowledge) is sent via the control line 321 to the # 0 processor bus interface 3
Return to 12.

The virtual memory controller 309 is
Processor bus interface 312 and real memory 307
Data exchanged with the external bus 301 via the external bus 301, C
Data transmitted and received between the PU 313 and the real memory 307 or the control memory 308 via the CPU bus 302, and between the network control circuit 310 and the real memory 307 via the network data reception bus 304 or the network data transmission bus 305. The switching control and the contention control of the exchanged data are performed.

The operation of the embodiment of the present invention having the above configuration will be described. <Overall operation of inter-processor communication> Now, in FIG. 2 and FIG. 3, for example, message data is sent from one processor 204 in the node 202 of # 000 to another processor 204 in the node 202 of # ***. The overall operation when transmitting will be described.

In this case, the message data transmitted from one processor 204 in the node # 000 is the message communication device 203 in that node (hereinafter, the message communication device 203 in # 000) via the processor bus 205. Call)) to the real memory 307,
It is sent to the real memory 307 of the message communication device 203 in the node 202 of # *** (hereinafter referred to as the message communication device 203 of # ***), and then the destination from the real memory 307 via the processor bus 205. The processor 204
Transferred to. That is, the real memory 307 of each message communication device 203 functions as a communication buffer. Communication Method Between Message Communication Devices 203 Here, a special method called a network virtual storage method is applied to communication of message data between the message communication devices 203.

First, in the entire network 201 of FIG.
A virtual memory space is defined. This virtual storage space is divided into a plurality of virtual pages, and message data is communicated via these virtual pages. For example, the virtual storage space is divided into virtual page addresses of 0000 to FFFF pages (hexadecimal number). One virtual page has a fixed length (for example, 8 kilobyte length) data length that can sufficiently accommodate a packet that is one unit of message data. Unless otherwise specified, the virtual page address and the dictated real page address are represented by hexadecimal numbers.

Next, the message communication device 203 of each node 202 connected to the network 201 is allocated for every predetermined number of pages of the virtual storage space, for example, every 16 pages. For example, the message communication device 203 of the # 000th node 202 is allocated to the 0000 to 000F page, the message communication device 203 of the # 001th node 202 is allocated to the 0010 to 001F page, and so on. ** 0-*** F page and %%% 0-%%% F page (3 digit *
And% are arbitrary numbers in hexadecimal numbers 0 to F), the message communication device 203 of each node 202 of the # *** th and # %%% th is assigned.

Therefore, in the above example, the network 20
1, a maximum of 4096 message communication devices 203 from # 000 to #FFF can be connected. On the other hand, the real memory 307 in each message communication device 203 is divided into a plurality of real pages each having the same data length as the above-mentioned virtual page. The page capacity of the real memory 307 may be much smaller than the page capacity of the virtual storage space, and may be, for example, about 64 to 256 pages.

Next, in the control memory 308 of each message communication device 203, as shown in FIG. 4, control data for all virtual page addresses are stored. As shown in FIG. 4, the control data of each virtual page address indicates the real page address data of the real memory 307 in the own message communication device 203 associated with the virtual page address and the communication state of the virtual page address. And page status data shown.

Then, as an initial state, each node 202
In the control memory 308 of the message communication device 203 in the internal message communication device 203, the virtual page address assigned to the node 202 is set to an arbitrary empty page in the real memory 307 of the message communication device 203 by the network reception control function of the CPU 313. The real page address of the network receiving buffer provided in the above and the receiving buffer allocation state VP as the page state are respectively written in advance. The network reception control function is a CP
This is realized by the U313 executing the control program stored in the program RAM 317.

For example, the # 000 message communication device 203
In the control memory 308 of the own message communication device 2
As shown in FIG. 4, each virtual page address of 0000,0001, ..., 000F pages assigned to the 03 is assigned to each real page of s, q, ..., p in the real memory 307. The address has been written and the page status VP indicating the receive buffer allocation status has been written.

In the control memory 308 of the message communication device 203 of # ***, the own message communication device 20
As shown in FIG. 4, each virtual page address of **** 0, *** 1, ..., *** F page assigned to
The page status indicating the receive buffer allocation status in which each real page address of v, u, ..., T in the real memory 307 is written.
VP is written.

Similarly, # %%% message communication device 203
In the control memory 308 of the own message communication device 2
, %%% 0, %%% 1, ..., %%% F, the virtual page addresses of the pages of the real memory 307 include y, w, and , X are written, and the page state VP indicating the receive buffer allocation state is written.

Now, by the transfer operation described later, for example, # 000
Message data is transferred from one processor 204 in the node # 000 202 to a network transmission buffer (to be described later) whose real page address is r in the real memory 307 of the message communication device 203 of FIG. To do.

The network transmission control function of the CPU 313 analyzes the destination address part in the header of the message data stored in the network transmission buffer in the real memory 307 via the CPU bus 302 and the virtual memory controller 309. By doing so, the virtual page address assigned to the node 202 in which the processor 204 corresponding to the destination address is accommodated is determined as the one whose page state is the buffer unallocated state NA. In the example of FIG. 4, for example, the virtual page address *** 2 is determined. The network transmission control function is realized by the CPU 313 executing the control program stored in the program RAM 317.

Next, the network transmission control function of the CPU 313 writes the real page address of the network transmission buffer in which the above-mentioned message data is stored in the determined virtual page address in the control memory 308, and the page Change the status from the buffer unallocated status NA to the transmission status SD. In the example of FIG. 4, the real page address r and the transmission state SD are set to the virtual page address *** 2, for example.

The network transmission control function of the CPU 313 is the transmission F function in the I / O controller 315.
The virtual page address and the transfer length of the message data described above are written to the IFO via the CPU bus 302 together with the transmission command.

When the network control circuit 310 reads the above-mentioned transmission command and the like from the transmission FIFO in the I / O controller 315 via the network command / result bus 303, the virtual page added to the transmission command. An address is designated to the control memory 308 via the control memory access bus 306, the real page address set in the above-mentioned virtual page address is read from the control memory 308, and set in the DMA transfer register in the virtual memory controller 309. To do.

Then, the network control circuit 310 is
The page data of the real page address in the real memory 307 including the message data to be transmitted to the virtual memory controller 309 is transferred to the network control circuit 310 via the network data transmission bus 305.
To DMA transfer.

The network control circuit 310 takes out the message data corresponding to the transfer length of the message data added to the send command from the page data described above, and the virtual page address added to the message data and the send command. And a transmission frame including the transfer length of the message data and generating the transmission frame.
Send to 6. The token ring network method is adopted as the frame transmission method of the optical fiber ring 206, and the network control circuit 310 can send a transmission frame only when a free token circulating on the optical fiber ring 206 is acquired. .

In the example of FIG. 4, the transmission frame including the virtual page address *** 2 and the message data stored in the real page address r in the real memory 307 from the message communication device 203 of # 000 is It is sent to the optical fiber ring 206.

The above-mentioned transmission frame is transmitted to another node 202 (see FIG. 2) connected to the optical fiber ring 206.
Are sequentially transferred to. When the network control circuit 310 of the message communication device 203 in each node 202 fetches the transmission frame from the optical fiber ring 206, the page state corresponding to the virtual page address stored in the transmission frame is set to the control memory access bus 306. Read from the control memory 308 via the, and whether the page status is the receive buffer allocation status VP, that is, whether the virtual page address is assigned to the message communication device 203 of the own node 202, or the page It is determined whether or not the state is the transmission state SD, that is, whether or not the transmission frame is transmitted by the own network control circuit 310.

When the network control circuit 310 determines that the page state of the virtual page address stored in the transmission frame is the reception buffer allocation state VP,
The message data stored in the transmission frame is taken into the real memory 307 as follows.

That is, the network control circuit 310 first designates the virtual page address stored in the transmission frame to the control memory 308 via the control memory access bus 306, and the control memory 308 changes the virtual page address to the above virtual page address. The set real page address is read out and set in the DMA transfer register in the virtual memory controller 309. Then, the network control circuit 310 causes the virtual memory controller 309 to
The message data included in the transmission frame is DMA-transferred to the above-mentioned real page address in the real memory 307 via the network data reception bus 304.

After that, the network control circuit 310
The virtual page address stored in the transmission frame is
Control memory 30 via control memory access bus 306
8 is specified, and the page status of the virtual page address is changed from the reception buffer allocation status VP to the reception completion status RD.

Further, the network control circuit 310 is
The virtual page address extracted from the transmission frame and the transfer length of the message data are written into the reception FIFO in the / O controller 315 via the network command / result bus 303 together with the result code indicating the success or failure of the reception.

Finally, the network control circuit 310
After writing the reception success notification in the response area in the above-mentioned transmission frame received from the optical fiber ring 206, the transmission frame is sent to the optical fiber ring 206 again.

For example, in the example of FIG. 4, the network control circuit 310 of the message communication device 203 of # *** is # 000.
The message stored in the transmission frame is determined by determining that the page state on the control memory 308 of the virtual page address *** 2 stored in the transmission frame from the node 202 is the reception buffer allocation state VP. The data is transferred to the real memory 30 having the real page address u set to the virtual page address *** 2 of the control memory 308.
After fetching in the network reception buffer in 7, the page state of the virtual page address *** 2 of the control memory 308 is changed from the reception buffer allocation state VP to the reception completion state RD.

The above-mentioned reception result notification is received by the CPU 313 via the CPU bus 302. That is, CP
The U313 network reception control function uses the reception F in the I / O controller 315 via the CPU bus 302.
When the above reception result notification is received from the IFO and if the result code is successful in reception, the virtual page address which is a part of the reception result notification is designated to the control memory 308 via the CPU bus 302, and the page state Read the real page address.

If the page state described above is the reception completion state RD, the network reception control function of the CPU 313 first controls the real memory 307 via the CPU bus 302 and the virtual memory controller 309 to make the above-mentioned real state. Separates the real page specified by the page address from the network receive buffer and connects it to the processor send-wait buffer queue.

Thereafter, the network reception control function of the CPU 313 controls the real memory 307 via the CPU bus 302 and the virtual memory controller 309 to connect an arbitrary empty page to the network reception buffer, and further Control memory 3 via CPU bus 302 with a virtual page address that is part of the reception result notification
08 is accessed, and the real page address of the above-mentioned empty page and the reception buffer allocation state VP as the page state are written to the virtual page address.

Thereafter, the processing for the processor transmission waiting buffer queue in the real memory 307 is performed by the CPU 31.
3 from the network reception control function to the processor transmission control function described later.

On the other hand, the network control circuit 310 reads the page state corresponding to the virtual page address stored in the transmission frame from the control memory 308, and as a result, the page state is neither the reception buffer allocation state VP nor the transmission state SD. If it is determined that the transmission frame is transmitted, the transmission frame is directly transmitted to the optical fiber ring 206.

For example, in the example of FIG. 4, the network control circuit 310 of the # %%% message communication device 203 uses # 000
By determining that the page state on the control memory 308 of the virtual page address *** 2 stored in the transmission frame from the node 202 of the node 202 is neither the reception buffer allocation state VP nor the transmission state SD, the transmission frame is left as it is. It is sent to the optical fiber ring 206.

Optical fiber ring 206 as described above
The transmission frame sequentially transferred above returns to the network control circuit 310 of the message communication device 203 in the node 202 which is the transmission source.

The source network control circuit 310 is
As a result of reading out the page state corresponding to the virtual page address stored in the transmission frame from the control memory 308, by determining that it is the transmission state SD,
It is determined that the transmission frame is the transmission frame transmitted by the own network control circuit 310.

In this case, the network control circuit 310
After confirming that the reception success notification is written in the response area of the received transmission frame, the control memory 308 of the control memory 308 corresponding to the virtual page address stored in the transmission frame is transmitted via the control memory access bus 306. The page state is changed from the transmission state SD to the transmission completion state SC.

Then, the network control circuit 310 is
The virtual page address extracted from the transmission frame is written to the reception FIFO in the I / O controller 315 via the network command / result bus 303 together with the result code indicating the success or failure of the transmission.

The above-mentioned transmission result notification is received by the CPU 313 via the CPU bus 302. That is, CP
The network transmission control function of the U313 is performed by the reception F in the I / O controller 315 via the CPU bus 302.
When the above result notification is received from the IFO, if the result code is successful, the virtual page address that is a part of the result notification is specified in the control memory 308 via the CPU bus 302, and the page status is changed. Read the real page address.

If the page state described above is the transmission completion state SC, the network transmission control function of the CPU 313 first controls the real memory 307 via the CPU bus 302 and the virtual memory controller 309, and The real page specified by the page address is separated from the network send buffer and used as a free page.

After that, the network transmission control function of the CPU 313 controls the control memory 3 via the CPU bus 302 with the virtual page address which is a part of the above-mentioned transmission result notification.
08 is accessed, and the buffer unallocated state NA is written as the page state of the virtual page address.

As described above, the network 201 (see FIG.
In the above, one virtual storage space is defined, and a virtual page having a fixed data length that constitutes this space is assigned to each message communication device 203. Communication of message data between the message communication devices 203 is performed using this virtual page. As a result, blocking control and sequence control that are performed in normal packet communication are not required.

When the network control circuit 310 of the message communication device 203 in each node 202 on the optical fiber ring 206 receives a transmission frame, the virtual page address stored in the transmission frame causes the network control circuit 310 on the control memory 308. By accessing the page state, the received transmission frame can be processed at high speed.

In addition, the transmission frame transferred on the optical fiber ring 206 is provided with a response area, and the network control circuit 310 of the message communication device 203 in the node 202 on the receiving side transmits the reception result of the transmission frame. It writes in the response area of the frame and sends it out again to the optical fiber ring 206. Therefore, by the time this transmission frame is transferred on the optical fiber ring 206 and returned to the transmission source, the message data transmission processing is completed, and the response from the reception side to the transmission source is sent using another frame. No need to notify. As a result, the communication protocol can be simplified and high-speed response processing can be performed.

Further, communication of message data between the message communication devices 203 is performed using the real memory 307 while the network control circuit 310 in the message communication device 203 accesses the control memory 308, and the communication with the processor 204 and the message communication device 203 is performed. The communication of message data between 203 is performed by the message communication device 2 as described later.
The processor bus interface 312 in 03 uses the real memory 307 independently of the operation of the network control circuit 310 described above. Further, the correspondence between the message data stored in the real page address in the real memory 307 and the virtual page address in the virtual storage space is as described below, in which the CPU 313 sends the destination address in the header added to the message data. Based on. Therefore, between the processor 204 and the message communication device 203,
Message communication device 203 and message communication device 203
It is possible to efficiently perform the processing between them at high speed. From the processor 204 at the sender to the message communication device
Operation of Transferring Message Data to Device 203 Next, from one processor 204 in the source node 202 (# 000 node 202 in the example of FIG. 4) to the real memory 307 of the message communication device 203 in that node, The operation when the message data is transferred will be described.

First, the processor reception control function of the CPU 313 accesses the real memory 307 via the CPU bus 302 and the virtual memory controller 309 to connect the processor reception buffer queue to the free buffer queue in the real memory 307. Connect the free buffer that is being used. The processor reception control function is a function realized by the CPU 313 executing the control program stored in the program RAM 317.

Then, the processor reception control function of the CPU 313 activates, for example, the # 0 processor bus interface 312 via the CPU bus 302, the bus coupling unit 311, and the external bus 301, and sends the interface 312 to the processor bus interface 312. The start address of the above-mentioned processor receive buffer queue is notified.

The processor bus interface 312 is
The message data transferred from the processor 204 via the processor bus 205 is received, and the received message data described above is updated while sequentially updating the buffer address with the start address as the reception start address.
External bus 301 and virtual memory controller 30
9 is sequentially transferred to an empty buffer connected to the processor reception buffer queue in the real memory 307.

The processor bus interface 312 is
When there is no free buffer connected to the processor reception buffer queue, the free buffer is automatically stopped, and the fact is notified to the CPU 313 via the external bus 301, the bus coupling unit 311, and the CPU bus 302.

The processor reception control function of the CPU 313 first controls the real memory 307 via the CPU bus 302 and the virtual memory controller 309 to separate the above-mentioned received buffer from the processor reception buffer queue and transmit it to the network. Connect to a buffer. Thereafter, the processing for the network transmission buffer in the real memory 307 is transferred from the processor reception control function of the CPU 313 to the network transmission control function described above, and the transmission source of the transmission source is transmitted in accordance with the communication method between the message communication devices 203 described above. From the real memory 307 in the message communication device 203 of the node 202 (# 000 message communication device 203 in the example of FIG. 4), the message communication device 203 of the node 202 (in the example of FIG. 4) in which the destination processor 204 is accommodated # *** message communication device 20
The message data transfer operation to the real memory 307 in 3) is executed. From the message communication device 203 on the receiving side to the process
Transfer Operation of Message Data to Server 204 Next, the real memory 3 of the message communication device 203 in the receiving node 202 (# 202 node 202 in the example of FIG. 4).
07 to one processor 204 in that node 202
The operation when the message data is transferred will be described below.

When the network control circuit 310 succeeds in receiving the transmission frame, as described above, the CPU 313.
The network reception control function of (1) connects the received message data to the processor transmission waiting buffer queue in the real memory 307.

On the other hand, the processor transmission control function of the CPU 313 includes the CPU bus 302 and the bus coupling unit 31.
For example, the # 0 processor bus interface 312 is activated via 1 and the external bus 301, and the interface 312 is notified of the start address of the above-mentioned processor transmission waiting buffer queue.

The processor bus interface 312 is
While sequentially updating the buffer address with the start address as the transmission start address, the real memory 30 is accessed via the external bus 301 and the virtual memory controller 309.
7 sequentially reads the message data stored in the buffer connected to the processor transmission waiting buffer queue, analyzes the destination address part in the header of the message data, and transfers the message data to the processor bus 205. Via the destination processor 204. <Description of I / O Controller Parity Error Detection and Recording Part> Next, the I / O controller 315 of FIG.
The configuration of the portion for detecting and recording the parity error in the bus connected to it will be described with reference to FIG.

In FIG. 5, as an example, the CPU data bus 501, the CPU address bus 502, which form the bus CPU bus 302 connected to the I / O controller 315,
And a configuration of a portion of the CPU control bus 503 for detecting and recording a parity error. First,
The CPU data bus 501 is the input data bus 50 in the I / O controller 315 due to the bidirectional buffer 504.
9 and the output data bus 510. The CPU data bus 501, the input data bus 509, and the output data bus 510 each have a data width of 32 bits,
1 parity bit per 8 bits, ie 32
Four parity bits are added per bit.

The CPU address bus 502 is connected to the internal bus by the one-way buffer 505, has an address width of 32 bits, and as in the case of the data bus, one parity bit per 8 bits, that is, 32 bits. Four parity bits are added per time.

The CPU control bus 503 is connected to the internal bus by the one-way buffer 506, has an address width of 32 bits, and has a parity bit of 1 bit per 8 bits, that is, 32 bits as in the case of the data bus. Four parity bits are added per time.

I / O connected to the CPU data bus 501
The input data bus 509 and the output data bus 510 in the O controller 315 are respectively # 0 and # 1 parity check modules 5 for checking the above-mentioned 4-bit parity.
07 is connected. In addition, each of the buses in the I / O controller 315 connected to the CPU address bus 502 and the CPU control bus 503 checks the above-described 4-bit parity # 2 and # 3 parity check module 5.
07 is connected.

Each parity check module 507 of # 0 to # 3
The 4-bit parity check output of is input to the parity error recording circuit 508. Each bus in the I / O controller 315 and the parity error recording circuit 508 operate in synchronization with the clock CLK, and the parity error recording circuit 5
The recorded content of 08 (described later) is reset by a reset signal.

The recorded contents of the parity error recording circuit 508 are the contents of the output data bus 510, the bidirectional buffer 504 and the CPU data bus 501, and the CPU 31 of FIG.
3 will be notified.

FIG. 6 is a common block diagram of each of the parity check modules 507 of # 0 to # 3 in FIG. # 0 ~ # 3
The parity check circuit 602 is a circuit which inputs 8-bit data out of 32-bit data and 1-bit parity bit corresponding to the 8-bit data and performs a parity check, and outputs the check result as a 1-bit signal. Yes, it is configured by a well-known circuit. The parity check circuit 602 outputs “0” as the check output if the check result is correct.
Is output, and if it is incorrect, "1" is output.

FIG. 7 shows the parity error recording circuit 5 of FIG.
It is a block diagram of 08. A 4-bit D flip-flop (D-FF) 70 is provided for each 4-bit parity check output of the # 0 to # 3 parity check module 507 of FIG.
1 and OR gate (OR) 702 and OR gate (OR) 7
The circuit components of # 0 to # 3 composed of # 3 and # 3 are configured.

The OR 703 calculates the logical sum of the 4-bit output of the D-FF 701 and outputs the 1-bit calculation result. The OR 702 outputs the output of the OR 703 and the clock CLK.
Is calculated, and the 1-bit calculation result is calculated by the D-FF70.
1 to the clock input terminal (CLK).

The D-FF 701 has a clock input terminal (C
The 4-bit parity check output of the parity check module 507 based on the pulse input to LK),
Further, it is reset by the reset signal 511 input to the reset input terminal (RST).

The operation of the configuration shown in FIGS. 5 to 7 will be described with reference to the timing chart of FIG. First, at the start of system operation, the content recorded in each D-FF 701 in the parity error recording circuit 508 is reset to “0” by a reset signal 511 asserted from a circuit (not shown).

In this state, all the 4-bit outputs of each D-FF 701 are "0", so that the clock CLK shown in FIG. 8 (a) is output via the OR 702 as shown in FIG. 8 (d). To the clock terminal (CLK) of the D-FF 701. The D-FF 701 records the 4-bit parity check output of the parity check module 507 in synchronization with the rising edge of the clock CLK.

Now, the parity check module 50 of # 0 to # 3
When a parity error is detected in at least one of the parity check circuits 602 of # 0 to # 3 in 7 and the output bit becomes “1” as shown in FIG. The output of the OR 703 connected to the output of the D-FF 701 to which the included parity check output is input becomes "1" as shown in FIG. 8 (c).

As a result, the output of the OR 702 to which the output of the OR 703 is input becomes "1" as shown in FIG. 8 (d). As a result, the 4-bit recording content of the D-FF 701 to which the output of the OR 702 is input is fixed.

After the above parity error detection and recording operation, the CPU 313 of FIG. 3 operates the output data bus 51 of FIG.
0 to bidirectional buffer 504 and CPU data bus 50
1 via the CPU bus 302 of FIG.
The fixed recording contents of the D-FF 701 in the parity error recording circuit 508 can be read. As a result, the CPU data bus 501 (input data bus 509,
Output data bus 510), CPU address bus 502,
Alternatively, it is possible to know which byte of which bus of the CPU control bus 503 has an error.

In the embodiment of the configuration for detecting and recording the parity error described above, the I / O controller 31 shown in FIG.
5 is taken as an example, a circuit for detecting and recording a parity error is connected to the external bus directly connected to it.
The present invention is not limited to this, and a circuit for detecting and recording a parity error can be connected to various buses formed in a general IC.

[0095]

According to the present invention, it is possible to know at which data position of which bus the error occurred when a parity error occurred.

Further, the recording content fixing means fixes the recording content at the time when the recording content of the parity error recording means changes, whereby the recording at the time when the parity error first occurs can be held. .

[Brief description of drawings]

FIG. 1 is a block diagram of the present invention.

FIG. 2 is a configuration diagram of a network to which an embodiment of the present invention is applied.

FIG. 3 is a configuration diagram of a message communication device according to an embodiment of the present invention.

FIG. 4 is an explanatory diagram of message communication.

FIG. 5 is a configuration diagram of a portion for detecting and recording a parity error of the I / O controller.

FIG. 6 is a configuration diagram of a parity check module.

FIG. 7 is a configuration diagram of a parity error recording circuit.

FIG. 8 is a timing chart of an operation of detecting and recording a parity error.

[Explanation of symbols]

 101 Integrated Circuit 102 Bus 103 Parity Checking Means 104 Parity Error Recording Means 105 Recorded Content Fixing Means

Claims (2)

[Claims] 1. A bus (10) inside an integrated circuit (101).
2) A plurality of parity check means (103) for performing a parity check in the predetermined unit based on a parity bit added in a predetermined unit, and recording each parity check result of the plurality of parity check means (103) And a parity error recording means (104) for outputting each to the outside, and a parity error recording device. 2. A bus (10) inside an integrated circuit (101).
2) A plurality of parity check means (103) for performing a parity check in the predetermined unit based on a parity bit added in a predetermined unit, and recording each parity check result of the plurality of parity check means (103) Then, a parity error recording means (104) for outputting each to the outside, and a recording content fixing means (1) for fixing the recording content of the parity error recording means (104) when the recording content changes.
05) and a parity error recording device comprising: