JPH0756640B2 - Storage device - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to a redundant (check) bit generation method at the time of a partial write operation in a storage device of a method in which redundant (check) bits are added to information bits and stored. Regarding the improved one.

[Background of the Invention]

Conventionally, a storage device of a type that collectively controls a plurality of storage units (banks) that operate independently is disclosed in JP-A-58-142459.
As described in No. 3, the generation of the check bit in the partial write operation for rewriting a part of an arbitrary address area is performed after the write data is merged. A conventional partial write operation will be described using an example. Figure 3 shows the main memory (MS)
Is divided into 16 banks (BK), which are grouped into 4 banks to form a 4 bank group (BG).
An example of computer system configuration when connected to U) is shown. FIG. 4 shows a data system structure in the one bank group.

4, receiving ports 201, 202, 203 from the SCU, error correcting code (ECC) check bit generating circuits 204, 205 ECC checking circuit 206, a write data buffer 207, a mark data buffer 208, and a sending / receiving port to the SCU. 209 etc. are the four banks BK0 of the bank group.
~ Share on BK3. The bank BK0 includes a storage element group 210, an address register 211, a write data register 212 and a read data register 213. The write data in the data path 215 for full write operation and the data path 216 for partial write operation are selected and set in the write data register 212 by the selection circuit 214. The configuration of banks BK1 to BK3 is similar.

When the partial write operation is executed with the configuration of FIG. 4, first, the data stored in the area of the address where the partial write is to be executed is read. Next, based on the write byte designation information (mark) held in the mark data buffer 208, a merge circuit 217 merges the write data stored in the write data buffer 207 with the above-mentioned read data. , ECC check bit generation circuit (ECC generation B) 205 generates check bits. After that, by writing the merged data including the check bit to the access address area,
The partial write operation is completed.

As is clear from the above description, the partial write operation in the conventional configuration requires the data buffer for holding the partial write data until the data at the access address is read. However, when a multi-bank configuration is required like the main memory of a computer for scientific and technological computers,
The amount of hardware to realize this has increased, and in order to cope with this, it has become necessary to reduce the amount of hardware of the mechanism that commonly controls each bank.

[Object of the Invention]

It is an object of the present invention to provide a means for reducing the amount of metal parts of a partial write data buffer in a storage device of a type in which a check bit is added to an information bit for storage.

[Outline of Invention]

The point of the present invention is that the hardware of the data buffer that holds the write data of the partial write operation by synthesizing the check bits independently generated from the data of the portion to be rewritten and the data of the portion that is not rewritten in the arbitrary address. It is possible to reduce the amount.

Here, the legitimacy of the method of dividing and generating the check bits will be considered. For explanation, as an error correction code system,
SEC−DED (Single bit Error Correcting−Double bit
Error Detecting) method, 64 information bits
(8 bytes) and the number of check bits is 8.

Let H be the check matrix (H matrix) of the SEC-DED method and the information bits Then the check bit is Is. here, For example If, Is.

Therefore, based on the byte selection information Create a check bit corresponding to each , And finally add (mod2) it Can be asked.

The above is the case of the SEC-DED system, but the same applies to other error correction codes.

Example of Invention

FIG. 1 is a diagram showing a data system structure in one bank group showing an embodiment of the present invention. The partial write operation will be described with reference to FIG. However, the data width of the write / read operation handled here is 8 bytes.

When a partial write request is received from the SCU, the address associated with the request, write data, and mark data (8 bits) designating which byte among 8 bytes is to be written are received, and the corresponding registers 301 and 302 are received. And set to 303. The address of the address register 301 is sent to each bank (BK) and set in the address register 304 of the bank to be accessed. The write data is similarly set in the write data register 305 of the bank to be accessed. However, at this point, the mark data is not used and all bytes are set in the write data register 305.

On the other hand, in the check bit generation circuit (ECC generation A) 306, based on the mark data, the data in which only the bytes to be rewritten in the write data of the write data register 302 are taken out, that is, all the bytes not to be rewritten are set to “0”. Create data and generate a first partial check bit. The generated check bit is held in the check bit data buffer 307 until data is read from the area of the access address. The data read from the storage element group 308 of the access bank is set in the read data register 310 via the read data register 309 provided for each bank. Here, the read data is checked by the ECC check circuit 311, and if a correctable error is detected, it is corrected and registered.
Set to 312.

Next, in the check bit generation circuit (ECC generation B) 313, based on the mark data held in the mark data buffer 315, data in which all the bytes to be rewritten in the corrected read data are set to “0” is created. , Generate a second partial check bit. This second partial check bit is supplied to the check bit data buffer 3 in the exclusive OR circuit 314.
An exclusive OR (addition of mod2) is taken for each bit with the first partial check bit held in 07, and a check bit of data to be newly written in the partial write operation is generated.
The corrected read data in the read data register 312 and the finally generated check bit are sent to each bank through the data path 316.

In the write data register 305 of the access bank, the data of the byte that is not rewritten and the check bit are reset based on the mark data, and the data to be written is created. The updated data is written in the area of the access address. As a result, the byte to be rewritten in the partial write operation is SC
The write data from U is written, and the data already stored in the byte that is not rewritten is written again in the area of the access address. This completes the partial write operation.

FIG. 2 shows a detailed configuration of the check bit generation circuit (ECC generation A) 306. Here, the AND gate 401 means 1 byte, that is, 8 gates. Write data is 1
Each byte corresponds to 1 bit of mark data, and the data of the byte whose mark data is "1" is passed through to "0".
Set the byte data of "0". By inputting this to the ECC check bit generation circuit 402 based on the H matrix, the first partial check bit is obtained.

The check bit generation circuit (ECC generation B) 313 can also obtain a second partial check bit by the same configuration.

As described above, according to this embodiment, it is possible to reduce the amount of metal of the partial write data buffer to 1/8 of that of the conventional configuration.

〔The invention's effect〕

According to the present invention, the amount of hardware of the data buffer for partial writing can be reduced to (the number of inspection bits) / (the number of information bits), so that it is physically and economically possible to realize a storage device having a multi-bank structure. In terms of ease.

[Brief description of drawings]

FIG. 1 is a structural diagram of a data system in one bank group according to the present invention, FIG. 2 is a circuit configuration diagram for generating a partial check bit, and FIG. 3 is a block showing a connection between a main memory device and a main memory control device. FIG. 4 and FIG. 4 are data system structure diagrams in one bank group having a conventional configuration. 307 ... Data buffer for check bits 306, 313 ... Partial check bit generation circuit 305 ... Write data register provided for each bank

Claims (1)

[Claims] 1. A plurality of storage units (banks), each bank operates independently of each other, and each bank has a number of information bits (hereinafter referred to as a first number of bits) as an information bit. ) A storage device group having a smaller number of bits (hereinafter, referred to as a second number of bits) for storing check bits, and a storage device having a write data register for writing data to the storage device. A means for writing the first bit number of write data in the write data register in response to the partial write request at the time of starting a read operation in response to the partial write request for partially rewriting the contents of the storage element, Of the write data of the first bit number that accompanies the partial write request, the data that is not rewritten for the partial write request is set to "0". A first check bit generation circuit for generating the first check bit of the second number of bits from the data bit of the data, for holding the first check bit generated by the first check bit generation circuit. A check bit data buffer having the second bit number width, of the data read from the storage element in the read operation based on the activation, information of data in which a rewriting portion related to the partial write request is set to "0" A second check bit generation circuit for generating a second check bit of the second number of bits from a bit; and the first check bit in the check bit data buffer after the second check bit is generated. And bitwise exclusive OR of the second check bit with the second check bit
A third check bit generation circuit for generating a third check bit having the number of bits of, the information bit of a portion that is not rewritten in the data read by the read operation and having error correction performed, A storage device comprising means for setting in the write data register of a portion which is not rewritten by a partial write request, and means for setting the third check bit in the write data register.