JPS62214599A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To reduce the write cycle by not correcting a word read by one address at write, storing words except the object one word in a register, inputting a write word and writing said information to the address together with an ECC bit generated corresponding to the obtained information. CONSTITUTION:A block 50 including a write object work 1 is read and the information of new ECC bit is decided from a new word '1' to be written and a word 2 of no correction. Thus, switches 62, 63 are turned to the position (b) at an address bit An, a word '1' of the input buffer 42 and a word 2 on a bus BS2 are inputted to a register 52 and the words are inputted to an EEC code bit generating circuit 33. The words 1'', 2 and the new ECC bit are written in the block 50 via buses BW1-3 and write amplifiers 21-23. At read, one of the corrected words 1', 2' is outputted via the ECC correction 31 and mis- detection 32. Through the constitution above, the write cycle is reduced and the peripheral circuit is simplified.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention provides a semiconductor memory device having an ECC (F4 error detection and correction) function, particularly a semiconductor memory device in which the ratio of ECC bits to information bits is reduced. Short (I'm trying to do that.

[Conventional technology]

In memory LSIs, mounting an FCC circuit on the memory chip is being considered as a countermeasure against α-ray soft errors. In addition, in NVRAM, which is a combination of SRAM (static random access memory) and EEFROM (electrically erasable programmable read-only memory) integrated in cell units, the niE
The use of CC technology is being considered. In such a case, the ratio of the number of ECC bits to the number of information bits is a problem. That is, even if a 1-bit corrected Hamming code is used, the ratio between the number of information bits and the number of ECC bits is as shown in the table below.

Table 1 One word is determined by the number of parallel l10 (input/output) terminals of the integrated circuit, but if this is 4 bits, it is necessary to add 3 ECC bits to each information bit (4 bits) of 1 word, for example, 1024 words. In the case of an IC memory without the ECCl1 function, the total number of bits is 4096 bits, but when the ECC1 function is added, the total number of bits suddenly increases to 7168 bits. As is clear from Table 1, when the number of information bits (the number of bits in one word) is large, the ratio of ECC bits to the information bits becomes small, and there is less waste, so to speak. The number of bits per hit is usually 4 or 8, 16.32.・・・・・・
There are only a few multi-bit configurations such as...

Therefore, 2 or more words are treated as 1 block, and ECC is applied to it.
It is possible to add bits. For example, if two 4-bit words per word are made into one block and an ECC bit is added to this block, the word unit requires only 4 bits instead of 6 bits.

Furthermore, if one block consists of four 4-bit words, then only 5 ECC bits are required.

Figure 2 is a block diagram of the main parts of a memory IC in which 2 words constitute one block and ECC bits are added to it. 11 to 13 are sense amplifiers, 21 to 23 are write amplifiers, BSI to BS3, and BW1 to BW3. 31 is a bus, 31 is an ECC circuit, 32 is an error detection circuit, 33 is an FCC code bit generation circuit, 41 is an output cover/7th floor, 42 is an input cover sofa, and 43 is an input/output terminal. 50 is a memory block, specifically a group of memory cells on one word line.

This word line and therefore the memory block is selected with address bits Ao-An4, one bit less than address bits Ao-An4 of the word, and word 1.2 and so on.
EC ordered for these as one group
Consists of C bits. 51 is a read register for 2 words, 52 is a write register for 2 words, 61 is a successive word selection circuit that is switched by the remaining address bit An,
62 and 63 are new/old write word selection circuits.

In the memory having the above configuration, when reading, for example, the address bit An is used to access the memory block 50 (more specifically, by A O-A n-1), and the word 1 . Word 2. and ECC pin I- for each sense amplifier 11,12゜13 and bus BSI,
BS2. After passing through BS3, words-1 and 2 are sent to ECC circuit 3.
Once again, the word 1.2 and the ECC bits enter an error detection circuit 32 where error detection and correction is performed.

If there is an error, the corrected word 1.2 enters the register 5I, and the word selected by the switch 61 switched by the address bit An is output from the cover sofa 4.
1 and the input/output terminal 43.

The ECC bit of memory block 50 is set to 1 for word 1°2.
Since it is assigned as a group, only a small number of bits are required.

Since access can be made to each word as described above, there is no particular problem.

[Problem that the invention seeks to solve]

However, with this memory, the signal processing when writing data is complicated and time-consuming, and the read cycle has an SR of 100 nS at the latest.
In AM, it is difficult to execute all processing within such a short period of time. That is, in this memory, writing is performed by: 1) first reading the block 50 containing the word to be written (referred to as word 1); 2) reading word 2 read together with word 1;
Correct by CC circuit (word after correction is word 1').

2'), ■ New word to be written (word I) and a new EC from the corrected word 2'.
Determine the C bit (this process sets the switches 62 and 63 to the b side according to the address An, loads word 1'' of the input cover sofa and word 1' of the register 51 into the register 52, and generates an ECC code bit. (This is done by inputting it to the circuit 33), ■Word 1'', Word 2'
, and new ECC bits to write amplifiers 21 to 23
It is necessary to perform the process in four steps: write to block 50 through 4 steps, and the processing time of each step is TR + T, where read access time is TR, ECC correction time is Tc, FCC generation time is TG, and write access time is 7'w.
It is difficult to make c + T O, + T w less than, for example, the above-mentioned 100 nS in one write cycle.

The present invention aims to shorten the write cycle and keep it within the required time by omitting part of the above processing.

[Means for solving problems]

The present invention provides a semiconductor memory device that has an error detection and correction function and adds ECC bits to multiple words that are simultaneously selected. As it is,
EC generated for the multi-word data created in this way by loading all but one word to be written into the write register and inputting the one word to be written into the register.
It is characterized in that the plural word data is written to the address along with the C bit.

[Effect]

If the probability of occurrence of soft errors in SRAM is small, there is no practical problem in omitting ECC correction for write cycles, except for read cycles. If the ECC correction process is omitted and the write cycle is executed, the time Tc required for ECC correction can be removed, and reading and writing can be executed simultaneously, so the required time is 'rR+Tc,+Tw
Instead, the longer one of TR and TW plus TG is sufficient.

〔Example〕

FIG. 1 is a block diagram of main parts showing an embodiment of the present invention, and the same parts as in FIG. 2 are given the same reference numerals.

Ru. As is clear from comparing the two, there is no particular difference in the read system, but the write system is slightly different, and words 1 and 2 are input to the write register 52 from the bus BSI and BS2 via switches 62 and 63. It looks like this. The write cycle of this memory is explained in the same way as in Figure 2.
■ Read the block 50 that includes word 1 to be written; ■ Determine the new ECC bit data from the new word 1" to be written and the word 2 that is not included in the correction just read. switches the switches 62 and 63 to the b side, inputs word 1 of the input buffer 42 and word 2 on the bus BSZ to the register 52, and inputs these words to the ECC code pin I-generating circuit 33.
(This is done by inputting ``Word 1'', Word 2)
, and a new ECC bit is written to block 50 via path BWI~3 and write amplifiers 21~23, and is completed with these three steps.

The time required for the above steps
Only r'G and Tw, and the time required for ECC correction Tc
becomes unnecessary. This eliminates the need for an internal ECC correction signal and its generation circuit. Also, a new word 1'' can begin to be written to the register 52 at step (2), and only the longer of Tw and TR will be effective.

Note that in the read cycle, the ECC correction circuit 31 and error detection circuit 32 are used, and the corrected words 1' and 2'
One of them is selected and output.

〔Effect of the invention〕

As described above, the present invention has the advantage of being able to reduce the number of ECC bits in a memory with ECC, 11 function, reduce write cycles, and simplify peripheral circuits.

[Brief explanation of drawings]

FIG. 1 is a block diagram of main parts showing one embodiment of the present invention, and FIG.
The figure is a block diagram of main parts of a conventional memory with FCC function. In the figure, 11 to 13 are sense amplifiers, 21 to 23 are write amplifiers, 31 is an FCC circuit, 32 is an error detection circuit, and 3
3 is an ECC code bit generation circuit, 43 is an input/output terminal, 5
2 is an internal register.

Claims (1)

[Claims] In a semiconductor memory device that has an error detection and correction function and adds ECC bits to multiple words that are selected simultaneously, in a write cycle, multiple words read by one address are written as they are without error correction. Load all but one target word into the write register, input the one word to be written into the register, and write the multi-word data to the address along with the ECC bit generated for the multi-word data thus created. A semiconductor memory device characterized in that it is configured to