JP2567986B2 - Data processing system - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing system, and more particularly to a data processing system that has a plurality of buses and that secures data in data transfer between the buses.

[Conventional technology]

Conventionally, this type of data processing system performs a parity check when inputting data from one bus, stores the parity bit in the data in an internal buffer, and outputs the data to the other data bus. In doing so, a parity check was performed on the data with the parity bit added, and it was confirmed whether the data was correct.

[Problems to be Solved by the Invention]

In the conventional data processing system described above, the parity check is performed at the input / output unit of the bus, and the parity bit is added to the internal buffer as well, so it is possible to detect a bit error in the internal buffer or the input / output register. However, there is a problem in that it is impossible to detect an update in the input / output register, a failure in the write / read control circuit for the data buffer, and a failure in the read / write control circuit.

It is an object of the present invention to provide a data processing system capable of detecting a failure in a write / read control circuit for a data buffer.

[Means for solving the problem]

The data processing system of the present invention is a data processing system in which there are a plurality of buses for transferring one or more addresses and data in one bus cycle, and the buses are connected to each other by a bus interface circuit. Input / output parity register means for storing a parity bit each time data bus information is input, (B) input / output parity inversion register means for storing inverted parity bits, and (C) parity bits from the input / output parity register means. Address / data buffer parity means for storing (D) Address / data buffer inversion parity means for storing parity bits inverted by the input / output parity inversion register means, (E) Input / output parity register means and input / output parity inversion register Paris comparing values with means A comparison means, (F) a check timing generation means for generating a timing for checking the comparison result every time the inputted information is output to the data bus, (G) an input / output parity register means at the start of the bus cycle, Output parity inversion register means, address
Reset means for resetting the data buffer parity means and the address / data buffer inversion parity means.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

 FIG. 1 is a block diagram of an embodiment of the present invention.

The data processing system shown in FIG. 1 includes an address / data bus 1, an address / data bus 2, an input / output register 3, an input / output parity register 3P, an input / output parity inversion register 3P3, an address / data buffer 4, an address / data buffer 4.
Data buffer parity 4P, address / data buffer inversion parity 4, input / output register 5, input / output parity register 5P, input / output parity inversion register 5, flag reset / check timing generation circuit (check timing generation means, reset means) 7, parity It is composed of a check circuit 9, parity comparison circuits 61 and 62, and parity comparison error flags 81 and 82.

 Next, the operation will be described.

In FIG. 1, when information is transferred from the address / data bus 1 to the address / data bus 2, if a bus cycle occurs in the address / data bus 1, the flag reset signal 7a of the flag reset / check timing generation circuit 7 causes , I / O parity registers 3P, 5P, I / O parity inversion registers 3, 5, address / data buffer parity 4P, and address / data buffer inversion parity 4 are reset. Every time the address and data of the address / data bus 1 are input to the input / output register 3, the parity is checked by the parity check circuit 9 connected to the address / data bus 1, and the input / output parity register 3P and the input / output parity inversion register The parity bit of the address / data bus 1 and the inverted parity bit are input to 3 respectively.

When the information is transferred from the input / output register 3 to the address / data buffer 4, the contents of the input / output parity register 3P and the input / output parity inversion register 3 are respectively transferred to the address / data buffer 4.
The data is transferred to the data buffer parity 4P and the address / data buffer inversion parity 4. Further, the contents of the address / data buffer 4 are transferred to the input / output register 5, and the parity information of the address / data buffer parity 4P and the address / data buffer inversion parity 4 is transferred to the input / output parity register 5P and the input / output parity inversion register 5. At the same time, the parity comparison circuit 62 compares the contents of the I / O parity register 5P and the I / O parity inversion register 5 through the I / O parity register signal 5a and the I / O parity inversion register signal 5b to determine the address of the I / O register 5, Each time data is output to the address / data bus 2, the flag reset / check timing generation circuit 7 generates a parity comparison check timing signal 7c, and the comparison result of the parity comparison circuit 62 is stored in the parity comparison error flag 82.

Similarly, when information is transferred from the address / data bus 2 to the address / data bus 1, if a bus cycle occurs, the I / O parity register 3P, the I / O parity inversion register 3, the address / data buffer parity 4P, Address / data buffer inversion parity 4,
I / O parity register 5P and I / O parity inversion register 5 are reset,
Each time the address and data of the data bus 2 are input, the parity is checked by the parity check circuit 9 connected to the address / data bus 2, and the input / output parity register 5P and the input / output parity inversion register 5 are respectively supplied with the address / data bus 2 The parity bit and the inverted parity bit are input.

When the information is transferred from the input / output register 5 to the address data buffer 4, the contents of the input / output parity register 5P and the input / output parity inversion register 5 are transferred to the address / data buffer parity 4P and the address / data buffer inversion parity 4, respectively. . Further, the contents of the address / data buffer 4 are transferred to the I / O register 3, and the parity information of the address / data buffer parity 4P and the address / data buffer inversion parity 4 is transferred to the I / O parity register 3P and the I / O parity inversion register 3. At the same time, the parity comparison circuit 61 compares the contents of the input / output parity register 3P and the input / output parity inversion register 3 through the input / output parity register A signal 3a and the input / output parity inversion register A signal 3b.
Each time the address and data of the above are output to the address / data bus 1, the flag reset / check timing generation circuit 7 generates the parity comparison check timing signal 7b, and the comparison result of the parity comparison circuit 61 is stored in the parity comparison error flag 81. To be done. That is, if the parity and the inverted parity are not correctly written after the start of the bus cycle, an error will be detected.

〔The invention's effect〕

As described above, according to the present invention, an inversion bit is added to the parity of the address and data parts, the parity bit and the inversion parity bit are set to a specific value at the start of the bus cycle, and comparison is performed every time data is output. By doing so, it is possible to detect a failure with respect to the write / read control circuit for the data buffer.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention. 1 ... Address / data bus, 1P ... Address / data bus A parity, 2 ... Address / data bus, 2P ...
Address / data bus B parity, 3 ... I / O register, 3a ... I / O parity register A signal, 3b ... I / O parity inversion register A signal, 3P ... I / O parity register, 3 ... I / O parity inversion Register, 4 ...
... Address / data buffer, 4P ... Address / data buffer parity, 4 ... Address / data buffer inversion parity, 5 ... I / O register, 5a ... I / O parity register B signal, 5b ... I / O parity inversion register B signal, 5P ... I / O parity register, 5 ...
Input / output parity inversion register, 7 ... Flag reset
Check timing generator circuit, 7a ... Flag reset signal, 7b, 7c ... Parity comparison check timing signal,
9 ... Parity check circuit, 61, 62 ... Parity comparison circuit, 81, 82 ... Parity comparison error flag.

Claims (1)

(57) [Claims] 1. A data processing system in which there are a plurality of buses for transferring one or more addresses and data in one bus cycle, and the buses are mutually connected by a bus interface circuit. Input / output parity register means for storing a parity bit each time information is input, (B) input / output parity inversion register means for storing an inverted parity bit, (C) address for storing a parity bit from the input / output parity register means Data buffer parity means, (D) address for storing parity bits inverted by the input / output parity inversion register means, data buffer inversion parity means, (E) of the input / output parity register means and input / output parity inversion register means Parity comparison means for comparing values, (F Check timing generation means for generating a timing for checking the comparison result every time the inputted information is output to the data bus, (G) the input / output parity register means, input / output parity inversion register means, address・
A data processing system, comprising: a data buffer parity means and a reset means for resetting an address / data buffer inversion parity means.