JPH06103469B2 - Memory control circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a memory control circuit having a function of detecting and correcting an error in read data, in which data with a Hamming check bit read from a memory contains an uncorrectable error. If it is, the operator converts it into data that can be easily recognized and outputs it.

[Conventional technology]

If the data stored in the memory such as the main memory of the computer has a bit error, the Hamming code is sometimes used to correct and output the bit error. By using the Hamming code, it is possible to detect a 2-bit error in the read data and correct the 1-bit error.
Of course, a larger number of bit errors can be detected and the error can be corrected, but since the number of bits of the Hamming code becomes large in this case, it is common to use 2-bit error detection and 1-bit error correction. Therefore, if a 2-bit error occurs, it cannot be corrected. When an uncorrectable error occurs, conventionally, uncorrectable data is directly output to a maintenance display device such as SVP (service processor), or
Instead of uncorrectable data, special data of all 0s or all 1s is output to the device.

[Problems to be solved by the invention]

However, with this method, the operator cannot determine which part is uncorrectable data even when looking at the maintenance display device. Also in this method, for example, even if all 0s are displayed, the pattern of all 0s is often found in normal data (cleared data, etc.), so it is difficult to distinguish it from this, and test errors are likely to occur. The present invention is intended to improve the above points by outputting a specific pattern which is less likely to occur in normal operation and which can be easily seen by an operator as uncorrectable data.

[Means for solving problems]

The present invention relates to a circuit that detects an error in data with a Hamming check bit read from a memory unit and generates an output indicating an error bit, and an exclusive circuit that inverts the corresponding bit of the data by the output of the circuit to correct the error. OR gate group, and a register for storing specific data which indicates an uncorrectable error, has a low probability of occurring as data normally written in the memory, and is easily recognized as an uncorrectable error when displayed or printed, A selector for inputting specific data of the register to the exclusive OR gate group instead of the data read from the memory unit when an uncorrectable error occurs, and a final output register to which the output of the exclusive OR gate group is set. Maintain the contents of the final output register at least when an uncorrectable error occurs It is characterized in that so as to output to the display device.

[Action]

When an uncorrectable error occurs, if a specific pattern that is XDBEE is output instead of the data, the probability of occurrence of this data is that it frequently occurs due to clear such as all 0 or all 1 or initial setting. However, since it is a very small value (because it is a 4-bit hexadecimal code, the probability that one of them will be 16 ^-4 ), it is extremely rare for an operator (maintenance staff) to mistakenly judge normal data of the same pattern as uncorrectable data. become. Moreover, since the above-mentioned specific pattern DBEE uses the acronym for Double Bit Error, there is an advantage that the operator can easily recognize (memorize). Hereinafter, this will be described in detail with reference to the illustrated embodiment.

〔Example〕

FIG. 1 is a block diagram of a memory control circuit showing an embodiment of the present invention. MEM is a memory body including a memory cell array, a decoder, and a sense / write amplifier, R1 is a register for write (write) control, and one of 1, 0 is set to set the memory MEM in the write mode and the other is set. To read mode. R2 is read (R; read)
/ Register to which write (W) address is set, DIN
0 and 1 are registers to which input data (write data) DIN is set, HMGEN is a circuit that generates a humming code (humming check bit) for the input data, HCIN1
Is a register in which the Hamming code is set. Also, DOUT0 and 1 are registers to which data (read data) read from the memory MEM is set, and HC0 and 1 are memory M.
This is the register to which the Hamming code read from EM is set. HMSG is a circuit that generates a syndrome bit from the data read from the memory MEM and a Hamming code, PG is a circuit that generates a parity bit from the data, and HS and P1 are registers to which these Hamming syndromes and parity are set. HSDEC is a decoder that receives Hamming syndrome, determines correctable error, uncorrectable error, and correct data, and creates collection information. Its output is data correction circuit DCC, Hamming code correction circuit HCC, Hamming. It is sent to the error bit logic circuit MHEBL and the parity correction circuit PCC. DOUT2 is the register where the corrected read data is set, HC2 is the register where the corrected Hamming code is set, EBL is the register where the error bit position information is set, and P2 is the corrected parity bit. It is a register.

First, to explain general read / write control of memory, the write enable WE becomes H (high) level at the time of writing, the write destination address is set in the register R2, and the write input from the data input bus is performed. Data is set in input register DIN0. This register DIN0
The write data set to is transferred to the input register DIN1 of the next stage in the next cycle, and is also added to the humming generation circuit HM GEN, which creates a humming check bit from the write data and uses it for the hamming check register. Set to HCIN1. In the next cycle, the contents of the registers DIN1 and HCIN1 (data with Hamming check bit) are written in the memory MEM.

At the time of reading, WE becomes L (low) level, the read address is set in the register R2, the read is performed by these, the read data from the memory MEM is set in the register DOUT0, and the humming check bit is humming check. It is set in register HC0. These are shifted to the registers DOUT1 and HC1 of the next stage in the next cycle. At this time, the Hamming syndrome generator HMSG creates the syndrome data from the read data and the Hamming check bit and sets it in the Hamming syndrome register HS. Also a parity generator
The PG creates a parity bit from the read data and sets it in the parity bit register P1.

The Hamming syndrome decoder HS DEC determines whether the read data from the Hamming syndrome in the register HS is correct data, a data including a correctable error (1 bit error in this example), or an uncorrectable error (same as above). It is determined whether the data includes an error of 2 bits or more), and the three types of determination results and collection information are output. The data correction circuit DCC, the Hamming correction circuit HCC, and the parity correction circuit PCC make respective corrections based on the determination result and the collection information.

FIG. 2 is a detailed diagram showing the data collection circuit DCC and its peripherals related to the present invention. These are the error byte due to the output of the exclusive OR gate EOR inserted in each bit of the read data and the decoder HSDEC. A decoder DEC ₁ that produces an output that indicates, a decoder DEC ₂ that produces an output that indicates the same error bit, and these decoders
It consists of AND gates AND, which are provided in the same number as the exclusive OR gates, receiving the outputs of DEC ₁ and DEC ₂ .

To explain the operation, in the case of a correctable error, for example, the read data is 16 bits, that is, 2 bytes, and the error byte is indicated by DEC _1.
The output of the AND gate AND, which is indicated by DEC ₂ and corresponds to the bit in error (thus, this bit is in error), becomes 1 and the outputs of the other AND gates become 0. In the case of a correctable error, the selector SEL selects the read data from DOUT1, so that in this example, 16-bit read data is applied to one input of 16 exclusive OR gates EOR. The exclusive OR gate becomes through when one input is 0, and becomes an inverter when 1 is input. Therefore, only the exclusive OR gate EOR in which the output of the AND gate AND is 1 inverts the read data bit, and thus error correction is performed. On the other hand, when an uncorrectable error occurs, the uncorrectable error signal output from the decoder HSDEC becomes "1", and the selector SEL selects the specific data register R3 instead of the register DOUT1 and selects the specific data XDBEE.
Is output. At this time, the correctable error signal output from the decoder HSDEC becomes "0", the output of the AND gate AND becomes 0, and therefore the exclusive OR gate EOR becomes through,
Therefore, the specific data is set in the final output register DOUT2. This is taken into SVP and displayed on its display. At the time of correct data, both the uncorrectable error signal and the correctable error signal are “0”, and the data in the register DOUT1 is set in the register DOUT2 as it is.

The specific data XDBEE is therefore displayed in binary in the register R3.
Among them, it is a 16-bit binary code 1101, 1011, 1110, 1110, but it is displayed as the character "DBEE" on the SVP display part. In the data collection circuit DCC, this specific code is held in advance in a register R3 (this specific code may be a non-volatile memory such as PROM since it does not need to be changed once it is determined), and is selected and output by the selector SEL. To do. By the way, if all 0 or all 1 pattern is used in binary display as in the past, X is displayed in hexadecimal display.
0000 or XFFFF can be used to provide some sort of distinctiveness, and since the pattern can be generated only by turning the gate on and off, no special register is required, but this pattern can be used even during normal operation such as clearing. Since it occurs, it is difficult to determine whether it is a double bit error. In this respect, it is easy to remember that the specific code XDBEE of the present invention is a literal double bit error once memorized, and the probability that the hexadecimal code DBEE occurs in normal operation is 1/65536. However, there is almost no concern about misidentification based on normal data.

〔The invention's effect〕

As described above, according to the present invention, when the data in the memory is read and there is data having an uncorrectable error in it, the specific data DBEE is displayed in the SVP. There is an advantage that the work at the time of testing for finding out the data possessed becomes significantly simple and efficient.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a detailed view of essential parts thereof. In the figure, MEM is memory, DCR is data collection circuit, HS
DEC is a Hamming syndrome decoder, and SEL is a selector for specific data and read data.

Claims (1)

[Claims] 1. A circuit for detecting an error in data with a Hamming check bit read from a memory section to generate an output indicating an error bit, and inverting the corresponding bit of the data by the output of the circuit to correct the error. A group of exclusive OR gates and a register that stores uncorrectable errors and that has a low probability of occurring as data that is normally written to memory and that is easily recognized as an uncorrectable error when displayed or printed. A selector for inputting specific data of the register to the exclusive OR gate group instead of the data read from the memory unit when an uncorrectable error occurs, and a final output register to which an output of the exclusive OR gate group is set The contents of the final output register are retained at least when an uncorrectable error occurs. Memory control circuit being characterized in that so as to output to use the display device.