JPH0738398A - Clock switching circuit - Google Patents

Abstract

PURPOSE:To provide a clock switching circuit which switches a clock without generating a glitch noise as to the clock switching circuit which outputs by switching plural clocks with phases different from each other synchronized with a master clock arbitrarily. CONSTITUTION:A frequency divider circuit 1 generates a first clock CLK0 and a second CLK1 with different from each other by 90 deg. by frequency-dividing the master clock MCLK. A synchronizing circuit 2 is constituted of a first flip-flop 21 operated by the falling of the master clock MCLK, and a second flip-flop 22 operated by the rising of the master clock MCLK. A selection circuit 3 is constituted of AND circuits 31, 32 and an OR circuit 33. The synchronizing circuit 2 synchronizes an asynchronous selection signal with the master clock, and generates selection signals SEL0, SEL1 provided with front and rear edges at the phase in the neighborhood of the center of the prescribed logical values of the clocks CLK0, CLK1, respectively.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock switching circuit, and more particularly to a clock switching circuit for arbitrarily switching and outputting a plurality of clocks having different phases synchronized with a master clock.

[0002]

2. Description of the Related Art Conventionally, a clock switch having a synchronization circuit for generating a switching signal (selection signal) of a selection circuit for selecting one of a master clock and a clock obtained by dividing the master clock by synchronizing with the master clock. A circuit is known (Japanese Patent Laid-Open No. 63-232615). FIG. 3 shows a circuit system diagram of an example of a conventional clock switching circuit in the case where the clock switching circuit is configured to switch between two types of clocks having phases opposite to each other, which are obtained by dividing a master clock.

In FIG. 3, the frequency dividing circuit 4 divides the master clock MCLK shown in FIG. 4 (A) by two, for example, and divides the phase by two to obtain a first clock CLK0 shown in FIG. 4 (B).
And a second clock CLK1 shown in FIG. 7C is generated, and these clocks CLK1 and CLK2 are input to the selection circuit 6, respectively.

The synchronizing circuit 5 uses the master clock MC mentioned above.
LK and the asynchronous selection signal ASYNC S shown in FIG.
EL is input and the asynchronous selection signal ASYNC SEL
Is generated in synchronization with the master clock MCLK, and a selection signal SEL as shown in FIG. 4 (E) is generated and input to the selection circuit 6.

As shown in FIG. 3, the selection circuit 6 includes 2-input AND circuits 61 and 62 to which clocks CLK0 and CLK1 are input to one input terminal, respectively, and a selection signal SEL.
Is provided to the other input terminal of the AND circuit 62, and a two-input OR circuit 64 to which the output signals of the AND circuits 61 and 62 are respectively input.

According to the clock switching circuit having such a configuration,
AND when the selection signal SEL is low level (L)
The AND circuit 62 of the circuits 61 and 62 opens the gate.
And the clock CLK1 is set to the AND circuit 62 and O.
It is selectively output through the R circuit 64. On the other hand, the selection signal S
When EL is at the high level (H), the AND circuit 61 of the AND circuits 61 and 62 is in the gate “open” state, and the clock CLK0 is the AND circuit 61 and the OR circuit 6
It is selectively output through 4.

As described above, in the conventional clock switching circuit, the selection signal ASYNC SE for clock switching is used.
Even if L is asynchronous with the master clock MCLK, the synchronization circuit 5 generates the selection signal SEL synchronized with the master clock MCLK to generate the clocks CLK0 and CLK1.
By selecting one of them, a clock output without noise is obtained.

[0008]

However, the above-mentioned conventional clock switching circuit has a configuration in which one of the two clocks CLK0 and CLK1 is selected by the single selection signal SEL synchronized with the rising edge of the master clock MCLK. Therefore, when the selection signal SEL changes from “H” to “L” in order to switch from CLK0 to CLK1, the AND circuit 61 immediately switches to the gate “closed” state.
The circuit 62 switches to the gate "open" state with a slight delay due to the delay time of the inverter 63.

Therefore, CL is selected before CLK1 is selected.
When K0 is prohibited and the falling edge of CLK0 is slightly faster than the rising edge of the master clock MCLK, as shown by point C in FIG. 4 (F), the selected clock CLK output from the OR circuit 64 is bearded. Glitch noise occurs.

Further, the selection signal SEL is set to the master clock M.
Even when it is generated so as to be synchronized with the falling edge of CLK, glitch noise may similarly occur in the output clock CLK. As described above, in the above-described conventional clock switching circuit, since the selection circuit 6 is selectively operated by the single selection signal SEL, there is a problem in that the output clock CLK may have noise.

The present invention has been made in view of the above points,
The selection signal that operates the selection circuit that selects the clock
An object of the present invention is to provide a clock switching circuit that solves the above-mentioned problems by providing the clock switching circuit corresponding to the selected clock.

[0012]

In order to achieve the above object, the present invention provides a frequency dividing circuit for dividing a master clock to generate a plurality of clocks having different phases, and a master clock and an asynchronous selection signal. A synchronization circuit that synchronizes an asynchronous selection signal that is input with the master clock and that generates a plurality of selection signals that each have a leading edge or a trailing edge at a phase near the center of a predetermined logical value of the plurality of clocks; A plurality of clocks and the plurality of selection signals are input, and a selection circuit that selects a desired clock among the plurality of clocks by the plurality of selection signals is provided.

[0013]

According to the present invention, the synchronizing circuit generates a plurality of selection signals in which the asynchronous selection signal is synchronized with the master clock, and the leading edge or the trailing edge of the plurality of selection signals has a predetermined number of clocks. Since the signals are generated so as to be positioned in the phase near the center of the logical value, the selection circuit can shift the switching timing for switching the selection clock at the leading edge or the trailing edge of the plurality of selection signals.

[0014]

1 is a circuit system diagram of an embodiment of the present invention, FIG.
Shows a time chart for explaining the operation of FIG. As shown in FIG. 1, the clock switching circuit of this embodiment includes a frequency divider circuit 1 to which a master clock MCLK is input, and a master clock M.
The synchronization circuit 2 to which the CLK and the asynchronous selection signal ASYNC SEL are input, and the selection circuit 3 are different from each other in the configuration of the synchronization circuit 2 and the selection circuit 3.

The frequency dividing circuit 1 has the same configuration as the conventional frequency dividing circuit 4, and divides the master clock MCLK shown in FIG. 2A by 2 to obtain a phase difference of 90 ° from each other as shown in FIG. 1
Clock CLK0 and a second clock CLK1 shown in FIG.

As shown in FIG. 1, the synchronizing circuit 2 comprises a first flip-flop 21 which operates at the falling edge of the master clock MCLK and a second flip-flop 22 which operates at the rising edge of the master clock MCLK. The Q output terminal of the flip-flop 21 is D of the flip-flop 22.
Asynchronous selection signal ASYNCS connected to the input terminal
EL is configured to be supplied to the D input terminal of the flip-flop 21.

The selection circuit 3 includes a first clock CLK0 from the frequency divider circuit 1 and a first selection signal SE from the synchronization circuit 2.
A first AND circuit 31 to which L0 is input, and a second AND circuit 32 to which the second clock CLK1 from the frequency dividing circuit 2 and the second selection signal SEL1 from the synchronizing circuit 2 are input. , A two-input OR circuit 33 to which the output signals of the AND circuits 31 and 32 are input.

Next, the operation of this embodiment will be described with reference to the time chart of FIG. Now, assuming that the output selection signal SEL0 of the synchronizing circuit 2 is "H" and SEL1 is "L", the AND circuit 31 is in the gate "open" state,
Since the AND circuit 32 is in the gate “closed” state, the first clock CLK0 shown in FIG.
Only the selected output clock CLK from the OR circuit 33
Is output as.

Here, when the "H" asynchronous selection signal ASYNC SEL for selecting CLK1 is input at the time point indicated by a in FIG. 2D, the master clock M immediately after the time point a.
At the falling input time t ₁ of CLK, the flip-flop 21 in the synchronization circuit 2 operates and the asynchronous input signal A at that time
The SYNC SEL is latched, and the "L" signal having the opposite polarity to the latched level is output from the Q bar output terminal.
As shown in (E), it is output as the first selection signal SEL0.

Then, the master clock M following the time t ₁
The flip-flop 22 operates at a time t ₂ after a half cycle of CLK, the Q output signal level “H” of the flip-flop 21 at that time is latched, and the “H” signal is output from the Q output terminal of FIG. ), The second selection signal SEL
Output as 1.

As a result, the AND circuit 31 is brought into the gate “closed” state at the time point t ₁ to inhibit the selection of the clock CLK0, and then the AND circuit 32 is brought into the gate “open” state at the time point t _2. After t _{2, the} clock CLK1 is AN
It is taken out as an output clock CLK through each of the D circuit 32 and the OR circuit 33.

Here, the time point (trailing edge) t ₁ at which the selection signal SEL0 falls is at a substantially central position during the period when the clock CLK0 is "L", as shown in FIG. , When the selection signal SEL1 rises (leading edge) t ₂
2C, the clock CLK1 is "L" as shown in FIG.
The position is approximately the center of the period.

Therefore, during the period from the time t ₁ to the time t ₂ , the AND circuits 31 and 32 are both in the gate “closed” state, the output clock CLK is “L”, and the falling time t of the master clock MCLK. even if no falling edge of the clock CLK1 is matched in _1, the clock selected by the selection circuit 3 at a later time t ₂ is switched to the CLK1 from CLK0, glitches as shown in FIG. 2 (G) at the switching point No noise is generated.

Then, in order to select CLK0, as shown in FIG.
At the time point indicated by b in (D), the asynchronous selection signal ASYNC S
When EL is set to "L", the master clock M immediately after that is set.
The flip-flop 21 operates at the falling time t ₃ of CLK, and the selection signal SE extracted from the Q-bar output terminal thereof is output.
L0 rises to "H" as shown in FIG. Further, the flip-flop 22 operates at the rising time point t ₄ of the master clock MCLK immediately after the time point t ₃ , and the selection signal SEL1 taken out from the Q output terminal thereof is as shown in FIG. 2 (F).
Fall to L ".

As a result, the AND circuit 31 is brought into the gate "open" state at the time point t ₃ to select the clock CLK0, and the AND circuit 32 is closed at the time point t ₄ thereafter.
In this state, selection of the clock CLK1 is prohibited. Here, a time point (leading edge) t ₃ at which the selection signal SEL0 rises.
2B, the clock CLK0 is "L" as shown in FIG.
2C, and the time point (trailing edge) t ₄ at which the selection signal SEL1 falls is approximately the center of the period during which the clock CLK1 is "L" as shown in FIG. 2C. The central position. Therefore, glitch noise does not occur even when the clocks CLK1 and CLLK2 are switched.

As described above, according to this embodiment, a plurality of clocks can be switched without generating glitch noise, and at the same time, the master clock MCLK of 2 can be switched.
Even if there is no double frequency clock, master clock MC
The clocks of CLK0 and CLK1 can be switched in the unit of half cycle of LK.

The present invention is not limited to the above-described embodiment. For example, the frequency dividing circuit 1 is configured to divide the master clock into four phase clocks having a phase difference of 90 ° from each other, and a synchronizing circuit. 2 is configured to generate a 4-phase selection signal that changes in synchronization with the master clock at a position near the center of a predetermined logical value of the corresponding clock among these 4-phase clocks. It is also possible to configure the selection circuit to select an arbitrary one of the clocks.

[0028]

As described above, according to the present invention,
Since the selection circuit shifts the switching timing for switching the selection clock at the leading edge or the trailing edge of the plurality of selection signals so as to have the predetermined logical value of the corresponding clock, the plurality of clocks can be switched without generating glitch noise. it can. Further, according to the present invention, the clock can be switched in units of half cycle of the master clock.

[Brief description of drawings]

FIG. 1 is a circuit system diagram of an embodiment of the present invention.

FIG. 2 is a time chart for explaining the operation of FIG.

FIG. 3 is a circuit diagram of a conventional example.

FIG. 4 is a time chart for explaining the operation of FIG.

[Explanation of symbols]

 1 Frequency divider circuit 2 Synchronization circuit 3 Selection circuit 21, 22 Flip-flop 31, 32 AND circuit 33 OR circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H03K 17/16 F 9184-5J

Claims (2)

[Claims] 1. A frequency dividing circuit for dividing a master clock to generate a plurality of clocks having different phases, the master clock and an asynchronous selection signal are input, and the asynchronous selection signal is synchronized with the master clock. And a synchronization circuit that generates a plurality of selection signals each having a leading edge or a trailing edge in a phase near the center of a predetermined logical value of the plurality of clocks, and the plurality of clocks and the plurality of selection signals are input. And a selection circuit for selecting a desired clock from the plurality of clocks by the plurality of selection signals. 2. The frequency dividing circuit generates first and second clocks having different phases, and the synchronizing circuit outputs a first selection signal synchronized with a falling edge of the master clock and a rising edge of the master clock. Generates a synchronized second selection signal,
The selection circuit selects the first clock when the first selection signal has a predetermined logical value, and selects the second clock when the second selection signal has a predetermined logical value. The clock switching circuit according to claim 1.