JP2595887B2 - Bit synchronization circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bit synchronization circuit, and more particularly to a bit synchronization circuit for burst signals.

[0002]

2. Description of the Related Art Conventionally, a bit synchronization circuit of this type has been disclosed in, for example, IEICE Technical Report CS92-3, 19
92.5.28 "and" 1991 IEICE Autumn Meeting B-601, 602 ".
(Passive Double Star Passive Double
Star) configuration of the optical line transmission system,
It is used for synchronization with a burst signal received at a different phase for each subscriber.

FIG. 2 is a block diagram showing an example of a conventional bit synchronization circuit. FIG. 2 shows a case where the clock has four phases. The bit synchronization circuit shown in FIG.
A clock selection circuit 250 and a clock selection circuit 2 which receive a multiphase clock 170 which is an output of 0 and data 110 as inputs.
Delay element 260, data 110, with 50 outputs as inputs
And an elastic store 150 to which the output of the delay element 260 and the output of the frequency dividing circuit 230 are input.

The clock selection circuit 250 includes a selector 251 that receives the multiphase clock 170 and the output of the up / down counter 252 as inputs, an up / down counter that receives the data 110 as a clock input, and uses the output of the selector 251 as an up / down control signal. 252.

FIGS. 3A and 3B are block diagrams showing a configuration example of a clock multiphase circuit. The clock multiphase circuit 130 is configured by cascade connection of delay elements 131 having the reference clock 120 as an input at the first stage.

The clock multi-phase circuit 204 is formed by cascading D-type flip-flops (DFFs) 242. Half of the DFFs 242 are the system clock 2
20 is a clock input, and half are system clocks 22
0 is the clock input, and half are the system clock 220
Is inverted by the inverter 241 as a clock input. In this case, assuming that the number of polyphase clocks is N and the cycle of the reference clock is T, the system clock needs to have a cycle of 2T / N. FIG. 4 is a waveform diagram showing the relationship between each clock and data. The multi-phase clock 170 is T /
It is desirable to have a phase difference every N.

Next, the circuit of FIG. 2 will be described with reference to FIG. It is assumed that the up / down counter 252 before data arrival outputs a count value of 0, whereby the phase 1 of the multiphase clock 170 is selected. The data 110 changes at the timing shown in FIG. 4, and the up / down counter 252 returns the count value when the up / down control signal is at the HI level, and advances the count value when the up / down control signal is at the LO level.

The data 110 arrives and the clock input of the up / down counter 252 rises. Now, since the selector 251 is outputting the phase 1 clock, the up / down control signal of the counter 252 at this time is LO, so the counter 252 advances the count value, whereby the selector 251 switches the phase 2 clock. Output. Next, when the data rises, the counter 252 similarly advances the count value because the clock is LO at this time, whereby the selector 251 outputs the phase 3 clock.
Next, when the clock rises, the counter 252 returns the count value this time because the clock is HI at this time.
The selector 251 outputs a phase 2 clock. As described above, the counter 252 evaluates the high and low of the clock selected by the selector 251 when the data rises, and controls the rising of the data to coincide with the falling of the clock. In the case of FIG. 4, the clock of phase 2 and the clock of phase 3 are alternately selected at every rising edge of the data.

The selected clock is supplied to a delay circuit 260
To optimize internal delays, elastic store 1
It becomes 50 write clocks. The elastic store 150 outputs the data 160 using the clock 270 output from the frequency dividing circuit 230 as a read clock.

[0010]

However, in the above-mentioned conventional bit synchronization circuit, a counter is used as means for selecting and controlling a multi-phase clock. 1, on the head of
An alternate bit sequence of 0 is added. This is called a preamble bit), and there is a problem that the time until synchronization is long.

An object of the present invention is to provide a bit synchronization circuit which eliminates the above-mentioned disadvantages.

[0012]

SUMMARY OF THE INVENTION In order to eliminate the above-mentioned drawbacks, a bit synchronization circuit according to the present invention comprises a clock multi-phase circuit which receives a reference clock and outputs a plurality of clock signals having N different phases. A clock selection circuit that receives the N plurality of clock signals and the received data;
An elastic store (memory) for writing received data using an output of the clock selection circuit as a write clock and outputting data using a reference clock as a read clock, wherein the clock selection circuit outputs an i-th ( (i is an integer from N to N) as a clock input, an output of the i-th NOR circuit as a reset input, and a data input fixed to a predetermined value.
DFF circuit, an N + 1-th DFF circuit for receiving data as a clock input, an output of a delay element as a reset input, and a data input fixed at a high level, and the delay for receiving an output of the N + 1-th DFF circuit as an input. An element and an i-th NOR input to which non-inverting outputs of DFF circuits other than the i-th DFF circuit among the first to N + 1 DFF circuits are input
Circuit, and an i-th A input to which an i-th clock signal of the plurality of clocks and a non-inverting output of the i-th DFF circuit are input.
An ND circuit, and an OR which receives the outputs of the first to Nth N AND circuits and inputs the outputs to the elastic store
Circuit.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a first embodiment of the present invention. The case where the clock has four phases is shown.

The bit synchronization circuit of the present invention includes a clock multiphase circuit 130 having a reference clock 120 as an input, a multiphase clock 170 output from the clock multiphase circuit 130, and a clock selection circuit 140 having data 110 as inputs. , The data 110, the output of the clock selection circuit 140, and the reference clock 120 as inputs.

The clock selection circuit 140 includes a DFF 14
1, DFF142, NOR143, AND144, OR
145 and a delay element 146. D
The FF 141 inputs the data 110 as a clock, and the delay element 1
The output of 46 is a reset input, and the data input is fixed at a high level (HI). The delay element 146 is
The inverted output of F141 is input, and DFF142, AND
144 is connected to each of the multi-phase clocks 170 by one set. The NOR 143 is a DFF 141
And the outputs of all the other DFFs 142 that do not have their own output and their own output as the reset input. DFF14
2 has a clock 170 as a clock input, an output of the NOR 143 as a reset input, and a data input of a high level (H
I). AND 144 is the clock 17
0 and the output of the DFF 142 are input, and the OR 145 receives the outputs of all the ANDs 144.

Next, the operation of the bit synchronization circuit shown in FIG. 1 will be described. The clock multi-phase circuit 130 receives the reference clock 120
To generate N clocks 170 with a delay for each T / N (T is the cycle of the clock, N is the number of polyphases). The clock selection circuit 140 evaluates the rise of the data 110, selects a clock for writing the data 110 from the clock 170, and outputs the selected clock. Elastic store 1
Reference numeral 50 reads data using this clock as a write clock and outputs data 160 as a read clock using the reference clock 120.

Next, the operation of the clock selection circuit 140 will be described. When the data 110 rises, the DFF 14
1 outputs HI. This HI output is the delay element 146
, And then goes to a low level (LO). While the output of the DFF 141 is HI, the output of the NOR 143 is LO, so that the DFF 142 is in the reset state and the output is LO. Next, when the output of the DFF 141 becomes LO, the reset of the DFF 142 is released. Thereafter, when one of the clocks 170 rises, the output of the DFF 142 connected to that clock becomes HI, the other DFFs 142 are reset, and their outputs are set to LO. The clock 17 connected to the DFF 142 whose output is LO is output by the AND 144.
0 is not output. Thereby, a clock is selected. Thereafter, each time the data 110 rises, this operation is repeated. The clock multi-phase circuit 240 may be used instead of the clock multi-phase circuit 130.

Next, a second embodiment will be described with reference to the drawings. FIG. 5 is a block diagram showing a second embodiment of the present invention. FIG. 5 shows a case where the clock has four phases.

The bit synchronization circuit 100 receives the data 110 and the reference clock 120 generated by the analog PLL 520 as inputs.
An output clock 530 of 0 is input. PLL52
0 is a phase comparator 521 that receives the data 110 and the output of the inverter 510 as inputs, a loop filter 522 that receives the output of the phase comparator 521 as an input,
And a holding circuit 523 which receives the output of the second and the holding signal 540 as inputs.
And a VCO (voltage controlled oscillator) 524 to which an output of the holding circuit 523 is input. The delay element 146 in the clock selection circuit 140 sets a delay to a value obtained by adding a data jitter width to T / 4 (T is a data period).

Next, the operation will be described. Since the clock selection circuit 140 sets the delay element 146 as described above, after the data 110 rises, T / 4 + α (α:
The clock 530 having the initial phase difference 0 <α <= T / 4) is selected. The phase comparator 521 compares the output of the inverter 510 with the data 110 and outputs a signal of the phase difference. After that, this signal is input to the band limiting sale and holding circuit 523 by the loop filter 522. When the holding signal 540 is HI, the holding circuit 523 supplies the output of the loop filter 522 to the VCO 524 as it is, and when the holding signal 540 is LO, the holding circuit 523 holds the output of the loop filter 522 at the time when the signal 540 is switched. This can prevent the internal frequency from flowing when the data 110 is not received.
Hold signal 540 is H when data 110 is being received.
I, if not received, set to LO (by the control circuit of the system after the bit synchronization circuit). VCO 524
Works so as to eliminate the phase difference between the data 110 and the output of the inverter 510 by the output of the holding circuit 523. Thus, a reference clock 120 synchronized with the data 110 is obtained. In this case, the above α is T / 4, and the data 110
Will be written to the elastic store 150 with a clock that is just a half phase shifted from the rising edge of the data.

FIG. 6 is a block diagram showing an example of a circuit for realizing the holding circuit 523.

The holding circuit 523 includes a switch 610 that uses a holding signal 540 as a control signal, and a capacitor 620 that holds a filter output voltage.

FIG. 7 is a diagram showing the relationship between clocks after synchronization. Basically, the phase 3 clock is selected, but if the jitter is large, the phase 2 clock may be selected. Therefore, as described above, the delay of the delay element 146 is set to T / 4 + jitter width (0 <jitter width <T / 4).

The second embodiment can be used when a transmission signal requires frequency synchronization with a reception signal.

[0025]

As described above, the bit synchronization circuit according to the present invention does not use a counter, but uses the rising edge of data to sequentially generate a clock for writing the data. Have.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a block diagram showing a conventional circuit.

FIGS. 3A and 3B are block diagrams illustrating a configuration example of a clock multiphase circuit.

FIG. 4 is a waveform chart showing a relationship between each clock and data.

FIG. 5 is a block diagram showing a second embodiment.

FIG. 6 is a block diagram illustrating a configuration example of a holding circuit.

FIG. 7 is a diagram showing a relationship between data and a selected phase.

[Explanation of symbols]

 100 bit synchronous circuit 110 data 120,270 reference clock 130,240 clock polyphase circuit 140 clock selection circuit 141,142,242 D flip-flop 143 NOR circuit 144 AND circuit 145 OR circuit 146,131,260 delay element 150 elastic Store 160 Output data 170 Multiphase clock 220 System clock 230 Divider 250 Conventional clock selector 251 Selector 252 Up / down counter 241 510 Inverter 521 Phase comparator 522 Loop filter 523 Holding circuit 524 Voltage controlled oscillator 530 Clock selection circuit output 540 Hold signal 610 Switch 620 Capacitor

Claims (2)

(57) [Claims] 1. A clock multi-phase circuit that receives a reference clock and outputs N clock signals having different phases, and a clock selection circuit that receives the N clock signals and received data. A burst signal bit synchronization circuit having a circuit and an elastic store (memory) for writing received data using an output of the clock selection circuit as a write clock and outputting data using a reference clock as a read clock, wherein the clock selection circuit comprises: The i-th (i is an integer from N) clock signal of the plurality of clock signals is used as a clock input, and the i-th NOR signal
An i-th DFF circuit in which the output of the circuit is used as a reset input and the data input is fixed to a predetermined value;
+1 DFF circuit, the delay element having an input of the output of the (N + 1) th DFF circuit as an input, and the i-th DF among the first to N + 1 DFF circuits
An i-th NOR circuit to which a non-inverting output of a DFF circuit other than the F circuit is input, an i-th clock signal of the plurality of clocks and the i-th clock signal
An i-th AND circuit that receives the non-inverting output of the DFF circuit as an input, and an OR circuit that receives the outputs of the first to N-th N AND circuits and outputs the input to the elastic store. Bit synchronization circuit. 2. The method according to claim 1, wherein the reference clock is generated by a phase locked oscillator including a phase comparator, a loop filter, and a voltage controlled oscillator, and the input data and the write clock are used as input signals of the phase comparator. The bit synchronization circuit according to claim 1, wherein: