JPH07154637A - Horizontal synchronizing signal coupling device - Google Patents

Abstract

PURPOSE:To provide a horizontal synchronizing signal coupling device from which a picture signal not causing jitter is obtained even in the case of obtaining a synthesized picture. CONSTITUTION:A 2nd reference periodic signal relating to a 2nd pixel rate of a 2nd picture signal which is obtained by multiplying at a multiple of M with a 1st horizontal synchronizing signal resulting from obtained by applying 1/N frequency division to a 1st reference periodic signal relating to a 1st pixel rate of a 1st picture signal is frequency-divided into 1/M by counters 4,5 to be reset by a 1st reset signal generated in themselves at the arrival of count M through self-running, a circuit 3 generates a reset signal used to reset the counter 4 at a time position at the head of the 1st horizontal synchronizing signal to reset the counter 4 and a D flip-flop 7 is provided, which invalidates a succeeding reset signal when the reset signal is generated from the reset signal generating circuit and given to the counter 4 at the succeeding clock time position after the counter 4 reaches the count M by self-running and the counter is reset automatically.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a horizontal sync combiner, and more particularly to a horizontal sync combiner for two image signals having different pixel rates.

[0002]

2. Description of the Related Art Creating a composite image by synthesizing image signals sent from different signal sources has been used in the technical field of television (hereinafter, television is abbreviated as TV) for video special effects. It is well known that it has been widely put into practical use as a device (electronic montage device). By the way, as an apparatus for handling images, in addition to the above-described television apparatus and VTR, recently, an apparatus that uses a computer to perform image information processing and displays an image on a display has been put into practical use. The image information processed by the computer and the television image information are displayed as a good reproduced image on the display as an image signal according to a predetermined scanning standard, or an image signal output from the computer on the display. Then, for example, it has become possible to obtain a composite image with an image signal obtained by decoding a compressed image signal which is highly efficiently compressed by the MPEG method.

By the way, the pixel rate (at the time of 2: 1 interlace scanning) applied when digitizing a typical television system image signal (for example, NTSC system image signal) is 13.5 MHz. On the other hand, the pixel rate (during sequential scanning) in the VGA standard applied to the image display of a computer is 25.175 MHz, which are different from each other. And the above-mentioned NTSC
The horizontal scanning frequency fh and the vertical scanning frequency fv in the scanning standard of the system are fh = 13.5 MHz / 858 = 15.
734 KHz, fv = 15.734 KHz / 262.5 =
It is 59.94 Hz, and the horizontal scanning frequency fh and the vertical scanning frequency fv in the scanning standard of the image signal for computer image display are fh = 25.175.
MHz / 800 = 31.468 KHz, fv = 31.46
It is 8 KHz / 525 = 59.94 Hz.

Here, the scanning standard in the above-mentioned typical television video signal (for example, NTSC video signal) and V applied to the image display of a computer.
Comparing with the scanning standard of the GA standard, the frequency value of the vertical scanning frequency fv in both the above formulas is the same, and regarding the horizontal scanning frequency fh, the frequency value in one system is the frequency value in the other system. Although it is twice as large as the above, it can be said that the same frequency value is obtained if both of the above systems are unified to the interlaced scanning system of 2: 1 or both to the progressive scanning system.

Now, an image based on an image signal output from a computer and an image based on a video signal of a television system (for example, an image signal obtained by decoding a compressed image signal highly efficient compressed by the MPEG system may be used) When it is desired to display the composite image on the display, it is necessary to perform synchronous coupling between the two image signals that form the composite image. To match the phases of two image signals for obtaining a composite image, for example, one image signal for forming a composite image is stored in an image memory having a large storage capacity (a memory having at least three frame memories). A means of storing and reading one image signal from the image memory so as to be in a state of being in phase with the other image signal is also conceivable, but such a method requires an expensive memory. There is a problem.

Therefore, without using a large capacity memory, 2
As an apparatus for performing synchronous coupling between two image signals, for example, as shown in the schematic configuration in FIG. 3 (only the component for performing phase synchronization with the horizontal synchronizing signal is shown), a horizontal synchronizing signal (vertical synchronizing signal for one image signal is used. Signal)
A synchronous coupling device has been considered in which the other horizontal synchronizing signal (vertical synchronizing signal) is reset to forcibly perform the phase synchronization of the synchronizing signals of the two image signals. Figure 3
1 denotes an input terminal of a horizontal synchronizing signal HH (see HH in FIG. 4) output from a VGA controller (not shown), and 25.17 supplied to the input terminal 1 described above.
The horizontal synchronizing signal HH having a repetition frequency of 5 MHz / 800 = 31.468 KHz is supplied to the rising edge detection circuit 3 and the phase locked loop 6.

The phase locked loop 6 includes a phase comparison circuit 61, a low pass filter (LPF) 62, and 1
The voltage controlled oscillator (VCO) 63 having a center oscillation frequency value of 3.5 MHz and a frequency divider 64 having a frequency division ratio of 858 constitute a well-known loop automatic phase control system, and the above-described loop automatic phase control system is used. A clock signal output from the voltage controlled oscillator 63 provided in the phase control system (clock signal having a center frequency of 13.5 MHz (CL in FIG. 4
K)) is supplied to the clock terminal of the D-type flip-flop 31 in the rise detection circuit 3, the clock terminal of the D-type flip-flop 32, and the clock terminal of the pixel counter 4. The horizontal synchronizing signal HH having a repetition frequency of 31.468 KHz is supplied to the data terminal of the D-type flip-flop 31 in the rise detection circuit 3 described above from the input terminal 1 described above.

The output signal from the Q output terminal of the D-type flip-flop 31 is supplied to the data terminal of the D-type flip-flop 32 and the AND circuit 33, and
The output signal from the Q-bar output terminal of the D-type flip-flop 32 is supplied to the AND circuit 33. Therefore, the AND circuit 33 in the rise detection circuit 3 rises at the rise time of the horizontal synchronizing signal HH supplied to the input terminal 1 and reset signal LCRST having a pulse width corresponding to one cycle of the clock signal. (See LCRST in FIG. 4) is output and supplied to the reset terminal LCRST of the pixel counter 4. The pixel counter 4 counts the clock signal {clock signal having a center frequency of 13.5 MHz (see CLK in FIG. 4)} output from the voltage controlled oscillator 63 in the phase locked loop 6 described above. As a result, the counting operation is performed and the count value is supplied from the output terminal LOUT to the input terminal LIN of the pixel comparison circuit 5.

In the above-mentioned pixel comparison circuit 5, the numerical value supplied to the input terminal LIN of the pixel comparison circuit 5 is used.
In the pixel comparison circuit, the output of the logic 1 is output to the output terminal 2 as the horizontal synchronization signal (HSync) and the value supplied to the input terminal LIN thereof is set to the pixel comparison circuit. In case of a numerical value preset in 5 (for example, 857), the reset signal HC of logical 1
ARRY (see HC ARRY in Fig. 4) is output terminal HC
From ARRY to reset terminal HCA of pixel counter 4
Give to RRY. So, the pixel counter 4 mentioned above
The pixel counter 4 in the circuit arrangement including the pixel comparison circuit 5 and the pixel comparison circuit 5 has the reset signal LCRS.
The output LOUT in the next one clock period after the one clock period in which T is in the logic 1 state is set to a count value of 0, and the above-mentioned reset signal LCRST is in the state of logic 0, and one clock in the state of the reset signal HCARRY of logic 1 Next 1 of period
The output LOUT in the clock period is set to 0, the reset signal LCRST is in the state of logic 0, and the reset signal HCARRY is in the state of logic 0 as the output LOUT in the period of one clock period subsequent to the one clock period. It operates so as to output “count value of LOUT + 1 count value in one clock period” (LCRS in FIG.
See T, LOUT, HCARRY).

Therefore, in the horizontal sync coupling apparatus shown in FIG. 3, the pixel counter 4 has 0 to 857 when the horizontal sync signal HH is not supplied to the input terminal 1 at all.
The counting operation up to is repeated, and the counting value of the pixel counter is reset to 0 by the rise of the horizontal synchronizing signal HH supplied to the input terminal 1. The above points will be specifically described with reference to FIG. In the example illustrated in FIG. 4, in the reference numerals 1 to 22 at the top of FIG. 4 which are described for convenience to indicate the position on the time axis, the horizontal synchronization signal HH supplied to the input terminal 1 is The change from the low level state to the high level in the middle of one clock period indicated by reference numeral 2 causes the reset signal LCRST to be in the high level state during the one clock period indicated by reference numeral 3. In this case, Since the reset signal LCRST is in the state of logic 1, the output LO of the pixel counter 4 in the one clock period indicated by the reference numeral 4 next to the one clock period indicated by the reference numeral 3 is satisfied.
The UT has a count value of zero.

The 1-clock period indicated by reference numerals 5 to 11 and 14 to 18 corresponds to the above-mentioned case, and therefore, the 1-clock period (next to the 1-clock period described above). (Reference numerals 6 to 12, 15 to 19)
The output LOUT of the pixel counter 4 in 1 outputs the “count value of LOUT in the immediately preceding one clock period + the count value of 1”, and further, for each one clock period indicated by the reference numeral 12 and the reference numeral 19, it is described above. Since it corresponds to the case of, the reset signal H of logic 1 is
1 clock period after 1 clock period in the CARRY state (1 clock period of reference numeral 13 and reference numeral 20)
The pixel counter 4 output LOUT in FIG.

[0012]

In the example shown in FIG. 4, one clock period (one clock period indicated by reference numeral 20) next to the clock period indicated by reference numeral 19 corresponding to the above-mentioned case is provided. The output LOUT of the pixel counter 4 in the period) becomes a count value of 0, but as described above, the count value of the output LOUT of the pixel counter 4 is set to 0 in the one clock period shown by the reference numeral 20 in FIG.
When the reset signal LCRST becomes the logic 1 state as shown therein, the one clock period indicated by the reference numeral 20 corresponds to the case described above, and thus the reset signal LCRST becomes the logic 1 state as described above. 1 clock period next to the 1 clock period shown by reference numeral 20 (1 clock period shown by reference numeral 21)
The output LOUT of the pixel counter 4 also has a count value of 0, and the count value of the output LOUT of the pixel counter 4 may have a value of 0 in two consecutive clock periods.

The disadvantages as described above are that the operating state of the phase-locked loop 6 slightly changes due to the fluctuation of the power supply voltage and the temperature change, whereby the rising time position of the input horizontal synchronizing signal HH and the clock. This is caused by the fact that the time position of the rising edge of the signal becomes almost the same. Then, as described above, the output LOUT of the pixel counter 4
If the count value of 0 becomes 0 in two consecutive clock periods, the horizontal synchronization signal originally output to the output terminal 2 should be always 858 clock cycles, but it is output to the output terminal 2. The cycle of the horizontal synchronizing signal is 857 clock cycles → 859 clock cycles → 858
The horizontal synchronizing signal cycle changes in the order of clock cycle → 857 clock cycle →, which causes jitter in the image. Therefore, the advent of a horizontal synchronous coupling device which does not cause the above-mentioned problems has been demanded.

[0014]

SUMMARY OF THE INVENTION The present invention is a horizontal synchronous combining apparatus for two image signals having different pixel rates, the first criterion being associated with the first pixel rate of the first image signal. Means for obtaining the first horizontal synchronizing signal by dividing the periodic signal of 1 to a predetermined 1 / N, and the second pixel of the second image signal by multiplying the first horizontal synchronizing signal by M. Means for obtaining a second reference periodic signal associated with the rate;
A counter for resetting the second reference periodic signal, which is related to the second pixel rate, by dividing it into 1 / M and reaching the count value of M by free running, and a first horizontal synchronizing signal. And a reset signal appearing at the time position of the next clock after the counter reaches the count value of M by free running and resets the counter. And a means for nullifying the horizontal synchronization coupling device.

[0015]

The first reference periodic signal 12.5875 MHz, which is related to the first pixel rate 25.175 MHz of the first image signal output from the VGA, is divided by 1/800 to obtain the first horizontal signal. The sync signal is obtained and multiplied by 858 times to obtain the second pixel rate of the second image signal of 13.5M.
Obtain a second reference periodic signal associated with Hz. A counter resets the second reference periodic signal associated with the second pixel rate with a first reset signal generated in the counter while reaching a count value of 858 by free running. Divide into. At the leading time position of the first horizontal synchronizing signal, the counter is reset by a reset signal generated by a reset signal generating circuit that resets the counter. A reset signal is generated from the reset signal generating circuit and applied to the counter at the time position of the next clock after the counter has reached the count value of 858 by self-running and the counter is automatically reset. In that case, the reset signal is invalidated so that the counter is not reset.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The concrete contents of the horizontal synchronous coupling device of the present invention will be described in detail below with reference to the accompanying drawings. FIG. 1 is a block diagram showing a configuration example of a horizontal synchronization coupling device of the present invention, FIG.
1 is an explanatory diagram of signals for explaining the operation of the horizontal synchronization coupling device shown in FIG. 1, FIG. 3 is a block diagram showing a configuration example of the horizontal synchronization coupling device for explaining conventional problems, and FIG. 4 is FIG. It is an explanatory view of a signal for operation explanation of a horizontal synchronous coupling device shown. In the horizontal synchronous coupling device of the present invention shown in FIG.
Is an input terminal of a horizontal synchronizing signal HH (see HH in FIG. 2) output from a VGA controller (not shown),
25.175 MHz / supplied to the input terminal 1
The horizontal synchronizing signal HH having a repetition frequency of 800 = 31.468 KHz is supplied to the rising edge detection circuit 3 and the phase locked loop 6. Phase Locked
The loop 6 includes a phase comparison circuit 61 and a low pass filter (L
PF) 62, a voltage controlled oscillator (VCO) 63 having a center oscillation frequency value of 13.5 MHz, and a frequency division ratio of 858.
The clock signal (center frequency is 13) is output from the voltage controlled oscillator 63 provided in the above-described one-cycle automatic phase control system. A clock signal of 0.5 MHz (see CLK in FIG. 2)} is supplied to the clock terminal of the D-type flip-flop 31 in the rise detection circuit 3 and D
Type flip-flop 32 clock terminal, pixel counter 4 clock terminal, and D-type flip-flop 7
Is being supplied to the clock terminal of. The horizontal synchronizing signal HH having a repetition frequency of 31.468 KHz is supplied to the data terminal of the D-type flip-flop 31 in the rise detection circuit 3 described above from the input terminal 1 described above.

The output signal from the Q output terminal of the D-type flip-flop 31 is supplied to the data terminal of the D-type flip-flop 32 and the AND circuit 33, and
The output signal from the Q-bar output terminal of the D-type flip-flop 32 is supplied to the AND circuit 33. Therefore, the AND circuit 33 in the rise detection circuit 3 rises at the rise time of the horizontal synchronizing signal HH supplied to the input terminal 1 and reset signal LCRST having a pulse width corresponding to one cycle of the clock signal. (See LCRST in FIG. 2) is output and supplied to the reset terminal LCRST of the pixel counter 4. The pixel counter 4 counts the clock signal {clock signal having a center frequency of 13.5 MHz (see CLK in FIG. 2)} output from the voltage controlled oscillator 63 in the phase locked loop 6 described above. As a result, the counting operation is performed and the count value is supplied from the output terminal LOUT to the input terminal LIN of the pixel comparison circuit 5.

In the pixel comparison circuit 5, the numerical value supplied to the input terminal LIN of the pixel comparison circuit 5 is used.
In the pixel comparison circuit, the output of the logic 1 is output to the output terminal 2 as the horizontal synchronization signal (HSync) and the value supplied to the input terminal LIN thereof is set to the pixel comparison circuit. In case of a numerical value preset in 5 (for example, 857), the reset signal HC of logical 1
ARRY (see HC ARRY in FIG. 2) is output terminal HC
From ARRY to reset terminal HCA of pixel counter 4
It is supplied to RRY and also to the data terminal of the D-type flip-flop 7. In the D-type flip-flop 7, the reset signal LHCARRY in a state in which the reset signal HCARRY supplied to its data terminal is delayed by one clock cycle is output from the Q output terminal, and the reset signal LHCARRY is Counter 4 reset terminal LHCARRY (LHCAR in FIG. 2
RY)).

Therefore, in the pixel counter 4 in the circuit arrangement including the pixel counter 4 and the pixel comparison circuit 5 described above, the reset signal LCRST is logic 1 and the reset signal LHCARRY is logic 0. In the state, the output LOUT in the next one clock period of the next one clock period is set to the count value 0, and when the reset signal LCRST is in the state of logic 1 and the reset signal LHCARRY is in the state of logic 1 , "The count value of the count value of LOUT in the immediately preceding one clock period + the count value of +1" is output as the output LOUT in the next one clock period, and the reset signal LCRST is in the state of logic 0, and the reset signal HCARRY is in the state of logic. Output LOUT for one clock period following the one clock period in the 1 state
Is set as a count value 0, the reset signal LCRST is in the state of logic 0, and the reset signal HCARRY is in the state of logic 0 as the output LOUT in the next 1 clock period of the 1 clock period.
UT count value + 1 count value ”(LCRST, LOUT, HCARRY,
See LHCARRY).

Therefore, in the horizontal sync coupling apparatus shown in FIG. 3, the pixel counter 4 has 0 to 857 when the horizontal sync signal HH is not supplied to the input terminal 1 at all.
The counting operation up to is repeated, and the counting value of the pixel counter is reset to 0 by the rise of the horizontal synchronizing signal HH supplied to the input terminal 1. The above point will be described in detail with reference to FIG. In the example illustrated in FIG. 2, in the reference numerals 1 to 22 at the top of FIG. 2 which are described for convenience to indicate the position on the time axis, the horizontal synchronization signal HH supplied to the input terminal 1 is The change from the low level state to the high level in the middle of one clock period indicated by reference numeral 2 causes the reset signal LCRST to be in the high level state during the one clock period indicated by reference numeral 3. In this case, Since the reset signal LCRST is in the state of logic 1, the output LO of the pixel counter 4 in the one clock period indicated by the reference numeral 4 next to the one clock period indicated by the reference numeral 3 is satisfied.
The UT has a count value of zero.

The 1-clock period indicated by reference numerals 5 to 11 and 14 to 18 corresponds to the above-mentioned case, and therefore, the 1-clock period (next to the 1-clock period). (Reference numerals 6 to 12, 15 to 19)
The output LOUT of the pixel counter 4 in 1 outputs the “count value of LOUT in the immediately preceding one clock period + the count value of 1”, and further, for each one clock period indicated by the reference numeral 12 and the reference numeral 19, it is described above. Since it corresponds to the case of, the reset signal HCARR
One clock period after one clock period in which Y is a logic 1 state (one clock period of reference numeral 13 and reference numeral 20)
The pixel counter 4 output LOUT in FIG. Furthermore, the 1 clock period indicated by reference numeral 20 corresponds to the above-mentioned case, and therefore the output of the pixel counter 4 in the 1 clock period (reference numeral 21) following the 1 clock period. L
OUT outputs “count value of LOUT count value + 1 count value in immediately preceding one clock period”.

As described above, in the horizontal synchronous coupling device of the present invention, the reference numeral 19 in the example shown in FIG. 2 is used.
1 clock period after the clock period indicated by (reference numeral 2
Pixel counter 4 in 1 clock period indicated by 0)
Even if the reset signal LCRST is in the state of logic 1 as shown in FIG. 2 in the state in which the output LOUT of the output LOUT is set to 0, the one clock period indicated by the reference numeral 20 corresponds to the case described above. Therefore, the reset signal LCRST is in the state of logic 1 as described above, which is one clock period after the one clock period shown by reference numeral 20 (one clock period shown by reference numeral 21). Output LOUT has a count value of 1, and the count value of the output LOUT of the pixel counter 4 does not become 0 in two consecutive clock periods.

[0023]

As will be apparent from the above detailed description, the horizontal sync combination apparatus of the present invention outputs the first reference periodic signal associated with the first pixel rate of the first image signal to 1 / N to obtain the first horizontal synchronizing signal and multiply it by M to obtain the second reference periodic signal associated with the second pixel rate of the second image signal. 1 / M by the counter which is reset by the first reset signal generated in the counter when the count value M is reached by running
And reset the counter with a reset signal generated by a reset signal generating circuit that resets the counter at the time position of the head of the first horizontal synchronizing signal described above. When the reset signal is generated from the reset signal generating circuit and is given to the counter at the time position of the next clock after the counter has automatically reset by the counter after reaching the count value M by free running. Since the reset signal is invalidated so that the counter is not reset, according to the horizontal synchronization coupling device of the present invention, two image signals having different pixel rates are generated by the conventional horizontal synchronization coupling device described above. It is possible to eliminate the jitter of the image, which is a problem when the images are combined.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration example of a horizontal synchronization coupling device of the present invention.

FIG. 2 is an explanatory diagram of signals for explaining the operation of the horizontal synchronous coupling device shown in FIG.

FIG. 3 is a block diagram showing a configuration example of a horizontal synchronization coupling device for explaining a conventional problem.

FIG. 4 is an explanatory diagram of signals for explaining the operation of the horizontal synchronous coupling device shown in FIG.

[Explanation of symbols]

1 ... Input terminal, 2 ... Output terminal, 3 ... Rise detection circuit,
4 ... Pixel counter, 5 ... Pixel comparison circuit, 6 ... Phase locked loop, 7, 31, 32 ... D flip-flop, 61 ... Phase comparison circuit, 62 ... Low pass filter, 63 ... Voltage controlled oscillator, 64 ... Divider,

Claims (1)

[Claims] 1. A horizontal synchronous combiner for two image signals having different pixel rates, wherein a first reference periodic signal associated with a first pixel rate of the first image signal is predetermined. Means for obtaining a first horizontal synchronizing signal by dividing by 1 / N, and a second reference relating to the second pixel rate of the second image signal by multiplying the first horizontal synchronizing signal by M And a second reference periodic signal associated with the second pixel rate is divided by 1 / M, and reset by a state where the count value of M is reached by free running. A counter, a reset signal generating means for resetting the counter at a time position at the head of the first horizontal synchronizing signal, and a counter after resetting the counter after the counter reaches the count value of M by free running. Reset signal appearing at time position of clock And a means for disabling the horizontal synchronizing device.