JPH07105931B2 - Video signal processing circuit - Google Patents

Description

The present invention relates to a video signal reproducing circuit of a video tape recorder (hereinafter referred to as VTR), and more particularly to a clamp circuit for clamping a sync signal tip level of a reproduced video signal to a predetermined level. Regarding

[Conventional technology]

The video signal reproducing circuit of the VTR is provided with a clamp circuit that clamps the leading end level of the sync signal included in the reproduced video signal to a predetermined level (hereinafter, referred to as a clamp level). The VTR has special playback modes such as still, slow, and quick in addition to the normal playback mode. The vertical sync signal included in the playback video signal in the special playback mode cannot be used for vertical synchronization of the television receiver. Therefore, in the special reproduction mode, a pseudo vertical synchronization signal is separately prepared and the same signal is inserted into the special reproduction mode signal. The tip level of the inserted pseudo vertical synchronizing signal also needs to be aligned with the clamp level. For this purpose, the insertion of the pseudo vertical synchronizing signal is performed in the preceding stage of the clamp circuit.

Normally, an equivalent pulse of 1/2 horizontal period (1 / 2H) is inserted in the vertical blanking period of the television signal, but the horizontal AFC used in recent high image quality and high resolution television receivers. The circuit controls the horizontal sync oscillator in response to the equivalent pulse to prevent horizontal sync disturbance even in the vertical blanking period. Therefore, the above-described horizontal AFC circuit can be dealt with by adding a pulse having a period substantially proportional to the horizontal period to the pseudo vertical synchronizing signal, for example, a 1/2 horizontal period.

[Problems to be Solved by the Invention]

However, in the conventional technique, since the pseudo vertical sync signal is simply inserted into the special reproduction video signal in the preceding stage of the clamp circuit, the entire pseudo vertical sync signal is clamped at the clamp level, and the 1/2 horizontal The periodic pulse had disappeared. As a result, the horizontal AFC function does not work and the horizontal synchronization is disturbed.

An object of the present invention is to provide a video signal processing circuit capable of inserting a pseudo vertical synchronizing signal into a reproduced video signal and outputting the same without extinguishing a 1/2 horizontal cycle pulse.

[Means for Solving the Problems]

The video signal processing circuit according to the present invention includes a first input terminal to which a reproduced video signal is supplied, a second input terminal to which a pseudo vertical synchronizing signal having a pulse having a predetermined cycle is supplied, and the second input terminal. Means for generating a detection signal by detecting the pseudo vertical synchronization signal, and means for separating the pulse from the pseudo vertical synchronization signal and outputting the detection signal, the detection signal being connected to the second input terminal. Switch means coupled to the first input terminal for outputting a reproduced video signal when not generated, and for outputting the separated pulse when the detection signal is generated, and coupled to the switch means. , The output signal of the switch means is set to a predetermined level during the sync signal period included in the reproduced video signal and the pseudo vertical sync signal supply period, in which the pulse does not exist. And a clamping means for clamping the.

As described above, in the present invention, the pulse included in the pseudo vertical synchronizing signal is separated from the pseudo vertical synchronizing signal, and the clamp means is in the inoperative state during the period of this pulse. Therefore, it is possible to obtain the reproduced video signal in which the pseudo vertical synchronizing signal is inserted and the pulse having the period related to one horizontal period is present during the signal period from the clamp means. Moreover, the tip level of each sync signal is clamped to a predetermined level.

[Examples] Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing a VTR reproducing system having a video signal processing circuit according to an embodiment of the present invention. The pseudo vertical synchronizing signal PV _S generated in the special reproduction mode is supplied to the terminal 22 and commonly applied to the non-inverting input terminals (+) of the comparators 13 and 14. A voltage source is connected to the inverting input terminal of the comparator 13.
The reference voltage V _A is applied from 500, and the reference voltage V _B is applied from the voltage source 510 to the non-inverting input terminal of the comparator 14.
The output of the comparator 14 is supplied to the terminal B of the switch circuit 8 via the waveform shaping circuit 17. A reproduced video signal is supplied to the terminal A of the switch circuit 8. The comparator 13 controls switching of the switch circuit 8. The output of the switch circuit 8 is a level shift circuit 9, an amplifier 10, a comparator 11, a smoothing circuit 12 and a voltage source.
It is supplied to the clamp circuit composed of 520. Comparator 11
Its operation is controlled by a signal from the control circuit 16. The control circuit 16 includes a comparator 14 output and a sync signal separation circuit.
Horizontal and vertical sync signals from 15 are provided. That is, when the output of the comparator 14 is high level, the control circuit 16
Alternatively, when the sync signal is output from the sync signal separation circuit 15, the comparator 11 is operated.

The signal recorded on the video tape 1 is read by the video head 2 and supplied to the reproduction / amplification circuit 4. Same circuit 4
Amplifies the input signal, separates the FM-modulated luminance signal and the frequency-converted chroma (color) signal, and outputs them. The FM-modulated luminance signal is demodulated by the luminance signal processing circuit 5, and the chrominance signal processing circuit 6 generates a chroma signal of the original frequency. The mixing circuit combines the respective outputs of the luminance signal processing circuit 5 and the chrominance signal processing circuit 6 and supplies them to the terminal A of the switch circuit 8 as a reproduced video signal.

The output of the amplifier 10 is supplied to the RF converter 19 and converted into a television signal. The switch 20 switches the input signal of the television receiver 21 at the time of playing a video and receiving a normal television broadcast.

In the normal reproduction mode, the pseudo vertical synchronizing signal PV _S is not generated, that is, it is at the low (GND) level, so the output of the comparator 13 is at the low level. Therefore, the switch circuit 8 is switched to the terminal A side, and the reproduced video signal from the mixing circuit 7 is supplied to the level shift circuit 9 and transmitted to the amplifier 10. When the sync signal separation circuit 15 outputs the vertical and horizontal sync separation signals, the control circuit 16 causes the comparator 11
To operate. The comparator 11 compares the front end level of the sync signal in the reproduced video signal with the reference voltage V _C from the voltage source 520, and outputs a control signal so that they are equal.
This control signal is converted into a DC voltage by the smoothing circuit 12 and is negatively fed back to the level shift circuit 9 to control the level shift amount. As a result, the tip level of each sync signal in the reproduced video signal is clamped to the reference voltage V _C.

In the special reproduction mode such as still, slow, and quick, the pseudo vertical synchronizing signal PV _S is supplied to the terminal 22. This signal PV _S
As shown in FIG. 2 (a), V
_{It has an S-} level voltage amplitude and is 0V in other periods. Further, for the horizontal AFC in the television receiver 21, the pulse 600 is inserted with a period related to one horizontal period. In this embodiment, the pulse 600 is inserted with a horizontal period of 1/2 (1 / 2H), but it may be 1H or 2H. It depends on the characteristics of the horizontal AFC in the television receiver 21. The leading level of each pulse 600 has a V _G level between the V _S level and 0V. The comparator 13 detects the pseudo vertical synchronizing signal PV _S , and the comparator 14 detects each pulse 600. For this purpose, as shown in FIG. 2 (a), the reference voltage V _A from the voltage source 50 is set between the V _G level and 0 V, and the reference voltage V _B from the voltage source 51 is It is set between the V _S level and the V _G level. That is, there is a relationship of V _A <V _G <V _B <V _S. Therefore, the pseudo vertical sync signal PV _S
When supplied to 2, the comparator 13 produces a high level output (Fig. 2 (b)), and the comparator 14 produces a high level output during the pseudo vertical synchronization period and when the pulse 600 is not present ( FIG. 2 (c)). The waveform shaping circuit 17 receives the output from the comparator 14 and generates an amplitude-controlled pulse 600 'in response to the low level of the output in the pseudo vertical synchronization period (second).
Figure (d)). Thus, the pulse 600 inserted in the pseudo vertical synchronizing signal PV _S is separated. The separated pulse is supplied to the terminal B of the switch circuit 8. Since the control circuit 16 operates the comparator 11 when the output of the comparator 14 is at a high level, the clamp operation is in the pseudo vertical synchronization period and when the pulse 600 is not present, the synchronization signal separation circuit 15 outputs the synchronization separation signal. It is done when it occurs.

Now, in the special reproduction mode, when the pseudo vertical synchronizing signal PV _S is not supplied to the terminal 22, the output of the comparator 13 is at the low level, so the switch circuit 8 is switched to the terminal A side. Therefore, the special reproduction video signal output from the mixing circuit 7 is supplied to the level shift circuit 9 and transmitted to the amplifier 10. When the sync signal separation circuit 15 outputs the sync separation signal in response to the vertical and horizontal sync signals in the reproduction luminance signal, the control circuit 16 operates the comparator 11. As a result, the tip level of the sync signal in the trick play video signal is clamped to the reference voltage V _C.

When the pseudo vertical synchronization signal PV _S (FIG. 2 (a)) is supplied to the terminal 22, the comparator 13 generates a high level signal during the pseudo vertical synchronization period (FIG. 2 (b)). The switch circuit 8 switches to the terminal B side. The terminal 600 is supplied with a 1 / 2H pulse 600 ′ (FIG. 2 (d)) from the waveform shaping circuit 17. While this pulse 600 'is generated, the comparator 11 is inactive, and between the adjacent pulses 600', the comparator 1
When 1 is set, the clamp operation is performed. As a result, as shown in FIG. 2 (e), a 1 / 2H pulse 600 'is inserted in the pseudo vertical synchronizing signal portion in the reproduced video signal, and the voltage of the portion other than the pulse 600' is the reference. It is clamped to the voltage V _C. Therefore, the horizontal AFC circuit of the television receiver 21 executes the horizontal AFC operation even during the pseudo vertical synchronization period.

The VTR is required to have a monitor function for recording the television signal on a tape and displaying the image being recorded on the screen of the television receiver. To this end, a second switch circuit 24 is provided, as shown in FIG.
Is provided between the switch circuit 8 and the level shift circuit 9. The output of the switch circuit 8 is supplied to the terminal D of the switch circuit 24, and the video signal being recorded is supplied to the terminal C via the amplifier circuit 25. The switching operation of the switch circuit 24 is controlled by the control circuit 26.

In the reproduction mode, the switch circuit 24 is switched to the terminal D side. During the monitor function, a monitor control signal is supplied to the control circuit 26, and the switch 24 is switched to the terminal C side. Therefore, the video signal being recorded is supplied to the level shift circuit 9. Further, although not shown, the sync signal separation circuit 15 is supplied with a luminance signal based on the video signal being recorded. Therefore, the leading edge level of the synchronizing signal of the recorded video signal is clamped to the reference voltage V _C of the voltage source 520 and supplied to the RF converter 19.

FIG. 4 shows a specific transistor circuit of the main block shown in FIG. When the pseudo vertical synchronizing signal PV _S is not supplied in the normal reproduction mode or the special reproduction mode, the transistors 70 and 71 in the comparator 13 are turned on and the transistors 72-75 are turned off, so that the current in the switch circuit 8 is increased. The source circuits 40 and 41 are turned on, the reproduced video signal is amplified by the differential transistors 42 and 43, and is supplied to the switch circuit 24 via the emitter follower transistor 48. In the reproduction mode, the control circuit 29 turns on the transistor 53 and turns off the transistor 54.
It is amplified by 9,50 and supplied to the transistor 55 in the level shift circuit 9. On the other hand, during monitor operation,
Since the transistor 53 is off and 54 is on, the differential transistors 51 and 52 amplify the recording video signal and supply it to the transistor 55. The amount of level shift in the level shift 9 is controlled by the resistors 92 and 93 and the transistor 56 as a variable impedance element.

The level-shifted video signal is the transistor 57-6.
1, amplified by an amplifier 10 composed of resistors 94, 95, current sources 35, 36 and voltage source 111 and supplied to a comparator 11, and also supplied to an RF converter 19 via an emitter follower transistor 62. . In the comparator 11, the current source transistor
By turning on 82, the comparison operation is executed. A diode-connected transistor 81 is provided for the transistor 82, and a resistor 107 is connected to the moving transistor 81.
A parallel circuit of transistors 78 and 79 is connected via. When the transistor 71 in the comparator 13 is on, the transistors 76 and 77 are on, so the transistors 78 and 80 are off. Therefore, when the sync separation signal is output from the circuit 15, the transistors 79, 81,
82 is turned on and the comparator 11 operates. The signal from the amplifier 10 is compared with the reference voltage V _C from the voltage source 520 by the transistors 82-88, and the comparison output is smoothed and rectified by the capacitor 110 connected to the terminal 127. The DC voltage is negatively fed back to the base of the transistor 56 via the transistors 89-91. Thus, the sync signal tip level of the reproduced video signal or the recorded video signal is clamped to the reference voltage V _C.

When the pseudo vertical synchronizing signal PV _S is applied to the terminal 22 in the special reproduction mode, the base voltage of the transistor 70 becomes the base voltage of the transistor 73, that is, the reference voltage V from the voltage sources 500 and 510 composed of the resistors 98-101. Higher than _A. Therefore, the transistors 70, 71, 40-43 are turned off, and the reproduced video signal is separated. On the other hand, the transistor
Since 72 and 73 are turned on, the current source transistors 46 and 47 operate and the differential transistors 44 and 45 are activated. Further, since the transistors 74 and 75 are turned on, the transistors 76 and 77 of the control circuit 16 are turned off. The transistor 80 is turned on and the transistor 79 is turned off. In the comparator 14, when the pseudo vertical synchronizing signal PV _S is applied, the base voltage of the transistor 63 (64) becomes higher than the base voltage V _B of the transistor 66 (65), so the transistors 63 and 64 are turned off. , 66 is turned on. Further, since the transistors 67 and 68 are turned off, a high level output is supplied from the transistor 65 to the transistor 78 and the transistors 78, 81 and 82 are turned on, and the comparator 11 operates. Since the transistor 64 is off, the connection point voltage of the resistors 98 and 99 is supplied to the base of the transistor 45 via the transistor 69. Pulse 60
When 0 (FIG. 2) is applied to terminal 22, transistor 63,
Since 64, 67 and 68 are turned on and transistors 65 and 66 are turned off, the transistors 78, 81 and 82 are turned off and the comparator 11 is deactivated. Since the transistor 64 is turned on, a pulse 600 '(FIG. 2) having an amplitude determined by the current of the current source 38, the resistance 96 and the emitter voltage of the transistor 69 is supplied to the transistor 45. Thus, the transistor 63
-68, resistors 96 and 97, current source 38 are comparator 14 and waveform shaping circuit 17
With both functions. Since the comparator 11 is inactive in the pulse 600 ′, the switch circuit 24, the level shift circuit 9,
It is supplied to the RF converter 19 via the amplifier 10. pulse
The level of the pseudo vertical sync period where 600 does not exist is clamped to the reference voltage V _C.

FIG. 5 shows another configuration example of the switch circuit 24. According to this configuration, by setting the values of the emitter resistances 121 and 122 of the differential transistors 114 and 115 and the emitter resistances 123 and 124 of the differential transistors 119 and 120 within the dynamic range of each of the reproduced video signal and the recorded video signal, they are independent of each other. The desired gain can be obtained. A common load is provided for the differential transistors (114, 115) and (119, 120). Turning on the transistors 117 and 118,
The off control is as described in FIG.

〔The invention's effect〕

As described above, according to the present invention, it is possible to provide a video processing circuit capable of inserting both the pseudo vertical synchronizing signal and the pulse added thereto into the special reproduction video signal.

[Brief description of drawings]

FIG. 1 is a partial block diagram of a VTR system having a video signal processing circuit according to an embodiment of the present invention, and FIGS. 2 (a) to 2 (e) are signal waveform diagrams for explaining the operation of FIG. 3 is a block diagram showing another embodiment of the present invention, FIG. 4 is a circuit diagram showing a concrete configuration of the main block shown in FIG. 3, and FIG. 5 is a switch circuit 24 shown in FIG. 6 is a circuit diagram showing another configuration of FIG.

Claims (1)

[Claims] 1. A first input terminal to which a reproduced video signal is supplied, and a pulse having a predetermined period within a pseudo vertical synchronization period which is the same as the vertical synchronization period used in the normal reproduction mode in the special reproduction mode. A second input terminal to which a pseudo vertical synchronization signal is supplied, means for generating a detection signal by detecting the pseudo vertical synchronization period, which is coupled to the second input terminal, and the second input terminal. Means coupled to an input terminal for separating the pulse from the pseudo vertical sync signal and outputting the pulse; and the first means when the detection signal is not generated.
Switch means for selecting the input terminal to output the reproduction video signal and outputting the separated pulse when the detection signal is generated, and the pulse is not present during the pseudo vertical synchronization period. A video signal processing circuit, comprising: clamp means for clamping the output signal of the switch means to a predetermined level during a period.