JP3587006B2

JP3587006B2 - Automatic gain control circuit

Info

Publication number: JP3587006B2
Application number: JP00431397A
Authority: JP
Inventors: 誠横村; 伸一内山
Original assignee: Panasonic Corp; Matsushita Electric Industrial Co Ltd
Current assignee: Panasonic Corp; Panasonic Holdings Corp
Priority date: 1997-01-14
Filing date: 1997-01-14
Publication date: 2004-11-10
Anticipated expiration: 2017-01-14
Also published as: JPH10200851A

Description

【０００１】
【発明の属する技術分野】
本発明は、映像信号を記録再生する映像記録再生装置（以下、ビデオテープレコーダと略す）における自動利得制御回路（以下、ＡＧＣ回路と略す）に関するものである。
【０００２】
【従来の技術】
以下、従来のビデオテープレコーダに使用されているＡＧＣ回路を図面を参照しながら説明する。
【０００３】
図３は従来のＡＧＣ回路の構成を示したブロック図である。図３において、１は入力端子、２は入力端子１から入力された映像信号が入力される振幅制御増幅回路、３は振幅制御増幅回路２の出力信号から色信号を除去するローパスフィルタ、４はクランプ回路、５はクランプ回路４の出力から複合同期分離信号を分離する同期信号分離回路であり、同期信号分離回路５の出力は第１の論理積回路９と、第１の矩形波発生回路１５と、第３の矩形波発生回路１２と、第１の反転回路１３とに入力される。１５は同期信号分離回路５の出力信号の立ち上がりから第１の所定幅の矩形波を発生する第１の矩形波発生回路、１６は第１の矩形波発生回路１５の出力信号を反転した信号を発生する第２の反転回路、９は同期信号分離回路５の出力信号と第２の反転回路１６の出力信号とを論理積演算する第１の論理積回路、１０は第１の論理積回路９の出力信号の立ち上がりから第４の所定幅の矩形波を発生する第４の矩形波発生回路、１２は同期信号分離回路５の出力信号の立ち上がりから第３の所定幅の矩形波を発生する第３の矩形波発生回路、１１は第４の矩形波発生回路１０の出力信号と第３の矩形波発生回路１２の出力信号とを論理積演算する第２の論理積回路、１３は同期信号分離回路５の出力信号を反転する第１の反転回路、１４は第２の論理積回路１１の出力信号と第１の反転回路１３の出力信号とを論理積演算する第３の論理積回路、６は第３の論理積回路１４の出力信号とクランプ回路４の出力信号とを加算する加算回路、７は加算回路６の出力信号の最大値を検波する最大値検波回路、８は比較回路であり、比較回路８の出力が振幅制御増幅回路２に帰還される。図１０は図３の同期信号分離回路における各部の信号波形図を示したものである。
【０００４】
以上のように構成された従来の自動利得制御回路において、以下同期信号分離回路以降の動作について説明する。
【０００５】
図１０（ａ）に示す同期信号分離回路５の出力信号は、第１の論理積回路９と第１の矩形波発生回路１５と、第３の矩形波発生回路１２と、第１の反転回路１３に入力される。第１の矩形波発生回路１５では、同期信号分離回路５の出力信号の立ち上がりから第１の所定の幅の矩形波（図１０（ｂ））が出力される。第１の矩形波発生回路１５の出力信号は第２の反転回路１６に入力され、第２の反転回路１６からは第１の矩形波発生回路１５を反転した信号（図１０（ｃ））が出力される。同期信号分離回路５の出力信号と第２の反転回路１６の出力信号は第１の論理積回路９に入力され、同期信号分離回路５の出力と第２の反転回路１６の出力の論理積の結果が出力される（図１０（ｄ））。第１の論理積回路９の出力信号は、第４の矩形波発生回路１０に入力される。第４の矩形波発生回路１０では、第１の論理積回路９の出力信号の立ち上がりから第４の所定の幅の矩形波（図１０（ｅ））が出力される。
【０００６】
一方、第３の矩形波発生回路１２では、同期信号分離回路５の出力信号の立ち上がりから第３の所定の幅の矩形波（図１０（ｆ））が出力される。第４の矩形波発生回路１０の出力信号と第３の矩形波発生回路１２の出力信号は、第２の論理積回路１１に入力され、第４の矩形波発生回路１０の出力と第３の矩形波発生回路１２の出力の論理積の結果が出力される（図１０（ｇ））。第２の論理積回路１１の出力信号と第１の反転回路１３の出力信号（図１０（ｈ））は第３の論理積回路１４に入力され、第２の論理積回路１１の出力と第１の反転回路の出力の論理積の結果が出力される（図１０（ｉ））。
【０００７】
この構成により、第３の論理積回路１４の出力は、第１の所定の幅の矩形波の幅よりも広く、第４の所定の幅の矩形波よりも幅の狭い同期信号分離回路５の出力に対してのみ、矩形波が出力される（以下、第３の論理積回路１４の出力をキーパルスとする）。
【０００８】
次に、従来のＡＧＣ回路に垂直帰線期間に所定の信号が付加されている映像信号を入力したときの動作について図８、図９を用いて説明する。
【０００９】
図９は映像信号の垂直帰線期間の一部を示した波形図である。図９（ａ）の映像信号は垂直帰線期間に所定の信号が付加されていない映像信号であり、図９（ｂ）の映像信号は垂直帰線期間に所定の信号が付加されている映像信号を示したものである。
【００１０】
図８（ａ）は図９のＡ、Ｂの部分を拡大したものである。垂直帰線期間に所定の信号が付加されている映像信号の場合、Ｂの部分には擬似同期信号と白１００％の信号が交互に挿入されている。この信号に対して従来のＡＧＣ回路は白１００％の信号部分にキーパルスを加算し、この最大値を所定の値にするように利得を制御するため、振幅が垂直帰線期間に所定の信号が付加されていない映像信号を入力した時よりも小さくなる。これを利用して映像信号の複製を制限している。
【００１１】
【発明が解決しようとする課題】
しかしながら上記従来の構成では、ケーブルテレビの放送などで意図せず複製を制限するための信号が付加されている放送信号があり、このような放送信号をビデオテープレコーダを経由してテレビジョン受像機に映像出力すると、記録していないにもかかわらず、出力される映像信号の振幅が低下するという問題点があった。
【００１２】
本発明は、上記問題点を解決するもので、ビデオテープレコーダが記録状態でないときには、複製を制限するための信号が付加された映像信号が入力されても、出力される映像信号の振幅の低下がない自動利得制御回路を提供することを目的とする。
【００１３】
【課題を解決するための手段】
本発明は上記の目的を達成するために、入力端子と、前記入力端子からの入力信号を入力とする振幅調整が可能な増幅回路と、前記増幅回路の出力を入力とするローパスフィルタと、前記ローパスフィルタの出力を入力とするクランプ回路と、前記クランプ回路の出力を入力とする同期信号分離回路と、前記同期信号分離回路の出力を入力とし前記同期信号分離回路の出力の立ち上がりから第１の所定の幅の矩形波を出力する第１の矩形波発生回路と、前記同期信号分離回路の出力を入力とし前記同期信号分離回路の出力の立ち上がりから第２の所定の幅の矩形波を出力する第２の矩形波発生回路と、前記同期信号分離回路の出力を入力とし前記同期信号分離回路の出力の立ち上がりから第３の所定幅の矩形波を出力する第３の矩形波発生回路と、前記同期信号分離回路の出力を入力とし前記同期信号分離回路の出力を反転して出力する第１の反転回路と、前記第１の矩形波発生回路と前記第２の矩形発生回路の出力を入力とし前記第１の矩形波発生回路と前記第２の矩形発生回路の出力を切り換えるスイッチ回路と、前記スイッチ回路を制御する信号を入力する第１の制御信号入力端子と、前記スイッチ回路の出力を入力とし前記スイッチ回路の出力を反転して出力する第２の反転回路と、前記同期信号分離回路の出力と、前記第２の反転回路の出力を入力し論理積の結果を出力する第１の論理積回路と、前記第１の論理積回路の出力を入力とし前記第１の論理積回路の出力の立ち上がりから第４の所定の幅の矩形波を出力する第４の矩形波発生回路と、前記第４の矩形波発生回路の出力と、前記第３の矩形波発生回路の出力を入力とし論理積の結果を出力する第２の論理積回路と、前記第２の論理回路の出力と前記第１の反転回路の出力とを入力とし論理積の結果を出力する第３の論理積回路と、前記第３の論理積回路の出力と前記クランプ回路の出力とを入力とし前記クランプ回路の出力に前記第３の論理積回路の出力を加算する加算回路と、前記加算回路の出力を入力とし前記加算回路の出力の最大値を検波する最大値検波回路と、前記最大値検波回路の出力を入力とし所定の直流電圧と比較する比較回路とを備え、ビデオテープレコーダが記録状態にないときは、擬似同期信号に対してキーパルスを発生させないことにより、ビデオテープレコーダが記録状態でないときには、複製禁止信号が付加された映像信号が入力されても、出力される映像信号の振幅の低下がない自動利得制御回路である。
【００１４】
この構成によって、ビデオテープレコーダが記録状態でないときには、複製を制限する信号が付加された映像信号が入力されても、出力される映像信号の振幅の低下がないビデオテープレコーダを提供することができる。
【００１５】
【発明の実施の形態】
本発明の請求項１から４に記載の発明は、入力端子と、前記入力端子からの入力信号を入力とする振幅調整が可能な増幅回路と、前記振幅調整が可能な増幅回路の出力を入力とするローパスフィルタと、前記ローパスフィルタの出力を入力とするクランプ回路と、前記クランプ回路の出力を入力とする同期信号分離回路と、前記同期信号分離回路の出力を入力とし、前記同期信号分離回路の出力の立ち上がりから第１の所定の幅の矩形波を出力する第１の矩形波発生回路と、前記同期信号分離回路の出力を入力とし、前記同期信号分離回路の出力の立ち上がりから第２の所定の幅の矩形波を出力する第２の矩形波発生回路と、前記同期信号分離回路の出力を入力とし、前記同期信号分離回路の出力の立ち上がりから第３の所定の幅の矩形波を出力する第３の矩形波発生回路と、前記同期信号分離回路の出力を入力とし、前記同期信号分離回路の出力を反転して出力する第１の反転回路と、前記第１の矩形波発生回路と前記第２の矩形発生回路の出力を入力とし、前記第１の矩形波発生回路と前記第２の矩形波発生回路の出力を切り換えるスイッチ回路と、前記スイッチ回路を制御する信号を入力する第１の制御信号入力端子と、前記スイッチ回路の出力を入力とし、前記スイッチ回路の出力を反転して出力する第２の反転回路と、前記同期信号分離回路の出力と、前記第２の反転回路の出力を入力し、論理積の結果を出力する第１の論理積回路と、前記第１の論理積回路の出力を入力とし、前記第１の論理積回路の出力の立ち上がりから第４の所定の幅の矩形波を出力する第４の矩形波発生回路と、前記第４の矩形波発生回路の出力と、前記第３の矩形波発生回路の出力を入力とし、論理積の結果を出力する第２の論理積回路と、前記第２の論理回路の出力と、前記第１の反転回路の出力を入力とし、論理積の結果を出力する第３の論理積回路と、前記第３の論理積回路の出力と、前記クランプ回路の出力を入力とし、前記クランプ回路の出力に前記第３の論理積回路の出力を加算する加算回路と、前記加算回路の出力を入力とし、前記加算回路の出力の最大値を検波する最大値検波回路と、前記最大値検波回路の出力を入力とし、所定の直流電圧と比較する比較回路を備え、前記比較回路の出力によって前記振幅調整が可能な増幅回路を制御することにより、前記入力端子から入力された映像信号を所定の振幅に制御して出力する自動利得制御回路で、前記水平同期信号分離回路の出力が前記第２の反転回路の出力の矩形波の幅以下のときには前記第４の矩形波発生回路から矩形波を出力しない構成で、前記第１の矩形波発生回路と前記第２の矩形波発生回路の出力を前記スイッチ回路を前記第１の制御信号入力端子からの信号によって切り換えることにより、前記スイッチ回路が第１の矩形波発生回路の出力を選択しているときに、映像信号の垂直帰線期間に所定の信号が付加されていない映像信号が入力されたときは第１の所定の振幅を出力し、映像信号の垂直帰線期間に所定の信号が付加されている映像信号が入力されたときは第２の所定の振幅を出力し、前記スイッチ回路が第２の矩形波発生回路の出力を選択しているときに、映像信号の垂直帰線期間に所定の信号が付加されていない映像信号が入力されたときは第１の所定の振幅を出力し、映像信号の垂直帰線期間に所定の信号が付加されている映像信号が入力されたときにも第１の所定の振幅を出力することを特徴とするもので、ビデオテープレコーダが記録状態にないときは、擬似同期信号に対してキーパルスを発生させないことにより、ビデオテープレコーダが記録状態でないときには、複製を制限する信号が付加された映像信号が入力されても、出力される映像信号の振幅の低下がないという作用を有する。
【００１６】
以下、本発明の実施の形態について、図面を参照しながら説明する。
（実施の形態１）
図１は本実施の形態の自動利得制御回路の構成を示したブロック図である。
【００１７】
図１において、１は入力端子、２は入力端子１から入力された映像信号が入力される振幅制御増幅回路、３は振幅制御増幅回路２の出力信号から色信号を除去するローパスフィルタ、４はクランプ回路、５はクランプ回路４の出力から複合同期分離信号を分離する同期信号分離回路であり、同期信号分離回路５の出力は第１の論理積回路９と、第１の矩形波発生回路１５と、第３の矩形波発生回路１２と、第１の反転回路１３とに入力される。１５は同期信号分離回路５の出力信号の立ち上がりから第１の所定幅の矩形波を発生する第１の矩形波発生回路、１７は同期信号の立ち上がりから擬似同期信号よりも幅が広く垂直帰線期間以外の同期信号の幅より狭い矩形波を発生させる第２の矩形波発生回路、１８は第１及び第２の矩形波発生回路１５及び１７の内一方を制御信号入力端子１９からの制御信号により選択するスイッチ回路、１６はスイッチ回路１８の出力信号を反転した信号を発生する第２の反転回路、９は同期信号分離回路５の出力信号と第２の反転回路１６の出力信号とを論理積演算する第１の論理積回路、１０は第１の論理積回路９の出力信号の立ち上がりから第４の所定幅の矩形波を発生する第４の矩形波発生回路、１２は同期信号分離回路５の出力信号の立ち上がりから第３の所定幅の矩形波を発生する第３の矩形波発生回路、１１は第４の矩形波発生回路１０の出力信号と第３の矩形波発生回路１２の出力信号とを論理積演算する第２の論理積回路、１３は同期信号分離回路５の出力信号を反転する第１の反転回路、１４は第２の論理積回路１１の出力信号と第１の反転回路１３の出力信号とを論理積演算する第３の論理積回路、６は第３の論理積回路１４の出力信号とクランプ回路４の出力信号とを加算する加算回路、７は加算回路６の出力信号の最大値を検波する最大値検波回路、８は比較回路であり、比較回路８の出力が振幅制御増幅回路２に帰還される。図４はスイッチ回路１８が第１の矩形波発生回路１５を選択したときの各部の信号波形図、図５はスイッチ回路１８が第２の矩形波発生回路１７を選択したときの各部の信号波形図を示したものである。
【００１８】
以上のように構成された本実施の形態の自動利得制御回路について、以下スイッチ回路１８が第１の矩形波発生回路１５側を選択した時の動作について図４と共に説明する。
【００１９】
入力端子１から入力された映像信号（図４（ａ））は振幅制御増幅回路２を介して、ローパスフィルタ３で色信号が除去される。ローパスフィルタ３の出力信号はクランプ回路４を介して、同期信号分離回路５で複合同期信号（図４（ｂ））が分離されると共に、加算回路６に入力される。同期信号分離回路５の出力信号は、第１の論理積回路９、第１の矩形波発生回路１５、第２の矩形波発生回路１７、第３の矩形波発生回路１２、第１の反転回路１３に入力される。
【００２０】
ここでスイッチ回路１８がａ側に切り換えられているため、第１の矩形波発生回路１５から同期信号の立ち上がりから擬似同期信号よりも幅の狭い矩形波（図４（ｃ））が出力される。スイッチ回路１８の出力は第２の反転回路１６で反転され（図４（ｅ））、第１の論理積回路９に入力される。第１の論理積回路９は同期信号分離回路５と第１の反転回路１６の論理積の結果を出力する（図４（ｆ））。第１の論理積回路９の出力信号は第４の矩形波発生回路１０に入力され、第４の矩形波発生回路１０は第１の論理積回路９の出力信号の立ち上がりから矩形波を発生させる（図４（ｇ））。第４の矩形波発生回路１０の出力する矩形波の立ち下がり位置は、垂直帰線期間以外の同期信号分離回路５の出力の立ち下がりと垂直帰線期間以外の映像信号のバックポーチの終了位置の間になるように設定する。
【００２１】
第３の矩形波発生回路１２は同期信号分離回路５の出力信号の立ち上がりから矩形波を発生させる（図４（ｈ））。第３の矩形波発生回路１２の出力する矩形波の立ち下がりは、垂直帰線期間以外の映像信号のバックポーチの終了位置になるように設定する。第４の矩形波発生回路１０の出力信号と第３の矩形波発生回路１２の出力信号とは第２の論理積回路１１に入力され論理積演算される（図４（ｉ））。また、同期信号分離回路５の出力信号を第１の反転回路１３で反転させた信号（図４（ｊ））は第３の論理積回路１４に入力され、第３の論理積回路１４では第２の論理積回路１１の出力信号と第１の反転回路１３の出力信号の論理積の結果を出力する（図４（ｋ））。
【００２２】
このようにして作成した第３の論理積回路１４の出力信号をキーパルスとし、加算回路６でクランプ回路４の出力に加算した信号（図４（ｌ））を、最大値検波回路７で最大値検波し（図４（ｍ））、比較回路８で基準の直流電圧と比較することにより振幅制御増幅回路２の出力が一定の値になるように帰還をかける。
【００２３】
次に、スイッチ回路１８が第２の矩形波発生回路１７側を選択した時の動作について図５と共に説明する。
【００２４】
入力端子１から入力された映像信号（図５（ａ））は振幅制御増幅回路２を介して、ローパスフィルタ３で色信号が除去される。ローパスフィルタ３の出力信号はクランプ回路４を介して、同期信号分離回路５で複合同期信号（図５（ｂ））が分離されると共に、加算回路６に入力される。同期信号分離回路５の出力信号は、第１の論理積回路９、第１の矩形波発生回路１５、第２の矩形波発生回路１７、第３の矩形波発生回路１２、第１の反転回路１３に入力される。
【００２５】
ここでスイッチ回路１８がｂ側に接続されているため、第２の矩形波発生回路１７で発生した同期信号の立ち上がりから擬似同期信号よりも幅が広く垂直帰線期間以外の同期信号の幅より狭い矩形波（図５（ｄ））がスイッチ回路１８から出力される。スイッチ回路１８の出力は第２の反転回路１６で反転され（図５（ｅ））、第２の反転回路１６の出力信号は第１の論理積回路９に入力される。第１の論理積回路９は同期信号分離回路５の出力信号と第１の反転回路１６の出力信号とを論理積演算して出力する（図５（ｆ））。第１の論理積回路９は第４の矩形波発生回路１０に入力され、第１の論理積回路９の出力信号の立ち上がりから矩形波を発生させる（図５（ｇ））。第４の矩形波発生回路１０の出力する矩形波の立ち下がり位置は、垂直帰線期間以外の同期信号分離回路５の出力の立ち下がりと垂直帰線期間以外の映像信号のバックポーチの終了位置の間になるように設定する。
【００２６】
一方、第３の矩形波発生回路１２は同期信号分離回路５の出力信号の立ち上がりから矩形波を発生させる（図５（ｈ））。第３の矩形波発生回路の出力する矩形波の立ち下がりは、垂直帰線期間以外の映像信号のバックポーチの終了位置になるように設定する。第２の論理積回路１１は第４の矩形波発生回路１０の出力信号と第３の矩形波発生回路１２の出力信号との論理積の結果を出力する（図５（ｉ））。第３の論理積回路１４は、第２の論理積回路１１の出力信号と第１の反転回路１３の出力信号（図５（ｊ））との論理積の結果を出力する（図５（ｋ））。
【００２７】
このようにして作成した第３の論理積回路１４の出力信号をキーパルスとし、加算回路６でクランプ回路４の出力に加算した信号（図５（ｌ））を、最大値検波回路７で最大値検波し（図５（ｍ））、比較回路８で基準の直流電圧と比較することにより振幅制御増幅回路２の出力が一定の値になるように帰還をかける。
【００２８】
図４、図５の映像信号のＢ部分において、スイッチ回路１８が第１の矩形波発生回路１５の出力を選択しているときはＢ部分の擬似同期信号に対してキーパルスを発生し、スイッチ回路１８が第２の矩形波発生回路１７の出力を選択しているときはＢ部分の擬似同期信号に対してキーパルスを発生しない。
【００２９】
以上のように本実施の形態によれば、ビデオテープレコーダが記録状態のときにはスイッチ回路１８が第１の矩形波発生回路１５の出力を選択し、ビデオテープレコーダが記録状態以外のときにはスイッチ回路１８が第２の矩形波発生回路１７の出力を選択するように設定することにより、ビデオテープレコーダが記録状態でないときには、複製を制限する信号が付加された映像信号が入力されても、出力される映像信号の振幅の低下がないビデオテープレコーダを提供することができる。
【００３０】
（実施の形態２）
以下、本発明の第２の実施の形態について図面を用いて説明する。
【００３１】
図２は本実施の形態の自動利得制御回路の構成を示したブロック図である。図２において、図１に示す実施の形態１と同様の構成要素については、その説明は省略する。２２は同期信号分離回路５の出力同期信号と後述する論理和回路２１の出力信号とが入力される第４の論理積回路、２０は第４の論理積回路２２の出力の立ち上がりから１水平同期期間の４分の３より広く１水平同期期間より狭い矩形波を発生する第５の矩形波発生回路、２３は第５の矩形波発生回路２０の出力信号を反転させる第３の反転回路、２１は第３の反転回路２３の出力信号と制御信号入力端子２４からの制御信号とにより論理和演算される論理和回路である。図６は図２における第２の制御信号入力端子２４が真のときの各部の信号波形図を示したもの、図７は第２の制御信号入力端子２４が偽のときの各部の信号波形図を示したものである。
【００３２】
以上のように構成された本実施の形態の自動利得制御回路について、以下制御信号入力端子２４が真の時の動作について図６と共に説明する。
【００３３】
入力される映像信号（図６（ａ））に対して、同期信号分離回路５によって同期信号（図６（ｂ））が分離される。その同期信号は第５の矩形波発生回路２０に入力され、第４の論理積回路２２の出力の立ち上がりから１水平同期期間の４分の３より広く、１水平同期期間より狭い矩形波（図６（ｃ））を発生する。ここで、第２の制御信号入力端子２４が真であるため、論理和回路２１の出力信号（図６（ｄ））は真となり、同期信号分離回路５の出力信号がそのまま第４の論理積回路２２から出力される（図６（ｅ））。
【００３４】
第１の矩形波発生回路１５は第４の論理積回路２２の出力の立ち上がりから擬似同期信号よりも幅の狭い矩形波（図６（ｆ））を発生させる。第１の矩形波発生回路１５の出力信号は、第２の反転回路１６で反転され（図６（ｇ））、第１の論理積回路９は第４の論理積回路２２の出力信号と第２の反転回路１６の出力信号との論理積の結果を出力する（図６（ｈ））。第１の論理積回路９の出力信号は、第４の矩形波発生回路１０に入力される。第４の矩形波発生回路１０は第１の論理積回路９の出力信号の立ち上がりから矩形波（図６（ｉ））を発生させる。第４の矩形波発生回路１０の出力する矩形波の立ち下がり位置は、垂直帰線期間以外の同期信号分離回路５の出力の立ち下がりと垂直帰線期間以外の映像信号のバックポーチの終了位置の間になるように設定する。
【００３５】
第３の矩形波発生回路１２は第４の論理積回路２２の出力信号の立ち上がりから矩形波（図６（ｊ））を発生させる。第３の矩形波発生回路１２の出力する矩形波の立ち下がりは、垂直帰線期間以外の映像信号のバックポーチの終了位置になるように設定する。第３の矩形波発生回路１２の出力信号は第２の論理積回路１１に入力され、第２の論理積回路１１は第４の矩形波発生回路１０の出力信号と第３の矩形波発生回路１２の出力信号の論理積の結果を出力する（図６（ｋ））。第３の論理積回路１４は第２の論理積回路１１の出力信号と第１の反転回路１３の出力信号（図６（ｌ））の論理積の結果を出力する（図６（ｍ））。
【００３６】
このようにして作成した第３の論理積回路１４の出力信号をキーパルスとし、加算回路６でクランプ回路４の出力信号に加算した結果（図６（ｎ））を、最大値検波回路７で最大値検波（図６（ｏ））し、比較回路８で基準の直流電圧と比較することにより、振幅制御増幅回路２の出力が一定の値になるように帰還をかける。
【００３７】
次に、制御信号入力端子２４が偽の時の動作について図７と共に説明する。
入力される映像信号（図７（ａ））に対して、同期信号分離回路５によって同期信号（図７（ｂ））が分離される。その同期信号は第５の矩形波発生回路２０に入力され、第４の論理積回路２２の出力の立ち上がりから１水平同期期間の４分の３より広く、１水平同期期間より狭い矩形波（図７（ｃ））を発生する。ここで、第２の制御信号入力端子２４が偽であるため、論理和回路２１の出力信号（図７（ｄ））は第３の反転回路２３の出力信号に応じて真または偽となり、第４の論理積回路２２への出力信号が偽の時には同期信号分離回路５の出力信号は第４の論理積回路２２の出力には出力されない。真の時には同期信号分離回路５の出力信号がそのまま第４の論理積回路２２から出力される（図７（ｅ））。
【００３８】
第１の矩形波発生回路１５は第４の論理積回路２２の出力の立ち上がりから擬似同期信号よりも幅の狭い矩形波（図７（ｆ））を発生させる。第１の矩形波発生回路１５の出力信号は、第２の反転回路１６で反転され（図７（ｇ））、第１の論理積回路９は第４の論理積回路２２の出力信号と第２の反転回路１６の出力信号との論理積の結果を出力する（図７（ｈ））。第１の論理積回路９の出力信号は、第４の矩形波発生回路１０に入力される。第４の矩形波発生回路１０は第１の論理積回路９の出力信号の立ち上がりから矩形波（図７（ｉ））を発生させる。第４の矩形波発生回路１０の出力する矩形波の立ち下がり位置は、垂直帰線期間以外の同期信号分離回路５の出力の立ち下がりと垂直帰線期間以外の映像信号のバックポーチの終了位置の間になるように設定する。
【００３９】
第３の矩形波発生回路１２は第４の論理積回路２２の出力信号の立ち上がりから矩形波（図７（ｊ））を発生させる。第３の矩形波発生回路１２の出力する矩形波の立ち下がりは、垂直帰線期間以外の映像信号のバックポーチの終了位置になるように設定する。第３の矩形波発生回路１２の出力信号は第２の論理積回路１１に入力され、第２の論理積回路１１は第４の矩形波発生回路１０の出力信号と第３の矩形波発生回路１２の出力信号の論理積の結果を出力する（図７（ｋ））。第３の論理積回路１４は第２の論理積回路１１の出力信号と第１の反転回路１３の出力信号（図７（ｌ））の論理積の結果を出力する（図７（ｍ））。
【００４０】
このようにして作成した第３の論理積回路１４の出力信号をキーパルスとし、加算回路６でクランプ回路４の出力信号に加算した結果（図７（ｎ））を、最大値検波回路７で最大値検波（図７（ｏ））し、比較回路８で基準の直流電圧と比較することにより、振幅制御増幅回路２の出力が一定の値になるように帰還をかける。
【００４１】
図６、図７の映像信号のＢ部分において、制御信号入力端子２４が真のときはＢ部分の擬似同期信号に対してキーパルスを発生し、制御信号入力端子２４が偽のときはＢ部分の擬似同期信号に対してキーパルスを発生しない。
【００４２】
以上のように本実施の形態によれば、ビデオテープレコーダが記録状態のときには制御信号入力端子２４が真となり、ビデオテープレコーダが記録状態以外のときには制御信号入力端子２４が偽となるように設定することにより、ビデオテープレコーダが記録状態でないときには、複製を制限するための信号が付加された映像信号が入力されても、出力される映像信号の振幅の低下がないビデオテープレコーダを提供することができる。
【００４３】
【発明の効果】
以上のように本発明によれば、ビデオテープレコーダが記録状態のときには制御信号入力端子が真となり、ビデオテープレコーダが記録状態以外のときには制御信号入力端子が偽となるように設定することにより、ビデオテープレコーダが記録状態でないときには、複製を制限するための信号が付加された映像信号が入力されても、出力される映像信号の振幅の低下がないビデオテープレコーダを提供することができる。
【図面の簡単な説明】
【図１】本発明の実施の形態１における自動利得制御回路のブロック図
【図２】本発明の実施の形態２における自動利得制御回路のブロック図
【図３】従来の自動利得制御回路のブロック図
【図４】本発明の実施の形態１における自動利得制御回路のスイッチ回路が第１の矩形波発生回路１５の出力を選択したときの各部の信号波形図
【図５】本発明の実施の形態１における自動利得制御回路のスイッチ回路が第２の矩形波発生回路１７の出力を選択したときの各部の信号波形図
【図６】本発明の実施の形態２における自動利得制御回路の制御信号入力端子２４が真ときの各部の信号波形図
【図７】本発明の実施の形態２における自動利得制御回路の制御信号入力端子２４が偽ときの各部の信号波形図
【図８】従来の自動利得制御回路の制御信号入力端子２４が真ときの各部の信号波形図
【図９】映像信号の垂直帰線期間を示した波形図
【図１０】従来の自動利得制御回路の同期信号とキーパルスの関係を示した波形図
【符号の説明】
１入力端子
２振幅制御増幅回路
３ローパスフィルタ
４クランプ回路
５同期信号分離回路
６加算回路
７最大値検波回路
８比較器
９第１の論理積回路
１０第４の矩形波発生回路
１１第２の論理積回路
１２第３の矩形波発生回路
１３第１の反転回路
１４第３の論理積回路
１５第１の矩形波発生回路
１６第２の反転回路
１７第２の矩形波発生回路
１８スイッチ回路
１９第１の制御信号入力端子
２０第５の矩形波発生回路
２１論理和回路
２２第４の論理積回路
２３第３の反転回路
２４第２の制御信号入力端子[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an automatic gain control circuit (hereinafter, abbreviated as an AGC circuit) in a video recording / reproducing apparatus (hereinafter, abbreviated as a video tape recorder) for recording and reproducing a video signal.
[0002]
[Prior art]
Hereinafter, an AGC circuit used in a conventional video tape recorder will be described with reference to the drawings.
[0003]
FIG. 3 is a block diagram showing a configuration of a conventional AGC circuit. In FIG. 3, 1 is an input terminal, 2 is an amplitude control amplifier circuit to which a video signal input from the input terminal 1 is input, 3 is a low-pass filter for removing a color signal from an output signal of the amplitude control amplifier circuit 2, 4 is The clamp circuit 5 is a synchronizing signal separating circuit for separating a composite synchronizing separation signal from the output of the clamping circuit 4. The output of the synchronizing signal separating circuit 5 is a first AND circuit 9 and a first rectangular wave generating circuit 15. Is input to the third rectangular wave generating circuit 12 and the first inverting circuit 13. Reference numeral 15 denotes a first rectangular wave generating circuit for generating a rectangular wave of a first predetermined width from the rising edge of the output signal of the synchronization signal separating circuit 5, and 16 denotes a signal obtained by inverting the output signal of the first rectangular wave generating circuit 15. The generated second inverting circuit 9 is a first AND circuit for performing an AND operation on the output signal of the synchronization signal separating circuit 5 and the output signal of the second inverting circuit 16, and 10 is the first AND circuit 9 A fourth rectangular wave generating circuit for generating a fourth predetermined rectangular wave from the rising edge of the output signal of the second signal; and a fourth rectangular wave generating circuit 12 for generating a third rectangular wave of the third predetermined width from the rising edge of the output signal of the synchronizing signal separating circuit 5. 3 is a rectangular wave generating circuit, 11 is a second logical AND circuit for calculating the logical product of the output signal of the fourth rectangular wave generating circuit 10 and the output signal of the third rectangular wave generating circuit 12, and 13 is the synchronizing signal separation. A first inverting circuit for inverting the output signal of the circuit 5; A third AND circuit 6 for performing an AND operation on the output signal of the AND circuit 11 and the output signal of the first inverting circuit 13, and the output of the third AND circuit 14, the output signal of the clamp circuit 4, , A maximum value detection circuit 7 for detecting the maximum value of the output signal of the addition circuit 6, and a comparison circuit 8. The output of the comparison circuit 8 is fed back to the amplitude control amplification circuit 2. FIG. 10 shows a signal waveform diagram of each part in the synchronization signal separation circuit of FIG.
[0004]
In the conventional automatic gain control circuit configured as described above, the operation after the synchronization signal separation circuit will be described below.
[0005]
The output signal of the synchronizing signal separating circuit 5 shown in FIG. 10A is obtained by a first AND circuit 9, a first rectangular wave generating circuit 15, a third rectangular wave generating circuit 12, and a first inverting circuit. 13 is input. The first rectangular wave generating circuit 15 outputs a rectangular wave having a first predetermined width (FIG. 10B) from the rise of the output signal of the synchronization signal separating circuit 5. The output signal of the first rectangular wave generating circuit 15 is input to a second inverting circuit 16, and a signal (FIG. 10 (c)) obtained by inverting the first rectangular wave generating circuit 15 is output from the second inverting circuit 16. Is output. The output signal of the synchronizing signal separating circuit 5 and the output signal of the second inverting circuit 16 are input to the first AND circuit 9, and the logical product of the output of the synchronizing signal separating circuit 5 and the output of the second inverting circuit 16 is obtained. The result is output (FIG. 10D). The output signal of the first AND circuit 9 is input to the fourth rectangular wave generation circuit 10. The fourth rectangular wave generation circuit 10 outputs a fourth predetermined rectangular wave (FIG. 10E) from the rising edge of the output signal of the first AND circuit 9.
[0006]
On the other hand, the third rectangular wave generating circuit 12 outputs a rectangular wave having a third predetermined width (FIG. 10 (f)) from the rising edge of the output signal of the synchronization signal separating circuit 5. The output signal of the fourth square wave generation circuit 10 and the output signal of the third square wave generation circuit 12 are input to the second AND circuit 11, and the output of the fourth square wave generation circuit 10 and the third The result of the logical product of the outputs of the square wave generation circuit 12 is output (FIG. 10 (g)). The output signal of the second AND circuit 11 and the output signal (FIG. 10 (h)) of the first inverting circuit 13 are input to the third AND circuit 14, and the output of the second AND circuit 11 The result of the logical product of the outputs of the 1 inverting circuit is output (FIG. 10 (i)).
[0007]
With this configuration, the output of the third AND circuit 14 is greater than the width of the rectangular wave having the first predetermined width, and is smaller than the width of the rectangular wave having the fourth predetermined width. A rectangular wave is output only for the output (hereinafter, the output of the third AND circuit 14 is referred to as a key pulse).
[0008]
Next, an operation when a video signal to which a predetermined signal is added during a vertical blanking period is input to a conventional AGC circuit will be described with reference to FIGS.
[0009]
FIG. 9 is a waveform diagram showing a part of a vertical blanking period of a video signal. The video signal in FIG. 9A is a video signal to which a predetermined signal is not added in a vertical blanking period, and the video signal in FIG. 9B is a video signal to which a predetermined signal is added in a vertical blanking period. It shows a signal.
[0010]
FIG. 8A is an enlarged view of portions A and B in FIG. In the case of a video signal to which a predetermined signal is added during the vertical blanking period, a pseudo-synchronous signal and a 100% white signal are alternately inserted in the portion B. In response to this signal, the conventional AGC circuit adds a key pulse to the 100% white signal portion and controls the gain so that the maximum value becomes a predetermined value. It becomes smaller than when a video signal not added is input. This is used to limit duplication of video signals.
[0011]
[Problems to be solved by the invention]
However, in the above conventional configuration, there is a broadcast signal to which a signal for unintentionally restricting duplication is added in a cable television broadcast or the like, and such a broadcast signal is transmitted to a television receiver via a video tape recorder. However, there is a problem that the amplitude of the output video signal is reduced even if the video signal is not recorded.
[0012]
The present invention solves the above problem. When the video tape recorder is not in a recording state, even if a video signal to which a signal for limiting duplication is added is input, the amplitude of the output video signal decreases. It is an object to provide an automatic gain control circuit having no.
[0013]
[Means for Solving the Problems]
In order to achieve the above object, the present invention provides an input terminal, an amplifier circuit capable of adjusting the amplitude of an input signal from the input terminal as an input, a low-pass filter having an output of the amplifier circuit as an input, A clamp circuit that receives an output of the low-pass filter as an input, a synchronization signal separation circuit that receives an output of the clamp circuit as an input, and a first signal from an output of the synchronization signal separation circuit that receives an output of the synchronization signal separation circuit as an input. A first rectangular wave generating circuit for outputting a rectangular wave having a predetermined width, and an output of the synchronizing signal separating circuit as an input and outputting a rectangular wave having a second predetermined width from a rising edge of the output of the synchronizing signal separating circuit. A second rectangular wave generating circuit, and a third rectangular wave generating circuit that receives the output of the synchronous signal separating circuit as an input and outputs a rectangular wave of a third predetermined width from the rising edge of the output of the synchronous signal separating circuit. A first inverting circuit which receives an output of the synchronizing signal separating circuit as an input and inverts an output of the synchronizing signal separating circuit and outputs the inverted signal; an output of the first rectangular wave generating circuit and an output of the second rectangular generating circuit And a switch circuit for switching the output of the first rectangular wave generating circuit and the second rectangular generating circuit with an input, a first control signal input terminal for inputting a signal for controlling the switch circuit, A second inverting circuit that receives an output as an input, inverts the output of the switch circuit and outputs the inverted signal, an output of the synchronization signal separating circuit, and an output of the second inverting circuit that outputs an AND result. And a fourth rectangular wave generating circuit that receives the output of the first logical product circuit as an input and outputs a rectangular wave of a fourth predetermined width from the rising edge of the output of the first logical product circuit And the fourth square wave generation time And an output of the third rectangular wave generating circuit, a second AND circuit for outputting the result of AND operation, and an output of the second logical circuit and an output of the first inverting circuit. And a third AND circuit which outputs a result of the AND operation, and an output of the third AND circuit and an output of the clamp circuit, and the third AND circuit outputs the output of the clamp circuit. An addition circuit that adds the outputs of the addition circuits, a maximum value detection circuit that receives the output of the addition circuit as an input, and detects a maximum value of the output of the addition circuit, and compares the output of the maximum value detection circuit as an input with a predetermined DC voltage. When the video tape recorder is not in a recording state, a video signal to which a duplication inhibiting signal is added when the video tape recorder is not in a recording state by not generating a key pulse with respect to the pseudo synchronization signal when the video tape recorder is not in a recording state. Is an automatic gain control circuit in which the amplitude of the output video signal does not decrease even if the input is input.
[0014]
With this configuration, when the video tape recorder is not in the recording state, it is possible to provide a video tape recorder in which the amplitude of the output video signal does not decrease even if the video signal to which the signal for limiting duplication is added is input. .
[0015]
BEST MODE FOR CARRYING OUT THE INVENTION
The invention according to claims 1 to 4 of the present invention provides an input terminal, an amplitude-adjustable amplifier circuit that receives an input signal from the input terminal, and an output of the amplitude-adjustable amplifier circuit. A low-pass filter, a clamp circuit that receives an output of the low-pass filter, a synchronization signal separation circuit that receives an output of the clamp circuit, and a synchronization signal separation circuit that receives an output of the synchronization signal separation circuit. A first rectangular wave generating circuit that outputs a rectangular wave of a first predetermined width from the rising edge of the output of the first input terminal, an output of the synchronous signal separating circuit, and a second rectangular wave generating circuit that outputs the second rectangular wave from the rising edge of the output of the synchronous signal separating circuit. A second rectangular wave generating circuit for outputting a rectangular wave having a predetermined width, and an output of the synchronizing signal separating circuit as inputs, and a rectangular wave having a third predetermined width from the rising edge of the output of the synchronizing signal separating circuit. A third rectangular wave generating circuit, an output of the synchronizing signal separating circuit, a first inverting circuit for inverting an output of the synchronizing signal separating circuit and outputting the same, and a first rectangular wave generating circuit And a switch circuit that receives the output of the second rectangular wave generating circuit as an input, switches between the outputs of the first rectangular wave generating circuit and the second rectangular wave generating circuit, and a signal that controls the switch circuit. A second control signal input terminal, an output of the switch circuit, a second inverting circuit for inverting and outputting the output of the switch circuit, an output of the synchronization signal separating circuit, and a second inverting circuit. A first AND circuit for receiving the output of the first AND circuit, receiving the output of the first AND circuit, and inputting the output of the first AND circuit as an input. Output a rectangular wave of width A second AND circuit which receives the output of the fourth rectangular wave generating circuit, the output of the fourth rectangular wave generating circuit, and the output of the third rectangular wave generating circuit, and outputs a logical product result; A third AND circuit which receives an output of a logic circuit, an output of the first inverting circuit as input, and outputs a result of AND, an output of the third AND circuit, and an output of the clamp circuit; An input circuit, an addition circuit that adds the output of the third AND circuit to the output of the clamp circuit, a maximum value detection circuit that receives the output of the addition circuit, and detects the maximum value of the output of the addition circuit; A comparison circuit that receives an output of the maximum value detection circuit as an input and compares the output with a predetermined DC voltage, and controls the amplification circuit capable of adjusting the amplitude by the output of the comparison circuit, thereby inputting the signal from the input terminal. Control the video signal to An automatic gain control circuit that outputs a rectangular wave from the fourth rectangular wave generating circuit when the output of the horizontal synchronizing signal separating circuit is equal to or smaller than the width of the rectangular wave of the output of the second inverting circuit; By switching the output of the first rectangular wave generating circuit and the output of the second rectangular wave generating circuit with the signal from the first control signal input terminal, the switch circuit generates the first rectangular wave. When the output of the circuit is selected, when a video signal to which a predetermined signal is not added is input during the vertical blanking period of the video signal, a first predetermined amplitude is output, and the vertical feedback of the video signal is performed. When a video signal to which a predetermined signal is added during the line period is input, a second predetermined amplitude is output, and when the switch circuit selects the output of the second rectangular wave generation circuit, Vertical retrace period of video signal When a video signal to which a predetermined signal is not added is input, a first predetermined amplitude is output, and when a video signal to which a predetermined signal is added during a vertical blanking period of the video signal is input. Is also characterized by outputting the first predetermined amplitude. When the video tape recorder is not in the recording state, the key pulse is not generated for the pseudo-synchronous signal so that the video tape recorder is not in the recording state. Even if a video signal to which a signal for restricting duplication is added is input, the amplitude of the output video signal does not decrease.
[0016]
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(Embodiment 1)
FIG. 1 is a block diagram showing the configuration of the automatic gain control circuit according to the present embodiment.
[0017]
In FIG. 1, 1 is an input terminal, 2 is an amplitude control amplifier circuit to which a video signal input from the input terminal 1 is input, 3 is a low-pass filter for removing a color signal from an output signal of the amplitude control amplifier circuit 2, 4 is The clamp circuit 5 is a synchronizing signal separating circuit for separating a composite synchronizing separation signal from the output of the clamping circuit 4. The output of the synchronizing signal separating circuit 5 is a first AND circuit 9 and a first rectangular wave generating circuit 15. Is input to the third rectangular wave generating circuit 12 and the first inverting circuit 13. Reference numeral 15 denotes a first rectangular wave generating circuit that generates a rectangular wave of a first predetermined width from the rising edge of the output signal of the synchronizing signal separation circuit 5, and 17 denotes a vertical retrace from the rising edge of the synchronizing signal which is wider than the pseudo synchronizing signal. A second rectangular wave generating circuit 18 for generating a rectangular wave narrower than the width of the synchronization signal other than the period is connected to one of the first and second rectangular wave generating circuits 15 and 17 by a control signal from a control signal input terminal 19. , A second inverting circuit for generating a signal obtained by inverting the output signal of the switching circuit, and a logical circuit between the output signal of the synchronizing signal separating circuit and the output signal of the second inverting circuit. A first AND circuit 10 for performing a product operation; a fourth rectangular wave generating circuit 10 for generating a fourth predetermined rectangular wave from the rising edge of the output signal of the first AND circuit 9; 5 output signal rise A third rectangular wave generating circuit for generating a rectangular wave having a third predetermined width from the beam, and a logical AND of an output signal of the fourth rectangular wave generating circuit and an output signal of the third rectangular wave generating circuit; A second AND circuit for performing an operation, 13 is a first inverting circuit for inverting an output signal of the synchronizing signal separating circuit 5, and 14 is an output signal of the second AND circuit 11 and an output signal of the first inverting circuit 13 Is a third AND circuit for performing a logical AND operation on the AND circuit, 6 is an adding circuit for adding the output signal of the third AND circuit 14 and the output signal of the clamp circuit 4, and 7 is the maximum value of the output signal of the adding circuit 6. Is a comparison circuit, and the output of the comparison circuit 8 is fed back to the amplitude control amplification circuit 2. FIG. 4 is a signal waveform diagram of each part when the switch circuit 18 selects the first rectangular wave generating circuit 15, and FIG. 5 is a signal waveform of each part when the switch circuit 18 selects the second rectangular wave generating circuit 17. FIG.
[0018]
The operation of the automatic gain control circuit of the present embodiment configured as described above when the switch circuit 18 selects the first rectangular wave generation circuit 15 will be described below with reference to FIG.
[0019]
The video signal (FIG. 4A) input from the input terminal 1 passes through the amplitude control amplifier circuit 2 and the low-pass filter 3 removes the color signal. The output signal of the low-pass filter 3 is separated by the synchronizing signal separating circuit 5 through the clamp circuit 4 into the composite synchronizing signal (FIG. 4B), and is input to the adding circuit 6. The output signal of the synchronizing signal separating circuit 5 is supplied to the first AND circuit 9, the first rectangular wave generating circuit 15, the second rectangular wave generating circuit 17, the third rectangular wave generating circuit 12, the first inverting circuit. 13 is input.
[0020]
Here, since the switch circuit 18 is switched to the a side, the first rectangular wave generating circuit 15 outputs a rectangular wave (FIG. 4C) having a width smaller than that of the pseudo synchronizing signal from the rising edge of the synchronizing signal. . The output of the switch circuit 18 is inverted by the second inverting circuit 16 (FIG. 4E), and is input to the first AND circuit 9. The first AND circuit 9 outputs the result of the logical product of the synchronization signal separating circuit 5 and the first inverting circuit 16 (FIG. 4 (f)). The output signal of the first AND circuit 9 is input to the fourth rectangular wave generating circuit 10, and the fourth rectangular wave generating circuit 10 generates a rectangular wave from the rising edge of the output signal of the first AND circuit 9. (FIG. 4 (g)). The falling position of the rectangular wave output from the fourth rectangular wave generating circuit 10 is determined by the falling edge of the output of the synchronizing signal separation circuit 5 outside the vertical blanking period and the end position of the back porch of the video signal outside the vertical blanking period. Set to be between.
[0021]
The third rectangular wave generating circuit 12 generates a rectangular wave from the rising edge of the output signal of the synchronization signal separating circuit 5 (FIG. 4 (h)). The falling edge of the rectangular wave output from the third rectangular wave generating circuit 12 is set to be the end position of the back porch of the video signal other than the vertical retrace period. The output signal of the fourth square wave generation circuit 10 and the output signal of the third square wave generation circuit 12 are input to the second AND circuit 11 and subjected to AND operation (FIG. 4 (i)). Further, a signal (FIG. 4 (j)) obtained by inverting the output signal of the synchronization signal separating circuit 5 by the first inverting circuit 13 is input to the third AND circuit 14, and the third AND circuit 14 outputs the signal. The result of the logical product of the output signal of the second AND circuit 11 and the output signal of the first inverting circuit 13 is output (FIG. 4 (k)).
[0022]
The output signal of the third AND circuit 14 created in this way is used as a key pulse, and the signal (FIG. 4 (l)) added to the output of the clamp circuit 4 by the addition circuit 6 is converted to the maximum value by the maximum value detection circuit 7. Detection (FIG. 4 (m)) and comparison with a reference DC voltage by the comparison circuit 8 provide feedback so that the output of the amplitude control amplification circuit 2 becomes a constant value.
[0023]
Next, an operation when the switch circuit 18 selects the second rectangular wave generation circuit 17 will be described with reference to FIG.
[0024]
The video signal (FIG. 5A) input from the input terminal 1 passes through the amplitude control amplification circuit 2 and the color signal is removed by the low-pass filter 3. The output signal of the low-pass filter 3 is separated by the synchronizing signal separating circuit 5 via the clamp circuit 4 into the composite synchronizing signal (FIG. 5B) and is input to the adding circuit 6. The output signal of the synchronizing signal separating circuit 5 is supplied to the first AND circuit 9, the first rectangular wave generating circuit 15, the second rectangular wave generating circuit 17, the third rectangular wave generating circuit 12, the first inverting circuit. 13 is input.
[0025]
Here, since the switch circuit 18 is connected to the side b, the width of the synchronization signal generated by the second rectangular wave generation circuit 17 is wider than the pseudo synchronization signal from the rise of the synchronization signal and is smaller than the width of the synchronization signal other than the vertical retrace period. A narrow rectangular wave (FIG. 5D) is output from the switch circuit 18. The output of the switch circuit 18 is inverted by the second inversion circuit 16 (FIG. 5E), and the output signal of the second inversion circuit 16 is input to the first AND circuit 9. The first AND circuit 9 performs a logical AND operation on the output signal of the synchronization signal separating circuit 5 and the output signal of the first inverting circuit 16 and outputs the result (FIG. 5 (f)). The first AND circuit 9 is input to the fourth square wave generation circuit 10 and generates a square wave from the rising edge of the output signal of the first AND circuit 9 (FIG. 5 (g)). The falling position of the rectangular wave output from the fourth rectangular wave generating circuit 10 is determined by the falling edge of the output of the synchronizing signal separation circuit 5 outside the vertical blanking period and the end position of the back porch of the video signal outside the vertical blanking period. Set to be between.
[0026]
On the other hand, the third rectangular wave generating circuit 12 generates a rectangular wave from the rising edge of the output signal of the synchronization signal separating circuit 5 (FIG. 5 (h)). The falling edge of the square wave output from the third square wave generation circuit is set to be the end position of the back porch of the video signal other than the vertical blanking period. The second AND circuit 11 outputs the result of the AND of the output signal of the fourth rectangular wave generating circuit 10 and the output signal of the third rectangular wave generating circuit 12 (FIG. 5 (i)). The third AND circuit 14 outputs a result of AND between the output signal of the second AND circuit 11 and the output signal (FIG. 5 (j)) of the first inverting circuit 13 (FIG. 5 (k)). )).
[0027]
The output signal of the third AND circuit 14 created in this manner is used as a key pulse, and the signal (FIG. 5 (l)) added to the output of the clamp circuit 4 by the addition circuit 6 is converted to the maximum value by the maximum value detection circuit 7. Detection (FIG. 5 (m)) and comparison with a reference DC voltage by the comparison circuit 8 provide feedback so that the output of the amplitude control amplification circuit 2 becomes a constant value.
[0028]
In the B portion of the video signal shown in FIGS. 4 and 5, when the switch circuit 18 selects the output of the first rectangular wave generating circuit 15, a key pulse is generated with respect to the pseudo synchronizing signal of the B portion, When the output 18 selects the output of the second rectangular wave generating circuit 17, no key pulse is generated for the pseudo synchronizing signal of the B portion.
[0029]
As described above, according to the present embodiment, when the video tape recorder is in the recording state, the switch circuit 18 selects the output of the first rectangular wave generation circuit 15, and when the video tape recorder is not in the recording state, the switch circuit 18 selects the output. Is set so as to select the output of the second rectangular wave generation circuit 17, so that when the video tape recorder is not in the recording state, even if a video signal to which a signal for restricting duplication is added is output. A video tape recorder without a decrease in the amplitude of a video signal can be provided.
[0030]
(Embodiment 2)
Hereinafter, a second embodiment of the present invention will be described with reference to the drawings.
[0031]
FIG. 2 is a block diagram showing a configuration of the automatic gain control circuit according to the present embodiment. 2, the description of the same components as those in the first embodiment shown in FIG. 1 is omitted. Reference numeral 22 denotes a fourth AND circuit to which an output synchronizing signal of the synchronizing signal separating circuit 5 and an output signal of an OR circuit 21 to be described later are input, and reference numeral 20 denotes one horizontal synchronizing from the rising of the output of the fourth AND circuit 22. A fifth rectangular wave generating circuit for generating a rectangular wave wider than three-quarters of the period and narrower than one horizontal synchronizing period, 23 is a third inverting circuit for inverting an output signal of the fifth rectangular wave generating circuit 20, 21 Is a logical sum circuit which performs a logical sum operation on the output signal of the third inverting circuit 23 and the control signal from the control signal input terminal 24. FIG. 6 is a signal waveform diagram of each part when the second control signal input terminal 24 in FIG. 2 is true, and FIG. 7 is a signal waveform diagram of each part when the second control signal input terminal 24 is false. It is shown.
[0032]
The operation of the automatic gain control circuit of the present embodiment configured as described above when the control signal input terminal 24 is true will be described below with reference to FIG.
[0033]
The synchronization signal (FIG. 6B) is separated from the input video signal (FIG. 6A) by the synchronization signal separation circuit 5. The synchronizing signal is input to the fifth rectangular wave generating circuit 20, and a rectangular wave wider than three quarters of one horizontal synchronizing period and narrower than one horizontal synchronizing period from the rise of the output of the fourth AND circuit 22 (see FIG. 6 (c)). Here, since the second control signal input terminal 24 is true, the output signal of the OR circuit 21 (FIG. 6D) becomes true, and the output signal of the synchronizing signal separation circuit 5 remains unchanged from the fourth AND. The signal is output from the circuit 22 (FIG. 6E).
[0034]
The first rectangular wave generating circuit 15 generates a rectangular wave (FIG. 6 (f)) having a width smaller than that of the pseudo synchronizing signal from the rising edge of the output of the fourth AND circuit 22. The output signal of the first rectangular wave generation circuit 15 is inverted by the second inversion circuit 16 (FIG. 6 (g)), and the first AND circuit 9 outputs the output signal of the fourth AND circuit 22 The result of the logical product with the output signal of the second inversion circuit 16 is output (FIG. 6 (h)). The output signal of the first AND circuit 9 is input to the fourth rectangular wave generation circuit 10. The fourth rectangular wave generating circuit 10 generates a rectangular wave (FIG. 6 (i)) from the rising edge of the output signal of the first AND circuit 9. The falling position of the rectangular wave output from the fourth rectangular wave generating circuit 10 is determined by the falling edge of the output of the synchronizing signal separation circuit 5 outside the vertical blanking period and the end position of the back porch of the video signal outside the vertical blanking period. Set to be between.
[0035]
The third rectangular wave generating circuit 12 generates a rectangular wave (FIG. 6 (j)) from the rising edge of the output signal of the fourth AND circuit 22. The falling edge of the rectangular wave output from the third rectangular wave generating circuit 12 is set to be the end position of the back porch of the video signal other than the vertical retrace period. The output signal of the third square wave generation circuit 12 is input to the second AND circuit 11, and the second AND circuit 11 outputs the output signal of the fourth square wave generation circuit 10 and the third square wave generation circuit. The result of the logical product of the twelve output signals is output (FIG. 6 (k)). The third AND circuit 14 outputs the result of the AND of the output signal of the second AND circuit 11 and the output signal (FIG. 6 (l)) of the first inverting circuit 13 (FIG. 6 (m)). .
[0036]
The output signal of the third AND circuit 14 created in this manner is used as a key pulse, and the result of addition to the output signal of the clamp circuit 4 by the addition circuit 6 (FIG. 6 (n)) is obtained by the maximum value detection circuit 7 By performing value detection (FIG. 6 (o)) and comparing it with a reference DC voltage by the comparison circuit 8, feedback is applied so that the output of the amplitude control amplification circuit 2 becomes a constant value.
[0037]
Next, the operation when the control signal input terminal 24 is false will be described with reference to FIG.
The synchronization signal (FIG. 7B) is separated from the input video signal (FIG. 7A) by the synchronization signal separation circuit 5. The synchronizing signal is input to the fifth rectangular wave generating circuit 20, and a rectangular wave wider than three quarters of one horizontal synchronizing period and narrower than one horizontal synchronizing period from the rise of the output of the fourth AND circuit 22 (see FIG. 7 (c)). Here, since the second control signal input terminal 24 is false, the output signal of the OR circuit 21 (FIG. 7D) becomes true or false according to the output signal of the third inversion circuit 23, When the output signal to the fourth AND circuit 22 is false, the output signal of the synchronization signal separating circuit 5 is not output to the output of the fourth AND circuit 22. When true, the output signal of the synchronizing signal separation circuit 5 is output from the fourth AND circuit 22 as it is (FIG. 7 (e)).
[0038]
The first rectangular wave generation circuit 15 generates a rectangular wave (FIG. 7 (f)) having a width smaller than that of the pseudo synchronization signal from the rising edge of the output of the fourth AND circuit 22. The output signal of the first rectangular wave generation circuit 15 is inverted by the second inversion circuit 16 (FIG. 7 (g)), and the first AND circuit 9 outputs the output signal of the fourth AND circuit 22 The result of the logical product with the output signal of the second inversion circuit 16 is output (FIG. 7 (h)). The output signal of the first AND circuit 9 is input to the fourth rectangular wave generation circuit 10. The fourth rectangular wave generating circuit 10 generates a rectangular wave (FIG. 7 (i)) from the rising edge of the output signal of the first AND circuit 9. The falling position of the rectangular wave output from the fourth rectangular wave generating circuit 10 is determined by the falling edge of the output of the synchronizing signal separation circuit 5 outside the vertical blanking period and the end position of the back porch of the video signal outside the vertical blanking period. Set to be between.
[0039]
The third rectangular wave generating circuit 12 generates a rectangular wave (FIG. 7 (j)) from the rising edge of the output signal of the fourth AND circuit 22. The falling edge of the rectangular wave output from the third rectangular wave generating circuit 12 is set to be the end position of the back porch of the video signal other than the vertical retrace period. The output signal of the third square wave generation circuit 12 is input to the second AND circuit 11, and the second AND circuit 11 outputs the output signal of the fourth square wave generation circuit 10 and the third square wave generation circuit. The result of the logical product of the twelve output signals is output (FIG. 7 (k)). The third AND circuit 14 outputs the result of the logical product of the output signal of the second AND circuit 11 and the output signal (FIG. 7 (l)) of the first inverting circuit 13 (FIG. 7 (m)). .
[0040]
The output signal of the third AND circuit 14 created in this manner is used as a key pulse, and the result of addition to the output signal of the clamp circuit 4 by the addition circuit 6 (FIG. 7 (n)) is obtained by the maximum value detection circuit 7 By performing value detection (FIG. 7 (o)) and comparing it with a reference DC voltage in the comparison circuit 8, feedback is applied so that the output of the amplitude control amplification circuit 2 becomes a constant value.
[0041]
In the B portion of the video signal of FIGS. 6 and 7, when the control signal input terminal 24 is true, a key pulse is generated for the pseudo synchronizing signal of the B portion, and when the control signal input terminal 24 is false, the key pulse of the B portion is generated. No key pulse is generated for the pseudo synchronization signal.
[0042]
As described above, according to the present embodiment, the control signal input terminal 24 is set to be true when the video tape recorder is in the recording state, and false when the video tape recorder is not in the recording state. A video tape recorder that does not reduce the amplitude of an output video signal even when a video signal to which a signal for restricting duplication is added is input when the video tape recorder is not in a recording state. Can be.
[0043]
【The invention's effect】
As described above, according to the present invention, by setting the control signal input terminal to be true when the video tape recorder is in the recording state and by setting the control signal input terminal to be false when the video tape recorder is not in the recording state, When the video tape recorder is not in the recording state, it is possible to provide a video tape recorder in which the amplitude of the output video signal does not decrease even if a video signal to which a signal for restricting duplication is added is input.
[Brief description of the drawings]
FIG. 1 is a block diagram of an automatic gain control circuit according to a first embodiment of the present invention.
FIG. 2 is a block diagram of an automatic gain control circuit according to a second embodiment of the present invention.
FIG. 3 is a block diagram of a conventional automatic gain control circuit.
FIG. 4 is a signal waveform diagram of each unit when the switch circuit of the automatic gain control circuit according to the first embodiment of the present invention selects the output of the first rectangular wave generation circuit 15;
FIG. 5 is a signal waveform diagram of each unit when the switch circuit of the automatic gain control circuit according to the first embodiment of the present invention selects the output of the second rectangular wave generation circuit 17;
FIG. 6 is a signal waveform diagram of each part when the control signal input terminal 24 of the automatic gain control circuit according to the second embodiment of the present invention is true.
FIG. 7 is a signal waveform diagram of each part when the control signal input terminal 24 of the automatic gain control circuit according to the second embodiment of the present invention is false.
FIG. 8 is a signal waveform diagram of each part when the control signal input terminal 24 of the conventional automatic gain control circuit is true.
FIG. 9 is a waveform diagram showing a vertical blanking period of a video signal.
FIG. 10 is a waveform chart showing a relationship between a synchronization signal and a key pulse in a conventional automatic gain control circuit.
[Explanation of symbols]
1 input terminal
2 Amplitude control amplifier circuit
3 Low-pass filter
4 Clamp circuit
5 Synchronous signal separation circuit
6 Addition circuit
7 Maximum value detection circuit
8 Comparators
9 First AND circuit
10. Fourth rectangular wave generation circuit
11 Second AND circuit
12. Third rectangular wave generating circuit
13 First inversion circuit
14 Third logical product circuit
15 First rectangular wave generating circuit
16 Second inverting circuit
17. Second rectangular wave generating circuit
18 Switch circuit
19 1st control signal input terminal
20 fifth rectangular wave generation circuit
21 OR circuit
22 Fourth AND circuit
23. Third Inverting Circuit
24 Second control signal input terminal

Claims

An input terminal, an amplitude-adjustable amplification circuit that receives an input signal from the input terminal as an input, a low-pass filter that receives an output of the amplification circuit, and a clamp circuit that receives an output of the low-pass filter as an input. A synchronizing signal separating circuit that receives an output of the clamp circuit as an input, and a first that outputs a rectangular wave having a first predetermined width from a rising edge of an output of the synchronizing signal separating circuit that receives an output of the synchronizing signal separating circuit as an input; A rectangular wave generation circuit, a second rectangular wave generation circuit that receives an output of the synchronization signal separation circuit as an input, and outputs a rectangular wave of a second predetermined width from a rising edge of an output of the synchronization signal separation circuit, A third rectangular wave generating circuit that receives an output of the separation circuit as an input and outputs a rectangular wave of a third predetermined width from a rising edge of the output of the synchronization signal separation circuit, and inputs an output of the synchronization signal separation circuit; A first inverting circuit for inverting and outputting an output of the synchronization signal separating circuit; an input of an output of the first rectangular wave generating circuit and an output of the second rectangular wave generating circuit; A switch circuit for switching an output of the circuit and the second rectangular wave generating circuit; a first control signal input terminal for inputting a signal for controlling the switch circuit; an output of the switch circuit which receives an output of the switch circuit as an input; A second inverting circuit for inverting and outputting an output of the synchronizing signal separating circuit, a first AND circuit for receiving an output of the second inverting circuit and outputting a logical product result, A fourth rectangular wave generating circuit that receives an output of the first logical product circuit as an input and outputs a rectangular wave of a fourth predetermined width from a rise of the output of the first logical product circuit; Circuit output and said third rectangular wave generation A second AND circuit that receives the output of the path as an input and outputs the result of the AND operation, and outputs the result of the AND operation by receiving the output of the second AND circuit and the output of the first inverting circuit as inputs A third AND circuit, an addition circuit that receives an output of the third AND circuit and an output of the clamp circuit as inputs, and adds an output of the third AND circuit to an output of the clamp circuit; A maximum value detection circuit that receives an output of the addition circuit as an input and detects a maximum value of an output of the addition circuit; and a comparison circuit that receives an output of the maximum value detection circuit as an input and compares the output with a predetermined DC voltage. Automatic gain control circuit.

An input terminal, an amplitude-adjustable amplification circuit that receives an input signal from the input terminal as an input, a low-pass filter that receives an output of the amplification circuit, and a clamp circuit that receives an output of the low-pass filter as an input. A synchronizing signal separating circuit that receives an output of the clamp circuit as an input, a fourth AND circuit that performs an AND operation by receiving an output of the synchronizing signal separating circuit and an output of an OR circuit described below, A first rectangular wave generating circuit that receives an output of the AND circuit as an input and outputs a rectangular wave of a first predetermined width from a rising edge of the output of the fourth AND circuit, and an output of the fourth AND circuit A second rectangular wave generating circuit that outputs a rectangular wave of a second predetermined width from a rising edge of an output of the fourth logical product circuit as an input; and a fourth rectangular circuit that receives an output of the fourth logical product circuit as an input. Invert the output of the AND circuit A first inverting circuit for receiving the output of the first rectangular wave generating circuit, a second inverting circuit for receiving the output of the first rectangular wave generating circuit as an input, inverting the output of the first rectangular wave generating circuit, and outputting the inverted signal, A rectangular wave generating circuit that receives the output of the AND circuit and outputs a rectangular wave having a fifth predetermined width from the rising edge of the output of the fourth AND circuit, and inputs the output of the fifth rectangular wave generating circuit A third inverting circuit for inverting and outputting the output of the fifth rectangular wave generating circuit, a second control signal input terminal for inputting a control signal, an output of the third inverting circuit and the second inverting circuit. The OR circuit which receives a signal from the control signal input terminal of the above as an input and outputs a result of an OR operation, and receives an output of the fourth AND circuit and an output of the second inverting circuit as inputs and outputs an AND result. A first AND circuit to be output, and an output from the first AND circuit to be input. A fourth rectangular wave generating circuit for generating a rectangular wave of a fourth predetermined width from a rising edge of the output of the first AND circuit; an output of the fourth rectangular wave generating circuit and the third rectangular wave A second AND circuit that receives the output of the generation circuit as an input and outputs a result of the AND operation, and receives the output of the second logic circuit and the output of the first inversion circuit as an input and outputs the result of the AND operation A third logical product circuit, an adder circuit that receives an output of the third logical product circuit and an output of the clamp circuit as inputs, and adds an output of the third logical product circuit to an output signal of the clamp circuit; A maximum value detection circuit that receives an output of the addition circuit as an input and detects a maximum value of an output of the addition circuit, and a comparison circuit that receives an output of the maximum value detection circuit as an input and compares the output with a predetermined DC voltage. An automatic gain control circuit.

An automatic gain control circuit that controls an amplification circuit by an output of a comparison circuit to control a video signal input from an input terminal to a predetermined amplitude and outputs the video signal. The output of the horizontal synchronization signal separation circuit is a second inversion circuit. When the output is less than or equal to the width of the rectangular wave, the fourth rectangular wave generating circuit does not output a rectangular wave, and the outputs of the first rectangular wave generating circuit and the second rectangular wave generating circuit are switched by a switch circuit. When the video recording / reproducing apparatus is in the recording state, the switch circuit selects the output of the first rectangular wave generating circuit, and when a video signal to which a predetermined signal is not added during the vertical blanking period of the video signal is input. A first predetermined amplitude is output, and when a video signal to which a predetermined signal is added during a vertical retrace period of the video signal is input, a second predetermined amplitude is output, and the video recording / reproducing apparatus performs recording. Other than state In this case, the switch circuit selects the output of the second rectangular wave generating circuit, and when a video signal to which no predetermined signal is added is input during the vertical blanking period of the video signal, the first predetermined amplitude is applied. And outputting a first predetermined amplitude even when a video signal to which a predetermined signal is added during a vertical blanking period of the video signal is input.

An automatic gain control circuit that controls a video signal input from an input terminal to a predetermined amplitude by controlling an amplification circuit by an output of a comparison circuit, and that a signal from a second control signal input terminal is a true signal. In this case, the output of the OR circuit is always true and is input to the fourth AND circuit. When the signal from the second control signal input terminal is false, the output of the third inverting circuit is directly output to the fourth AND circuit. And when the input to the second control signal input terminal is false, the output period of the fifth predetermined width rectangular wave is applied to the output of the fourth AND circuit in synchronization with the synchronization signal. Since the output of the separation circuit is not output, the input to the second control signal input terminal becomes false when the video recording / reproducing apparatus is in the recording state, and a predetermined signal is added to the vertical blanking period of the video signal. When no video signal is input, the first predetermined And outputs a second predetermined amplitude when a video signal to which a predetermined signal is added during a vertical blanking period of the video signal is output. When the video recording / reproducing apparatus is in a recording state, the second predetermined amplitude is output. When the input to the control signal input terminal 2 is true and a video signal to which a predetermined signal is not added during the vertical retrace period of the video signal is input, a first predetermined amplitude is output, and An automatic gain control circuit that outputs a first predetermined amplitude even when a video signal to which a predetermined signal is added during a vertical blanking period is input.