JPH0668598A - Device and method for data processing - Google Patents

Abstract

PURPOSE:To greatly reduce the number of seeks and seek time by skipping data between a disk medium and a data buffer for a data transfer based on the output of an address comparator. CONSTITUTION:The data processing device has a first information map constructing means STEP 3 which constructs a first information map which is separated to physically continuous block addresses when a defect sector exists in the sector constructed by a map constructing means STEP 1 and a second information map constructing means which constructs a second information map that is separated to block addresses when a defect sector exists in the sector constructed by the STEP 1. Biased on the STEP 3 and a STEP 4, a writing or a reading to a disk carrier 21 or from the disk carrier 21 is collectively done by letting an alternating sector to seek after skipping the defect sector.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a magnetic disk such as an MO disk.
The present invention relates to a data processing device suitable for reading or writing defect data from a defective sector of an optical disc medium.

[0002]

2. Description of the Related Art Conventionally, two types of processing methods have been adopted for reading out defect data from a defective sector such as an MO disk or writing data into a defect area. That is, since an MO disk medium generally has a lower error rate than a hard disk (HD), a sector slipping algorithm (Sect) is applied to a defective data portion, that is, a defective sector.
or Slipping Algorithm (hereinafter referred to as SSA) as well as Linear Replacement Algorithm (Linear Replaceme)
nt Algorithm: hereinafter referred to as LRA) was used to perform defective sector processing.

If there is a defective sector in the above-mentioned SSA, an algorithm is designed to skip this defective sector and automatically slip the next sector as a substitute sector. Therefore, in most cases, the data transfer rate at the time of writing or reading the data block does not slow down. However, when actually detecting this defective sector, the waveform is lowered at a predetermined position of the sector before the defect portion for each data block of the sector from the computer (hereinafter referred to as CPU), and the next data block may be normal. For example, a hardware-like clock that raises a clock waveform at a predetermined position in the waveform of the defect part is compared with an address waveform from the actual disk medium in software, and a defective sector is detected when both waveforms match. Has been done.

Further, in the case of the above-mentioned LRA method, especially when a replacement area is secured at a specific position of the disk medium, for example, an outer or inner track position, and a defective sector is detected, a replacement sector at this specific position is replaced. Seek to write block data or read block data to add LRA information, and the number of seeks increases as the number of defective sectors increases.

[0005]

According to the SSA method described in the above-mentioned conventional configuration, the writing or reading speed from the CPU is slow when the next sector is set as the alternative sector with respect to the defective sector. Almost no, but this S
The SA method is applied only when the disk is initialized, and no measures can be taken against a defect generated after the initialization, and the sector information of the address data from the disk medium and the defect data from the CPU in the comparator. If the soft comparison time is longer than the sector passage time, the SS is rotated after one rotation
Since the writing or reading mode of A is performed, there is an adverse effect that writing and reading are performed in a state in which the disk is delayed by one rotation.

Further, in the LRA method, it is necessary to secure an alternative sector in the exchange area and seek the head each time a defective sector is detected. If this number of times increases, the data transfer speed becomes slower by the seek to the alternative sector. Of course, it is conceivable to increase the seek speed like HD, but
The seek speed is relatively slow in MO disks and the like, and this seek time becomes a problem.

The present invention has been made in order to solve the above problems, and the purpose thereof is to collectively execute the number of seeks to an alternative sector so that the number of seeks can be minimized. A data processing device and a processing method thereof are provided.

[0008]

DISCLOSURE OF THE INVENTION A data processing apparatus of the present invention is a disk medium capable of reading or writing defect address data for each sector upon receiving a read or write command as shown in FIG. 21
From the disk medium 21 or the disk medium 21
In a data processing device having a system computer 10 for transferring disk data to the data buffer 17 via a data buffer 17, a memory controller 24 for storing the address and length of the data buffer 17 from the system computer 10 and a physical sector from the system computer 10. A register 12 for storing an address and a length,
A disk medium 21 and an address comparator 13 to which an address is supplied from the register 12 are provided, and based on the output of the address comparator 13, data is skipped between the disk medium 21 and the data buffer 17 and transferred. It is a data processing device characterized by comprising.

An example of the data processing method of the present invention is shown in FIG.
As shown in FIG. 3, based on a command from the host computer 22, the system computer 10 writes or reads data from or into the readable disk carrier 21 via the data buffer 17. In the data processing method configured as described above, the map creating means S for creating the physical address of the defective sector of the disk carrier 21 based on the defect map from the logical sector from the host computer 22.
TEP1 and a first information map creating means STEP3 for creating a first information map separated into physically continuous block addresses when there is a defective sector in the sectors created by the map creating means STEP1.
A second information map separated into block addresses when a physically interrupted alternative sector is set at a distant position of the disk carrier 21 when there is a defective sector created by the map creating means STEP1. And a second information map creating means STEP4 for creating the first information mat creating means STEP3.
According to STEP 4 and STEP 4, writing or reading of data to or from the disk carrier 21 is performed collectively by skipping a defective sector and then seeking to an alternative sector. Is.

[0010]

According to the data processing apparatus and the data processing method of the present invention, it is possible to obtain a disk carrier having a large number of defective sectors, in which the seek time can be shortened.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A data processing device and a data processing method according to the present invention will be described below with reference to the drawings. In this example, description will be made on the case of a magnetic optical disk such as a writable or readable MO as a record carrier.

For example, in the case of MO discs, the pre-group and pre-bit formats are defined by the ISO standard, etc. There are two methods, one is the sample servo method (hereinafter referred to as SS method) and the other is. It is a continuous composite method (referred to as other CC method).
The CC method has a header, a guide groove, and a mirror surface portion in the sector,
One sector is 1024 bytes and has 17 sectors / track. In the SS system, a wobble pit is provided at the center of the track, a servo sector has a servo area and a data area, one sector is 512 bytes (logically 1024 bytes possible), and 32 sectors / track are formed. 1
One block consists of 8 bytes. Of course, the sectors are not limited to being formed radially from the center of the disk carrier, but the number of sectors may be different on the inner and outer peripheries.

In this example, the case of using the above-mentioned SS system will be described. First, FIG. 1 shows an overall system diagram of the present invention.

In FIG. 1, the disk carrier 21 is an MO as described above.
Block data is written and read on the disk by the SS method, and its sector structure is as shown in FIG. 4, for example. That is, the disk 21 has the center hole 1
.. 2n spirally provided for sectors 1a, 1b, 1c, 1d ,. The position of the alternative track 4 of the address is defined. The defect track 3 is read when the disk 21 is driven, and the defective address position is known before reading and writing of data.

The defect track 3 and the alternative track 4 can be provided at appropriate positions such as the outer circumference or the inner circumference of the disk 21.

Data is written to the disk carrier 21 from the host computer 22 shown in FIG. 1 or disk data transfer for reading the data read from the disk carrier 21 is performed via the data buffer memory 17. It is done like this.

Reference numeral 10 denotes a system control CPU of the data processing apparatus, which is a system control CPU.
The output of the PU 10 is output via the bus to the memory controller 24.
It is also supplied to the first register 11 including the sector / track register 11A and the length register 11B.

The memory controller 24 is composed of a first address register 19A and a second address register 20A for determining the address of the data buffer memory 17, and a length register 19B and a length counter 20B for determining the same length. Address register 19
The output of the first address register 19 consisting of A and the length register 19B is supplied to the second address register 20 consisting of the second address register 20A and the length counter 20B via the bus and the output of the second address register 20. The output is supplied to the data buffer memory 17 via the bus.

The output of the first register 11B is supplied to a second register 12 including a sector / track register 12A and a length counter 12B.

Writing of data to the disk carrier 21 or reading of data from the disk carrier 21 is performed through a decoder and encoder 18, and a timing controller 15 is connected to the decoder and encoder 18.

From the timing controller 15, the first sector synchronization pulse 15a and the second sector pulse 15
The sector address 15d of the actual disk carrier 21 is output in the same manner as b and the word pulse 15c. The first sector sync pulse 15a and the sector address 15d are supplied to the address comparator 13, the second sector sync pulse 15b is supplied to the length counter 12B, and the word pulse 15c.
Is the length counter 20B in the memory controller 24.
Is supplied to.

The address comparator 13 has a second register 12
The address from the sector / track register 12A of 1 is compared with the actual address of the disk carrier 21, and the SR flip-flop circuit 14 is set by the comparison output. In addition, the SR flip-flop circuit 14 is the second register 12
Is reset by the output of the length counter 12B, and the output of the SR flip-flop circuit 14 outputs the read / write gate signal 14a.
a is supplied to the timing controller 15 in the same manner as the gate circuit 23.

The gate circuit 23 comprises first and second AND gates 23a and 23b. The first and second AND gates 23a and 23b are provided with a read / write switching signal 10 from the system control CPU 10.
a is supplied to each of the positive and negative logics, and the output from the series-parallel conversion circuit 16 is also supplied to the first AND gate 23a. The output of the first AND gate 23a is the same as that of the decoder and encoder 18. It is also supplied to the second AND gate 23b, and the output of the second AND gate 23b is supplied to the series-parallel conversion circuit 16. The serial-parallel conversion circuit 16 is connected to the data buffer memory 17 by a bus.

The operation of the above configuration will be described in detail below with reference to the overall flow charts of FIGS. 2A, 2B, 3C and 3 and the flow chart of the disk data transfer.

In FIG. 2A, the system control CPU 10 of the data processing device receives a command and parameters from the host computer 22 (S1), analyzes the command (S2), and performs a read command (S3), write command (S4). Shows the process of obtaining other commands (Sn).

When the read command (S3) is received, the system control CPU 10 switches the read / write switching signal 10a to the read signal to turn on the second AND gate 23b of the gate circuit 23 to write the data recorded on the disk 21. Readout, encoder / decoder 18 → gate circuit 23 → serial-parallel conversion circuit 16
→ Data buffer memory 17 → Host computer 2
The disk data transfer (ST1) is performed through the second path, the data is transmitted from the data buffer 17 to the host computer (ST2), and the process ends (ST3).

Similarly, when the write command (S4) is received, the system control CPU 10 switches the read / write switching signal 10a to the write signal to turn on the first AND gate 23a of the gate circuit 23, and the data of the host computer 22 is written. Is received by the data buffer memory 17 (ST4), and the data buffer memory 17 → serial-parallel conversion circuit 16 → gate circuit 23
First AND gate 23a → decoder / encoder 1
8 → Disk data transfer via disk 21 (ST
5) is performed and the process ends (ST6).

Such disc data transfer step ST
1 or ST5 is shown in FIG. At the disk data transfer step ST1 or ST5 in FIG. 3, the system control CPU 10 scans the defect track 3 shown in FIG. 4 when the power is turned on with the disk carrier 21 in the drive state, and reads the defective sector peculiar to the disk 21 to make a defect. The map is read and stored in a predetermined memory. Further, the logical sector designated by the command of the host computer 22, for example, the logical sector data block 5 shown in FIG. 5A is converted into a physical data block 6 showing an actual sector of the disk carrier 21 to convert the first and second information. Create a map (STEP 1).

The first information map is the sector / track register 11A and the length register 11 shown in FIG.
The second information map is information supplied to the first register 11 composed of B, and the second information map is information supplied to the memory controller 24 composed of the address register 19A and the length register 19B shown in FIG.

In the second step STEP2, the system control CPU 10 determines whether or not there is a defective sector in the logical sector data block 5 designated by the host computer 22, and if the defective sector is YES, the system control CPU 10 proceeds to the third step STEP3. Go, NO
In this state, the process proceeds to the fifth step STEP5.

In the present example, for convenience of explanation, the logical sector data block 5 is from sector 15 to sector 34 as shown in FIG. 5A, and the physical sector data block 6 is also shown in FIG. 5B.
As shown in, there are sectors 15 to 35, and
The actual defect address of the disk carrier 21 is read from the defect track 3, and this defect is stored in the physical sector data block 6 at addresses 19 and 23.
It is assumed that there are two defect sectors 7a and 7b indicated by. Further, the defect sector 7a is in charge of SSA, the defect sector 7b corresponds to LRA, and the defect sector 7b is converted into the address indicated by the physical sector 99 of the alternative track 4 shown in FIG.
Proceed with the explanation.

In the third step STEP3, the first information map divided into physically consecutive sectors is recreated in the system control CPU 10. This first information map is for the first and second registers 11 and 12 and is the sector / track register 11A of the first register 11.
Is supplied to the length register 11B.

In the case of the sector data blocks shown in FIGS. 5A and 5B described above, physically continuous reproduction of the sector data blocks is performed as shown in FIG. 6A.

That is, as shown in FIG. 6A, the first block is the start sector data block 15 shown in FIG. 5B, the track / sector = 15, the length = 4, and the sector data block 18 is the first block. 1
Assuming that the sector is usually 512 bytes, the length = 4 is 512 bytes × 4 = 2048 bytes.

Thereafter, the second block is the blocks 20 to 23 shown in FIG. 5B, and the block 19 of the SSA is skipped so that track / sector = 20 and length = 3.
Similarly, the block 23 of the LRA is skipped, and the blocks 24 to 35 have a track / sector = 24 and a length of 12. In the fourth block, the sector 99 on the alternative track 4 corresponding to the LRA block 23 of the defective sector which is the subject matter of the present invention is selected. Ie track /
Sector = 99, length = 1, and at this time, the write / read heads seek-moved to the position of the alternative track 4 collectively write / read the alternative sector of the defective sector.

In the fourth step STEP4, when the alternative sector of the physically interrupted sector is assigned to the distant position as shown in FIG. 4, the second information map for controlling the memory buffer is recreated based on it. .

That is, as shown in the map example in FIG. 6B, the start address 1000 (h) of the first sector data block 15 shown in FIG. 5B is taken for the first block, and the length corresponds to the sector data block 15 to LRA. SS of 15 to 22 up to sector data block 23
Blocks A of A were removed 15, 16, 17, 18,
Total of 7 blocks, that is, 15 to 21 (refer to the data buffer memory map in FIG. 7) of 20, 21, and 22, ie, 51
2 (1 sector × 7 = 3587 bytes, which is the hexadecimal display E00 (h)) bytes.

Similarly, the second block is the data block 2
Although the LRA portion of 3 is removed and there are data blocks 24 to 35, the LRA data block is 22 as shown in FIG. 7 on the map of the data buffer memory 17,
The address is 2000, which is the start position of block 23.
(H). Further, the length is 512 × 124 = 1800 (h) in 12 blocks of blocks 23 to 34.

Further, in the third block, since reading and writing are performed last in time after the address 3800 (h) of the block 34 is reached, the block 2 of the LRA is
It is returned to the first address 1E00 (h) of 2. That is, a seek operation is performed. Also, the length is 200 for the block.
(H) will be taken.

Based on the second and first information maps recreated in this way, the system control CPU 10 sends the second information to the memory controller 24 by the fifth and sixth steps STEP5 and STEP6. It is set in the first register 11.

Next, in the seventh step STEP7, reading and writing are executed.

This reading and writing drives the magnetic or optical head based on the first and second information maps of FIGS. 6A and 6B. That is, the movement of the driver performs the read / write of (1) to (8) as shown by the broken line in FIG. 3 and sees if it is finished in the eighth step STEP8. If it is not finished, it is returned to the fifth step STEP5. If so, the process returns to the ninth step STEP9.

The case where the reading and writing procedure in the above case is performed by software has been described. The operation of the hardware configuration will be described below with reference to FIGS. 1 and 5.

In FIG. 1, the system control CPU 10
Is the address 10 of the data buffer memory 17 shown in FIG.
00 (h) and the length E0 of the logical sectors 15 to 27
0 (h) is set in the address register 19A and the length register 19B of the memory controller 24.

If the second address register 20 consisting of the address register 20A and the length counter 20B of the next stage in the memory controller 24 is empty, the address register 19A and the length register 19B of the first address register 19 are used. The set address value and length value are immediately transferred to the second address register 20.

Thereafter, the address value of the address register 20A is incremented by 1 and the count value of the length counter 20B is decremented by -1 by the word pulse signal 15c from the timing controller 15 (see FIG. 5F), and the length value of the length counter 20B becomes zero. If the address value and the length value are already set in the address register 19A and the length register 19B, the address value and the length value of the first address register 20 are immediately moved to the second address register 20 side and the same operation is performed thereafter. Will be repeated.

The system control CPU 10 sets the address and length to the memory controller 24 and simultaneously sets the physical sector address (see FIGS. 5B and 7) 15 and the length in the sector / track register 11A and the length register 11B of the first register 11. As 15
Set 4 from sector to 18 sectors.

If the second register 12 of the next stage is empty, the sector / track register 11A of the first register
The physical sector address value and the length value of the length register 11B immediately move to the second register 12 side, and the physical sector address value of the second register 12 is input to the address comparator 13. Further, since the disk carrier 21 is recorded by the SS system, the address value of the unique disk is the decoder / encoder 18, the timing controller 15
From the physical sector address 15d to the address comparator 1
3 is supplied to perform address comparison operation.

That is, at the moment when the first sector sync pulse 15a shown in FIG. 5C from the timing controller 15 becomes active, when the two address values supplied to the address comparator 13 match, the RS which constitutes the gate controller is formed. A flip-flop circuit (hereinafter referred to as FF) 14 is set.

After that, the length value of the length counter 12B in the second register 12 is decremented by -1 by the second sector synchronization pulse 15b shown in FIG. 5D from the timing controller 15.

When the length value is set to zero, the FF 14 is reset. If the next address value and length value have already been set in the first register 11, they are immediately moved to the second register 12, and the same operation is repeated thereafter.

When the FF14 of the gate controller is set, the read and write gate signal 14a becomes active from the FF14, and the data on the disk carrier 21 is synchronized with the word pulse 15c, and the decoder / encoder 18 and the serial-parallel conversion circuit. Data transfer between the data buffer memories 17 through 16 is performed through the gate circuit 23. Data transfer is performed until the FF 14 is reset and the read and write gate signal 14a becomes inactive.

The read / write procedure of such a data block will be described with reference to the data block of the physical sector of FIG.
The data buffer memory map will be specifically described.

First, the system control CPU 10
Is the start logical address value 1000 as shown in FIG.
(H) and length of sectors 15 to 21 = E00
(H) is set in the address register 19A and the length register 19B.

Simultaneously with these operations, the CPU 10 makes the sector / track register 11A constituting the first register 11
Then, the physical sector address 15 and the length 4 (for the physical sector addresses 15 to 18 shown in FIG. 5B) are set in the length register 11B. Logical sector address 19
Is automatically moved to the physical sector address 20 by SSA and the sector is skipped. Next, the CPU 10 sets the physical sector address 20 and the register 23 (the physical sector addresses 20 to 22 shown in FIG. 5B) in the sector / track register 11A and the length register 11B.

The next physical sector 23 is a defective sector and is LRA.
However, since the sector 7b of the alternative track 4 is located at a distant position, the CPU 10 has the first register 11 and the first register 11
Of the logical sector address 22 (alternative sector 7b) is confirmed by confirming that the address register 19 is empty.
As shown in FIG. 7, the address 2000 of the logical sector 23
(H) and length 1800 (h) (logical sectors 23 to 3
4) are set in the address register 19A and the length register 19B, and the sector / track register 11A and the length register 1 of the first register 11 are set.
The physical sector address 24 and the length 12 (for physical sectors 24 to 35) shown in FIG. 5B are set in 1B.

After confirming that the above-mentioned setting has been completed, the CPU 10 seeks the head near the sector 99 of the alternative track 4.

After the seek is completed, the CPU 10 causes the first address register 19 to skip the recording sector 2 as shown in FIG.
2 address 1E00 (h) and length 200 (h) (for the logical sector 22) are set, and at the same time, the physical sector address 99 and length 1 are set in the first register 11, and the second sector shown in FIGS. Sector sync pulse 15b '
Then, the last data transfer is performed by the read / write gate signal 14a '.

That is, also with the above configuration, the address value and the length value of the data buffer memory 17 are set in advance in the address register 19A and the length register 19B of the memory controller 24, and the first register 1 is also used.
Since the physical sector address value and the length value can be set in advance in one sector / track register 11A and length register 11B, it is possible to skip one sector and disturb the address in the data buffer memory 17. In the final state, it is possible to collectively seek to the alternative tracks, and the seek time is shortened as the number of defective sectors increases.

[0060]

According to the data processing apparatus and the data processing method of the present invention, in the case of the LRA, when there are alternative sectors at positions far apart, in order to scan the alternative tracks collectively at the end, each defective sector is scanned. It has become possible to greatly reduce the number of seeks compared to seeking to. Furthermore S
Even in the case of SA, it is possible to obtain one in which the scan to the next sector is not made in time and the scan is not performed after one rotation.

[Brief description of drawings]

FIG. 1 is a system diagram of a data processing device (method) of the present invention.

FIG. 2 is an overall flow chart of a data processing device (method) of the present invention.

FIG. 3 is a flowchart of disk data transfer of the data processing device (method) of the present invention.

FIG. 4 is an explanatory diagram of sectors of a disk carrier used in the present invention.

FIG. 5 is an explanatory diagram of a sector data block and waveform of a data processing device (method) according to the present invention.

FIG. 6 is a first example used in the data processing method (apparatus) of the present invention.
6 is a second information map example.

FIG. 7 is a data buffer memory map used in the data processing method (apparatus) of the present invention.

[Explanation of symbols]

 10 System Control CPU 11A, 12A Sector / Track Register 11B, 19B Length Register 12B, 20B Length Counter 17 Data Buffer Memory 19A, 20A Address Register 22 Host Computer

Claims (2)

[Claims] 1. A disk medium capable of reading or writing defect address data for each sector in response to a read or write command, and a system computer for transferring disk data from or to the disk medium via a data buffer. In a data processing device having: a memory controller for storing an address and a length of the data buffer from the system computer; a register for storing a physical sector address and a length from the system computer; and a disk medium and the register. And an address comparator to which the address is supplied, and based on the output of the address comparator, data is skipped between the disk medium and the data buffer for transfer. The data processing apparatus according to claim. 2. A disk processing adapted to write data to a readable disk carrier or read data from the disk carrier by a system computer based on a command from a host computer. In the method, based on the defect map from the logical sector from the host computer, a map creating means for creating a physical address of a defective sector of the disk alone, and a defect sector in the sector created by the map creating means. In the case where there is a defect sector in the sectors created by the first information map creating means for creating a first information map separated into physically continuous block addresses, Physically interrupted alternative sectors are A second information map creating means for creating a second information map separated into block addresses when the carrier is set at a distant position, and the first and second information map creating means are provided. On the basis of the above, a data processing method is characterized in that data is written into or read from the disk carrier by skipping a defect sector and then seeks to the alternative sector in a batch.