JPH06332842A - Direct memory access control circuit - Google Patents

Abstract

PURPOSE:To simultaneously perform read from a transfer origin and write to a transfer destination and to accelerate transfer from a memory to a memory by letting an address generation unit for generating the address of the transfer origin and the address generation unit for generating the address of the transfer destination become independent. CONSTITUTION:This direct memory access control circuit 1 is provided with a first address generation unit 9 for performing output to a first bus 2 connected to a first memory 5, a second address generation unit 10 for performing the output to a second bus 3 connected to a second memory 7, a bus control unit 13 for performing interface with the first bus 2 and the second bus 3 and a DMA control unit 12 for starting/stopping a DMA counting unit 11 for counting the number of times of direct memory access or the like. Then, the actual direct memory access control circuit 1 capable of simultaneously performing the read from the memory and the write to the memory is constituted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a direct memory access / control circuit for directly accessing a memory or an I / O device without going through a CPU, and particularly when performing a DMA (Direct Memory Access) transfer from the memory to the memory. It is related to the one aiming at speeding up.

[0002]

2. Description of the Related Art FIG. 4 shows, for example, 1989 by NEC Corporation.
FIG. 6 is a block diagram of a conventional direct memory access control circuit shown on pages 233 to 273 of a user's manual “V series peripheral LSI” issued in November, 2014. In the figure, 13 is a bus control unit for controlling an address bus, a data bus and a control bus, and an address bus buffer 21 for inputting / outputting an address signal and a data bus for inputting / outputting a data signal. It is composed of a bus buffer 22 and a bus control logic 23 for controlling the bus, and interfaces with a bus to which a CPU, a memory and the like are connected. 9 is an address incrementer that increases / decreases the address value for each DMA transfer.
An address generation unit including a decrementer 24 and an address register 25 that holds a DMA address signal.
Give an address. The address register 25 of the address generation unit 9 is composed of a base register 25a in which a starting point of a desired DMA address value is set and a current register 25b in which a current DMA address value obtained by increasing or decreasing the starting point is set. Reference numeral 12 is a DMA control unit for controlling activation and termination of direct memory access, which is a priority control logic 1 for designating one of four independent DMA channels.
21 and a timing control logic 122 for exchanging the CPU's stop and its acknowledge with the CPU by starting the DMA. Reference numeral 11 is a DMA count unit that counts the number of direct memory access transfers, and is a count register including a base register 111a in which a desired number of bytes of data to be transferred is set and a current register 111b in which a current count value is set. 111 and a count decrementer 112 that counts down the count value by "1".

Numeral 8 indicates this direct memory access
A plurality of control registers 81 for controlling the control circuit
Is a control register group consisting of ˜87, 81 is a channel register for selecting one of four DMA channels, and 82 is a device, that is, this direct register.
A device control register for controlling the memory access / control circuit, 83 a status register indicating the state of the direct memory access / control circuit, and 84 controlling an operation mode of the direct memory access / control circuit. Mode control register, 85 is a temporary register used for temporarily storing data when performing memory-memory transfer, that is, DMA transfer between memories, 86 is a request register indicating the status of a DMA request, 87 Which DMA
It is a mask register for setting whether or not to execute channel DMA transfer.

Next, the operation will be described. Using this direct memory access control circuit, I
When transferring data to the I / O device, the DMA control unit 12 requests the CPU to use the bus HL.
Output DRQ14 to request bus usage. The bus use request is accepted, and the CPU permits bus use HLDAK1
When 5 is input, the address generation unit 9 outputs the address of the data transfer source to the bus control unit 13
Output to. The bus control unit 13 reads the data written in the address given from the address generator 9 from the memory and outputs the DMA acknowledge signal DMAAK as the chip select signal, whereby the data is output from the memory. At the same time, this data is transferred to the I / O device connected on the same bus.

When data is transferred from one memory to another memory using this direct memory access control circuit, the DMA control unit 12
Outputs a bus use request HLRQ14 to the CPU to request the use of the bus. Bus use request is accepted, C
When the bus use permission HLDAK15 is input from PU,
The address generation unit 9 outputs the address of the data transfer source to the bus control unit 13. bus·
The control unit 13 reads out the data written in the address given from the address generator 9 and writes it in the temporary register 85 inside the control register group 8.

Next, the address generation unit 9 updates the transfer destination address and outputs the transfer destination address to the bus control unit 13. The bus control unit 13 uses the control register group 8 at the address given by the address generation unit 9.
The data written in the temporary register 85 inside is written. When this writing is completed, the address generation unit 9 updates the transfer source address.
This completes one direct memory access.

[0007]

Since the conventional direct memory access control circuit is constructed as described above, it takes time to read and decode instructions as compared with the case of transferring data via the CPU. Is unnecessary, and the time required for data transfer can be shortened. At this time, when performing a DMA transfer between the I / O device and the memory, it is not necessary to perform the address decoding to access the I / O device. Therefore, the read cycle and the write cycle can be executed in the same cycle. When performing a DMA transfer from the memory to the memory, the data is once transferred through the temporary register, and therefore one transfer requires two bus cycles of reading and writing the data.

Therefore, if the conventional direct memory access control circuit is applied to a field requiring real-time processing, it takes a lot of time to transfer data in the memory-memory transfer, which makes its use difficult. There is a problem that it may become.

The present invention has been made in order to solve the above problems, and enables direct memory access transfer to be further speeded up when data is transferred from memory to memory. -To provide a memory access / control circuit.

[0010]

The direct memory access control circuit according to the present invention has two address generation units so that reading and writing of the memory are performed in the same bus cycle, thereby achieving high-speed transfer. It is designed to be converted.

Further, the direct memory access control circuit according to the present invention is the direct memory access control circuit, wherein the first memory is connected to the first memory.
First address generation unit for generating an address to be sent to the second bus, a second address generation unit for generating an address to be output to the second bus to which the second memory is connected, the first bus, the second It has a bus control unit that interfaces with other buses, a DMA count unit that counts the number of direct memory accesses, and a DMA control unit that starts and stops direct memory access. It is a thing.

Also, the direct memory access control circuit according to the present invention generates an address to be sent to the first bus to which the first and second memories are connected in the direct memory access control circuit. A first address generating unit, a second address generating unit for generating an address to be output to the second bus, the first bus,
A bus control unit for interfacing with a second bus, a DMA count unit for counting the number of times of direct memory access, a DMA control unit for starting and stopping direct memory access, and a first Is arranged between the second bus and the second memory and normally connects all the signal lines of the first bus and the second memory. However, when the memory-memory transfer is started, the data is transferred. Regarding the signal lines, the first bus and the second memory are still connected, but for signals other than the data signal lines such as address signal lines, the second bus is connected to the second memory instead of the first bus. It is equipped with a bus / switch that switches so as to switch.

Further, the direct memory access control circuit according to the present invention generates the address to be sent to the first bus to which the first and second memories are connected.
Address generation unit, a second address generation unit for generating an address to be sent to the second bus, a bus control unit for interfacing with the first bus and the second bus, and a direct memory access DMA count unit that counts the number of times, DMA that starts and stops direct memory access
An I / O-memory transfer control circuit having a control unit, and an external address generation unit arranged between the first bus and the second memory outside the I / O-memory transfer control circuit The external address generation unit normally connects the first bus and the second memory, and when the memory-memory transfer is started, the signal line output to the second memory is output. Disconnecting the address signal line and the control signal line in the first bus from the first bus and connecting the address signal and the control signal line for outputting the address signal and the control signal generated by itself to the second memory,
At this time, the data signal of the second memory and the data signal of the first bus are kept connected.

[0014]

According to the present invention, one of the two address generation units generates the address of the transfer source and the other generates the address of the transfer destination, so that the read from the memory and the write to the memory are simultaneously performed. Is possible.

Further, in the present invention, the direct
In a memory access / control circuit, a first address generation unit for generating an address to be sent to a first bus to which a first memory is connected, and an address to be output to a second bus to which a second memory is connected A second address generation unit for generating, a bus control unit for interfacing with the first bus and the second bus, and a DM for counting the number of direct memory accesses.
By including an A count unit and a DMA control unit that starts and stops direct memory access, it is possible to read from memory and write to memory at the same time.
A configuration of a memory access / control circuit can be provided.

Further, in the present invention, the direct
In the memory access / control circuit, the first bus and the second memory are normally connected, but when the memory-memory transfer is started, the second signal is applied to the data signal line of the first bus. Address signal line, etc.
Regarding signals other than the data signal line, the bus / switch for switching the second bus to connect to the second memory is provided, so that the signals are the same not between the memories connected to two different buses. DM between memories connected to the bus
A transfer can be performed at high speed.

Further, in the present invention, a first address generation unit for generating an address for sending the direct memory access control circuit to the first bus to which the first and second memories are connected, A second address generation unit that generates an address to be sent to the first bus, a bus control unit that interfaces with the first bus and the second bus, and a direct memory
In addition to the I / O-memory transfer control circuit having a DMA count unit that counts the number of accesses and a DMA control unit that activates / stops direct memory access, normally, the All signal lines are connected to the second memory, and during memory-memory transfer, address signal lines and control signal lines among the signal lines output to the second memory are disconnected from the first bus An external address generation unit that connects the address signal line and the control signal line generated and output by itself to the second memory and keeps the data signal line of the second memory and the data signal line of the first bus connected. I decided to install it, so memory
A memory-memory transfer control circuit having a function capable of executing memory-memory DMA transfer control in one bus cycle by using an I / O-memory transfer control circuit requiring two bus cycles for memory DMA transfer control Easy to implement.

[0018]

【Example】

Example 1. An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a direct memory access control circuit according to an embodiment of the present invention. In the figure, 1 is a direct memory access / control circuit, which is a bus 1
(2), the bus 2 (3), and the bus arbitration circuit 4. The memory 1 (5) and the bus buffer 6 are connected to the bus 1 (2). Memory 2 on bus 2 (3)
(7) The bus buffer 6 is connected. Reference numeral 8 is a register group that controls the operation of the direct memory access control circuit 1, 9 is an address generation unit 1 that generates an address to be sent to the bus 1 (2), and 10 is a bus 2 (3). An address generation unit 2 that generates an output address, 11 is a DMA count unit that counts the number of direct memory accesses, and 12 is a direct memory access start-up unit.
It is a DMA control unit for stopping, 1
A bus control unit 3 interfaces with the bus 1 (2) and the bus 2 (3). These register group 8, address generation unit 1 (9), address generation unit 2 (10), DMA count unit 1
The direct memory access control circuit 1 is composed of the 1, DMA control unit 12 and bus control unit 13.

Next, the operation will be described. Memory 1
When transferring from (5) to the memory 2 (7), the DMA control unit 12 outputs a bus use request HLRQ14 to the bus arbitration circuit 4. The bus arbitration circuit 4 controls the bus buffer 6 to control the bus 1 (2) and the bus 2
The data bus of (3) is connected, and the fact that the bus usage right has been obtained is output to the direct memory access control circuit 1 by outputting the bus usage permission HLDAK15. The direct memory access control circuit 1 which has obtained permission to use the bus causes the address generation unit 1 (9) to generate a transfer source address and the address generation unit 2 (10) to generate a transfer destination address.・ Bus 1 (2), Bus 2 (3) through Unit 13
Output to each. Bus control unit 1
The memory 3 executes the read cycle for the memory 1 (5) and simultaneously causes the memory 2 (7) for the write cycle.

At this time, since the data buses of the bus 1 (2) and the bus 2 (3) are connected by the bus buffer 6, the data read from the memory 1 (5) is stored in the memory 2 (7). Written and memory-memory transfers can be performed. When one transfer is completed in this way, the address generation unit 1 (9) and the address generation unit 2 (1
0) and the DMA count unit (11) are updated and ready for the next transfer.

As described above, according to the above-described embodiment, two address generating units are provided to perform the memory-memory transfer, and the source address and the destination address are simultaneously generated by the two address generating units. Therefore, like the conventional direct memory access control circuit that has only one system of address line, the data transferred from the external bus is temporarily stored in the temporary register in the DMA control circuit and stored in the external bus. There is no need to transfer data, data read cycles and write cycles can be performed in parallel, and data read and write between two memories can be executed simultaneously.

Example 2. Further, in the above-described first embodiment, the case of performing the transfer between the memories connected to the two different buses has been described, but in order to perform the transfer between the memories connected to the same bus, as shown in FIG. Further, instead of the bus buffer 6 of FIG. 1, the bus switcher 16 may be used.

That is, in FIG. 2 showing the second embodiment of the present invention, the bus / switch 16 normally connects the bus 1 (2) and the memory 2 (7) with respect to all the signal lines. However, when the memory-memory transfer is started, the output of the bus arbitration circuit 4 causes the data signal line to be the bus 1
For signals other than the data signal line such as address signals, the bus 2 of (2) remains connected to the memory 2 (7).
The signal line of (3) is connected to the memory 2 (7).

By performing such switching, transfer between memories connected to the same bus can be normally performed in the same manner as in the first embodiment, and a write cycle and a read cycle are executed simultaneously. As a result, the DMA transfer of data between memories can be performed at high speed.

Example 3. Further, in the above-described first and second embodiments, the two address generation units are both incorporated in the direct memory access control circuit, and the addresses are given to the memory via the bus control unit. Even in a direct memory access control circuit having only one generation unit, a high-speed memory similar to that in the above-described first and second embodiments can be obtained by additionally adding an address generation unit to the outside thereof. Memory transfer can be realized.

That is, in FIG. 3 showing the third embodiment of the present invention, reference numeral 17 denotes an I / O-which transfers data between the I / O and the memory.
This is a memory transfer control circuit, which has only one address generation unit 9 therein, like the conventional direct memory access control circuit shown in FIG.
For DMA transfer between / O-memory,
Can be executed in cycles, but DM between memory
Two bus cycles are required for A transfer. Reference numeral 18 denotes an external address generation unit externally attached to the I / O-memory transfer control circuit 17, which is a register having a bit number equal to the address width, a signal line switcher, and some registers for interfacing with the CPU. The bus 1 (3) is normally connected to the memory 2 (7), but when direct memory access is started, one of the signal lines output to the memory 2 (7) is The address signal line and the control signal line are cut off from the bus 1 (3), and the address signal and the control signal generated by the external address generation unit 18 themselves are output to the memory 2 (7).
At this time, the data signal of the memory 2 (7) and the bus 1
The data signal of (3) remains connected. In the present embodiment, the I / O-memory transfer control circuit 17 and the external address generation unit 18 are used for direct memory
The access control circuit 1 is configured.

Next, the operation will be described. C not shown
Direct memory from memory to memory by PU
When the access is activated, the external address generation unit 18 sends a direct command to the I / O-memory transfer control circuit 17.
The memory access request DMARQ19 is output. I /
Upon receiving the direct memory access request 19, the O-memory transfer control circuit 17 outputs a bus use request HLDRQ 14 to the bus arbitration circuit 4. When the bus arbitration circuit 4 receives the bus use request HLDAK 19, it arbitrates the bus and then outputs the bus use permission 15 to the I / O-memory transfer control circuit 17 to output the I / O-memory transfer control circuit 1.
Give bus usage rights to 7. The I / O-memory transfer control circuit 17, which has received the bus use permission 15, outputs the direct memory access permission DMAAK 20 to the external address generation unit 18, and starts the direct memory access.

By receiving the direct memory access permission DMAAK 20, the external address generation unit 18 knows that the direct memory access is started, and selects one of the signal lines output to the memory 2 (7). The address signal line and the control signal line are cut off from the bus 1 (3), and the address signal line generated by the external address generation unit 18 itself and the address signal line transmitting the control signal are transmitted.
The control signal line is connected to the memory 2 (7). Therefore, the memory 1 (5) is supplied with the address signal and the control signal output from the I / O-memory transfer control circuit 17, and the memory 2
An address signal and a control signal generated by the external address generation unit 18 are given to (7). Also, memory 1
The data signal line of (5) and the data signal line of the memory 2 (7) are still connected via the bus 3.

The control signal output from the external address generation unit 18 is such that a write cycle is generated when the I / O-memory transfer control circuit 17 generates a read cycle, and a read cycle is generated when the write cycle is generated. Set to. Therefore, memory 1 (5) and memory 2
Data can be transferred at high speed during (7).

By configuring the direct memory access control circuit as described above, the direct memory access control circuit can execute only the direct memory access function between the I / O and the memory in one cycle. A memory-memory transfer control circuit that can execute DMA transfer between memories at high speed in one cycle can be configured by adding an external address generation circuit that can be realized by a few circuits, and this circuit Can be realized easily and inexpensively.

[0031]

As described above, according to the direct memory access control circuit of the present invention, the address generation unit for generating the transfer source address and the address generation unit for generating the transfer destination address are provided. By making them independent, it is possible to simultaneously read from the transfer source and write to the transfer destination, and it is possible to speed up the transfer from memory to memory.

According to the direct memory access control circuit of the present invention, the direct memory access
In the access / control circuit, a first address generation unit that generates an address to be sent to the first bus connected to the first memory, and an address to be output to the second bus connected to the second memory A second address generating unit, a bus control unit for interfacing with the first and second buses, a DMA count unit for counting the number of direct memory accesses, and a direct memory access Since a DMA control unit for starting / stopping the memory is provided, it is possible to provide an actual direct memory access / control circuit configuration capable of simultaneously reading from and writing to the memory. There is.

According to the direct memory access control circuit of the present invention, the direct memory
In the access / control circuit, the first for generating an address to be sent to the first bus to which the first and second memories are connected
Address generation unit, a second address generation unit that generates an address to be output to the second bus, a bus control unit that interfaces with the first bus and the second bus, and a direct memory access DMA count unit that counts the number of times, DMA that starts and stops direct memory access
-Allocated between the control unit and the first bus and the second memory, usually connecting all the signal lines of the first bus and the second memory, but memory-memory transfer Is started, the first bus and the second memory are still connected for the data signal line, and the second bus is used instead of the first bus for signals such as address signal lines other than the data signal line. Since a bus / switch that switches to connect to the second memory is provided, not the high-speed transfer between the memories connected to two different buses, but the DMA transfer between the memories connected to the same bus. The effect is that it can be performed at high speed.

Further, according to the direct memory access control circuit of the present invention, the first address generation unit for generating the address to be transmitted to the first bus to which the first and second memories are connected, A second address generation unit for generating an address to be sent to the second bus, the first bus, a bus control unit for interfacing with the second bus, and a DMA for counting the number of direct memory accesses. An I / O-memory transfer control circuit having a count unit and a DMA control unit for starting and stopping direct memory access, and a first bus outside the I / O-memory transfer control circuit The external address generation unit is provided between the second memory and the external address generation unit. Knit, usually the first of the bus the second
When the memory-memory transfer is started, the address signal line and the control signal line of the signal lines output to the second memory are disconnected from the first bus. , The address signal generated by itself, the address signal line for outputting the control signal, and the control signal line are connected to the second memory. At this time, the data signal of the second memory and the data signal of the first bus are Since the connection is maintained, the DMA transfer between the memory and the memory can be performed only by adding a few circuits to the I / O-memory transfer control circuit which requires two bus cycles for the memory-memory DMA transfer control. This has an effect of easily realizing a memory-memory transfer control circuit having a function of executing control in one bus cycle.

[Brief description of drawings]

FIG. 1 is a functional block diagram showing a direct memory access / control circuit according to a first embodiment of the present invention.

FIG. 2 is a functional block diagram showing a direct memory access / control circuit according to a second embodiment of the present invention.

FIG. 3 is a functional block diagram showing a direct memory access control circuit according to a third embodiment of the present invention.

FIG. 4 is a functional block diagram of a conventional direct memory access control circuit.

[Explanation of symbols]

 1 direct memory access control circuit 2 bus 1 3 bus 2 4 bus arbitration circuit 5 memory 1 6 bus buffer 7 memory 2 8 register group 9 address generation unit 1 10 address generation unit 2 11 DMA count unit 12 DMA control unit 13 bus control unit 14 bus use request 15 bus use permission 16 bus switcher 17 I / O-memory transfer control circuit 18 external address generation unit 19 direct memory access request 20 direct memory access permission 21 address Bus buffer 22 Data bus buffer 23 Bus control unit 24 Address incrementer / decrementer 25 Address register 85 Temporary register

Claims (4)

[Claims] 1. A direct memory access control circuit capable of directly transferring data from memory to memory, comprising two address generation units for simultaneously generating a transfer destination address and a transfer source address. Direct memory access control circuit featuring. 2. A direct memory access control circuit capable of directly transferring data from memory to memory, the first memory generating an address to be transmitted to a first bus to which the first memory is connected. An address generation unit, a second address generation unit that generates an address to be output to a second bus to which a second memory is connected, and a bus control that interfaces with the first bus and the second bus. .Unit and D that counts the number of direct memory accesses
MA count unit and DM for starting / stopping direct memory access
A direct memory access control circuit characterized by comprising an A control unit. 3. A direct memory access control circuit capable of directly transferring data from memory to memory, for generating an address to be sent to a first bus to which first and second memories are connected. A first address generation unit, a second address generation unit that generates an address to be output to the second bus, a bus control unit that interfaces with the first bus and the second bus, and .D that counts the number of memory accesses
MA count unit and DM for starting / stopping direct memory access
An A control unit is provided between the first bus and the second memory,
Normally, all the signal lines of the first bus are connected to the second memory, and during the memory-memory transfer, the connection between the first bus and the second memory is maintained for the data signal line. For a signal other than the data signal line, a direct memory including a bus / switch for switching the second bus so as to connect to the second memory.
Access / control circuit. 4. A direct memory access control circuit capable of directly transferring data from memory to memory, for generating an address to be sent to a first bus to which first and second memories are connected. A first address generation unit, a second address generation unit that generates an address to be output to the second bus, a bus control unit that interfaces with the first bus and the second bus, and .D that counts the number of memory accesses
MA count unit and DM for starting / stopping direct memory access
An I / O-memory transfer control circuit having an A. control unit, and the first external unit of the I / O-memory transfer control circuit.
External address generation unit arranged between the second memory and the second memory, and the external address generation unit normally connects all the signal lines of the first bus to the second memory. When the memory-memory transfer is performed, the address signal line and the control signal line among the signal lines output to the second memory are connected to the first
The address signal line and the control signal line which are cut off from the bus and are generated and output by themselves are connected to the second memory, and the data signal line of the second memory and the data signal line of the first bus are connected. Direct memory access control circuit characterized by being left as it is.