JPH0630081B2 - Communication control circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing circuit having a memory, and more particularly to a communication control circuit that realizes a DMA (Direct Memory Access) function.

“Prior Art” FIG. 2 is a block diagram of a conventional data processing circuit 100.
In this figure, reference numeral 1 is an ALU (arithmetic unit), which does not have a function of managing an empty state of the bus, but has a general arithmetic function. 2 is a readable and writable memory. Reference numeral 3 denotes a DMA controller, which outputs a control signal to each section of the circuit in response to an external DMA request and controls input / output of external data to / from the memory 2. 4 is D
It is an MA control register and has a control bit RQ that is set when there is a DMA request and a control bit AK that indicates whether or not a DMA operation is currently in progress. A
A data bus DB and an address bus AB are wired between the LU 1, the memory 2 and the DMA controller 3. Addressing in the memory 2 is performed by the address data on the address bus AB. Then, data is input and output between the memory 2 and the ALU 1 or between the memory 2 and the external memory through the DMA controller 3 via the data bus DB. Also, address bus A
A switch SW is provided in the middle of B and the data bus DB, and the ALU 1 can input / output data to / from the memory 2 when the switch SW is in the ON state.

Next, the operation of the data processing circuit 100 will be described. In the normal operation mode, the control bits RQ and AK of the DMA control register are "0". Further, since the control bit AK is "0", the switch SW is turned on.
In this state, the ALU 1 is connected to the memory 2 via the address bus AB and the data bus DB. Therefore, in this state, the ALU 1 can input / output data to / from the memory 2.

Next, when the DMA request signal HLDRQ is input to the DMA controller 3 from the outside, the control bit RQ of the DMA control register 4 is set by the DMA controller 3. Then, the setting of the control bit RQ is detected by the ALU1, and when the ALU1 is not using the memory, the ALU1 sets the control bit AK. As a result, the control bit AK becomes "1", so that the switch SW is turned off and ALU1
Is separated from the memory 2. Further, the setting of the control bit AK is detected by the DMA controller 3. Then, the DMA controller 3 outputs a DMA permission signal HLDAK indicating that the DMA is executable. Then, the DMA operation is executed as described below.

When writing external data to the memory 2, the DMA controller 3 reads data from an external memory (not shown) and outputs the data to the data bus DB. At this time, the write destination address is supplied to the memory 2 via the address bus AB under the control of the DMA controller 3. Then, the data on the data bus DB is written to the designated write destination in the memory 2. On the other hand, when reading data from the memory 2 and writing it to the external storage,
The read destination address is supplied from the DMA controller 3 to the memory 2 via the address bus AB. Then, the data of the specified address in the memory 2 is transferred to the data bus D.
Is output on B. Then, this data is read under the control of the DMA controller 3 and written in the external memory.

Then, when the above-described DMA operation is completed, the DMA controller 3 resets the control bit AK of the DMA control register 4. As a result, the switch SW turns off.
The N state is established and the ALU 1 is connected to the memory 2. Then, the ALU 1 can input / output data to / from the memory 2.

"Problems to be Solved by the Invention" In the conventional data processing circuit described above, since the memory 2 is separated from the ALU 1 during the DMA operation, the ALU 1 cannot access the memory 2,
The process cannot proceed until the DMA operation is completed,
Therefore, there is a problem that it is not suitable for application to a communication control circuit or the like.

The present invention has been made in view of the above-mentioned circumstances.
It is an object of the present invention to provide a communication control circuit that allows an ALU to access a memory and proceed with processing even during A operation.

"Means for Solving the Problem" A communication control circuit according to the present invention includes an arithmetic processing circuit, an internal storage circuit, a system bus, a DMA dedicated bus, and a DMA.
A communication control circuit having a controller and a transmitting / receiving means, wherein the arithmetic processing circuit is connected to the internal storage circuit via the system bus, and the transmitting / receiving means transmits / receives data to / from an external device. In the normal operation, the DMA controller connects the system bus to the transmitting / receiving means, and when a DMA transfer request is issued from a host device, the storage device of the host device is accessed via the DMA dedicated bus. It is connected to the transmission / reception means and controls the DMA transfer between the external device and the storage device of the host device via the DMA dedicated bus and the transmission / reception means.

[Operation] According to the above configuration, even if the DMA transfer is being performed between the external device and the storage device of the host device, this D
Since the MA transfer is performed via the DMA dedicated bus, the arithmetic processing circuit can access the internal storage circuit via the system bus.

[Embodiment] An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a communication control circuit according to an embodiment of the present invention. In this communication control circuit, a communication control circuit 100a for inputting / outputting data to / from an external communication partner, and a host processor 200 and a RAM 201 for performing higher processing on the communication control circuit 100a are connected to a processor bus P.
B and other control lines are connected to each other.

The internal configuration of the communication control circuit 100a will be described below. 1
Reference numeral 02 denotes an ALU (arithmetic unit), which has a built-in accumulator and executes arithmetic processing using this accumulator. The ALU 102 has an address output terminal connected to the address bus AB and a data output terminal connected to the data bus DB. These address buses AB
The system bus SB is composed of the data bus DB and the data bus DB. Reference numeral 103 denotes a RAM, which is used as a temporary storage of a macro instruction or a calculation processing result of the ALU 102. The RAM 103 is addressed by the address data on the address bus AB, and inputs / outputs data via the data bus DB. Reference numeral 104 denotes a micro program ROM (read only memory) in which a micro program corresponding to a macro instruction is stored. And
When the address data corresponding to the macro instruction is supplied via the address bus AB, the code of the microprogram corresponding to this is output to the data bus DB.

Reference numeral 105 denotes an input / output buffer, which is connected to the address bus AB, the data bus DB, and the input / output interface 106, and temporarily stores data input / output between the communication control circuit 100a and the upper processor 200. The input / output interface 106 is connected to the above-mentioned input / output buffer 105 and the DMA controller 107, which are connected to the host processor 200 and R.
Input / output control of data to / from the AM 201 is performed. DMA
The controller 107 is connected to the data bus DB, the DMA dedicated buses B1 and B2, and the input / output interface 106, outputs a control signal according to a DMA request generated externally or internally, and outputs the control signal to the memory in the communication control circuit 100a. It controls the DMA operation with the external RAM 201.

108 is a transmission FIFO (first-in first-out) register, 109
Is a PS (parallel-serial) conversion circuit, and 110 is an HDLC (high level data link control) frame assembly circuit. These perform a series of processes described below when transmitting data from the communication control circuit 100a to an external communication partner. First, the transmission FIFO register 108
Captures the data on the data bus DB or the DMA dedicated bus B1 and sequentially stores the captured data.
Here, this transmission FIFO register is internally provided with a selector, and by switching this selector by a control signal from the ALU 102, the data on the data bus DB and the data on the DMA dedicated bus B1 are switched and fetched. Is able to. The data stored in the transmission FIFO register is supplied to the P-S conversion circuit 109 in order from the previously stored data, and P-S
It is converted into serial data in the S conversion circuit and supplied to the HDLC frame assembly circuit 110. And HDLC
In the frame assembly circuit 110, this serial data is 8
Frames are grouped into a plurality of blocks each having one bit as a block unit, and a start flag, an address, control information, FCS (frame check sequence) information and a close flag are added to each frame.
The transmission format conforms to the LC transmission procedure and is transmitted to the communication partner.

111 is an HDLC frame decomposing circuit, 112 is an SP
A (serial-parallel) conversion circuit 113 is a reception FIFO register. In the HDLC frame decomposition circuit, the received data
(HDLC format) to the above-mentioned start flag,
The address, control information, FCS information and close flag are removed and serial data is output. In the SP conversion circuit 112, this serial data is parallelized in units of 8 bits and output as parallel data. Then, this parallel data is sequentially stored in the reception FIFO register 113.
The data stored in the reception FIFO register 113 is sequentially output to the data bus DB and the DMA dedicated bus B2 from the previously stored data.

Reference numeral 114 is a command status register, which generates control information based on the data on the address bus AB and the data bus DB, and supplies this control information to each section in the circuit.

Next, the operation of this communication control circuit will be described.

Normal operation mode Address data is output from the ALU 102 to the address bus AB. Then, arbitrary data is read from the storage address of the RAM 103 designated by the address data and output to the data bus DB. The data on this data bus DB is read into the ALU 102 and
At 102, an operation based on the corresponding data is performed. Then, the calculation result is the microprogram ROM.
If the access is to 104, the microprogram ROM 104 is enabled via the address bus AB, and the corresponding microprogram code is read to the data bus DB. Then, this microprogram code is read into the ALU 102, and the ALU1
At 02, the corresponding operation is performed. These are arbitrarily combined and the calculation is repeated.

DMA Mode In this communication control circuit, the communication control circuit 100a performs a communication procedure with an external communication partner. Then, when this communication procedure is completed, data is input / output between the RAM 201 and an external communication partner via the communication control circuit 100a. Here, this data input / output is RA
M201, transmission FIFO register 108 and reception FI
This is performed by a DMA operation with the FO register 113.

The DMA operation will be described below. RAM201
When a predetermined storage data in the storage device is transmitted to an external partner, the start address value of the storage data in the RAM 201 and the count value representing the length of the storage data in the RAM 201 are the processor bus PB → the input / output interface 1
The data is taken in by the ALU 102 via a route of 06 → input / output buffer 105 → data bus DB. And AL
The U 102 sets the start address value and the count value in the address counter and the data counter in the DMA controller 107. In addition, the ALU 102 has a TEI (terminal identification number) of a communication partner prior to data transmission.
Control information on SAPI (service access point identification number) and transmission contents is set in the data bus DB → transmission FIFO register 108 in advance. And A
The LU 102 switches the selector inside the transmission FIFO register 108 so as to read the DMA data on the DMA dedicated bus B1. This allows RAM2
The DMA transfer from 01 to the transmission FIFO register 108 is on standby.

The DMA controller 107 uses the DMA request signal HLDR.
Q is output to the upper processor 200. Upon receiving this signal, the upper processor 200 releases the processor bus PB at the time when the RAM 201 is not accessed,
At the same time, the DMA permission signal HL is sent to the DMA controller 107.
Output DAK. Upon receiving this signal, the DMA controller 107 supplies the output data of the address counter to the RAM 201 as a read address via the input / output interface and the processor bus PB. As a result, the storage data is read from the RAM 201, and the transmission FIFO register 1 is sent via the path of the processor bus PB → the input / output interface 106 → the DMA dedicated bus B1.
DMA transfer to 08. And one data is DM
When A is transferred, the address counter is incremented and the data counter is decremented in the DMA controller 107, and the right to use the processor bus PB is once returned to the upper processor 200. Then, the DMA controller 107 determines whether or not the data counter is “0”, and when the determination result is “NO”, the above-mentioned DMA transfer is repeated again. Then, when the data counter in the DMA controller 107 reaches "0", the DMA transfer ends.

Here, the address bus AB and the data bus DB in the communication control circuit 100a are not used as the DMA transfer path. Therefore, even during the DMA transfer, the ALU 102 is in the RAM via the address bus AB and the data bus DB.
103 and the microprogram ROM 104 can be accessed. Further, the upper processor 200 is
When there is a DMA request from the DMA controller 107, the processor bus PB only needs to be released at a time when the RAM is not used, so that the processing is not interrupted by the DMA operation.

In this way, the DMA transfer from the RAM 201 to the transmission FIFO register 108 is performed. In parallel with this, the data of the transmission FIFO register 108 is sequentially taken out and the P-S conversion circuit 109 and the HDLC frame assembly circuit 110 are transferred. Is transmitted to an external communication partner via the Internet.

Received data from an external communication destination is stored in the RAM 201.
In the case of MA transfer, data transfer is performed by the same operation.

"Effects of the Invention" As described above, the communication control circuit according to the present invention includes an arithmetic processing circuit, an internal storage circuit, a system bus, and a DM.
A communication control circuit having an A dedicated bus, a DMA controller, and a transmitting / receiving means, wherein the arithmetic processing circuit is connected to the internal storage circuit via the system bus, and the transmitting / receiving means is connected to an external device. The DMA controller connects the system bus to the transmission / reception means during normal operation, and transfers the data to and from the storage device of the host device when the DMA transfer is requested from the host device. DMA via the dedicated bus connected to the transmission / reception means via the dedicated bus and between the external device and the storage device of the host device and the transmission / reception means
Since the transfer is controlled, even if the DMA transfer is being performed between the external device and the storage device of the host device, this DMA transfer is performed via the DMA dedicated bus, so that the arithmetic processing is performed. The circuit has the advantage that it can access internal storage circuits via the system bus and thus can provide very high processing power.

[Brief description of drawings]

FIG. 1 is a block diagram of a communication control circuit according to an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional general data processing circuit. 100a ... communication control circuit, 102 ... ALU, 103
...... RAM, 108 ...... Transmission FIFO register, 113
...... Reception FIFO register, AB ...... Address bus, D
B ... Data bus, B1, B2 ... DMA dedicated bus, 1
07 ... DMA controller.

Claims (2)

[Claims] 1. An arithmetic processing circuit, an internal storage circuit, a system bus, a DMA dedicated bus, a DMA controller,
A communication control circuit having a transmitter / receiver, wherein the arithmetic processing circuit is connected to the internal storage circuit via the system bus, and the transmitter / receiver exchanges data with an external device. In the normal operation, the DMA controller connects the system bus to the transmission / reception means,
At the time of transfer request, the storage device of the upper device is connected to the transmission / reception means via the DMA dedicated bus, and via the DMA dedicated bus and the transmission / reception device between the external device and the storage device of the upper device. A communication control circuit for controlling DMA transfer. 2. The communication control circuit according to claim 1, wherein the system bus includes an address bus and a data bus, and the dedicated DMA bus includes only a data bus.