JPH03160550A - Endian converting system - Google Patents

Abstract

PURPOSE:To enable the normal exchange of data even between the processor of various endian by storing the data in a common memory while swapping the high-order byte and low-order byte of the communication data by a data swap control part when the communication data are the data. CONSTITUTION:The communication data between a local processor 36 on an I/O adapter 34 side and a main processor 38 on a system side are once stored in an information register 33. On the system side, it is discriminated whether the communication data are the data or a parameter, and the information are sent from the system side through a transmission/reception control part 32 to a data swap control part 35. By this data swap control part 35, data swap or data through control is executed to the communication data stored in the information register 33 and the data are stored in a local memory 31. Thus, the normal exchange of the communication data can be executed even between the processors of the various endian.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field J] The present invention relates to an endian conversion method for a data processing system that uses a common memory and exchanges data between processors. This paper relates to an endian conversion method that can perform the following.

[Conventional technology J] Conventional data processing systems, for example, as shown in Figure 2,
It includes a processing module 22.23 composed of processors 24, 25 and local memories 26.27 associated with them, and a common memory 28, and a bus 2.
When exchanging data between processing modules on l,
Data was exchanged via the common memory 28.

In this case, the processors 24 and 25 need to have the same endianness indicating how the upper and lower bytes of word-sized data are arranged.

For example, when using a Motorola processor, when writing word-sized data to the memory 28, the upper byte is written to the lower address, and the lower byte is written to the higher address.

In other words, a pick-endian system is used. In addition, Intel processors use a little endian method in which upper and lower bytes are written in reverse.

Therefore, if the endianness of the processors 24 and 25 is different, for example, the processor 24 writes "'O I 2 3H" as word data in the communication memory 28, and the processor 25 reads the data as "2301H".
I recognize that.

Note that related devices of this type include, for example, Japanese Patent Application Laid-open No. 119066/1983.

[Problems to be Solved by the Invention] In the above conventional technology, data exchange between processors of the same endian is performed normally. In the case of processors of different endianness, due to endianness differences,
There was a problem that data exchange was not performed normally.

SUMMARY OF THE INVENTION An object of the present invention is to solve these problems and provide an endian conversion method that allows normal data exchange between processors of different endians using I-RF.

[Means for solving problem a]

In order to achieve the above object, the endian conversion method of the present invention includes a local (front end) processor, and a transmission/reception buffer that stores operation regulation parameters (including commands) indicating control information thereof and transmission/reception data,
An I/O adapter has a common memory (local memory) that can be accessed in word size from both the local processor and the main processor of the system device, and the main processor has a different endian from the local processor. Has main memory and bus controller,
In a data processing system that includes a system device equipped with an I/O adapter and a system bus that connects the I/O adapter and the system device, the I/O adapter has the ability to communicate with other systems under the control of the local processor. a transmission/reception control unit that transmits and receives communication data, an information register that stores swap information for the upper byte and lower byte of word-sized data transferred via the main processor and system bus, and the values stored in the information register. Equipped with a data swap control section controlled by
Information indicating whether the communication data between the local processor and the main processor is data or parameters is sent from the system device side to the data swap control unit via the transmission/reception control unit, and the I/O adapter side sends information indicating whether the communication data between the local processor and the main processor is data or parameters. When information is stored in the information register and the communication data is data, the data swap control section is characterized in that the upper byte and lower byte of the communication data are swapped and stored in the common memory.

[Operation] In the present invention, in a system that performs data communication between processors of different endianness, there is a transmission/reception control section that transmits and receives communication data between those processors, and a system that transmits data from the main processor on the system side via the system bus. The following operation is performed by providing an information register having swap information of the upper byte and lower byte of word-sized data and a data swap control section in the I/O adapter.

That is, communication data between the local processor on the I/O adapter side and the main processor on the system side is temporarily stored in the information register. The system determines whether the communication data is data or a parameter.
m is sent from the system side to the data swap control unit through the transmission/reception control unit.

The data swap control unit performs data swap or data through control on the communication data stored in the ++7 information register and stores it in the local memory.

As a result, even between big brother endian processors,
Normal communication data can be exchanged.

[Example] An example of the present invention will be described below with reference to the drawings. FIG. 3 is a configuration diagram of a data processing system in one embodiment of the present invention.

In FIG. 3, 3l is a local memory, 32 is a transmission/reception control unit, 33 is an information register, 34 is an I/O adapter,
35 is a data swap control unit, 36 is a local processor, 37 is a bus controller, 38 is a main processor, 39 is a main memory. 40 is a system device, and 4l is a system bus. In addition, the I/O adapter 34 (local memory 31, transmission/reception control unit 32, information register 33
, data slip 1νjga section 35, local processor 36) and a system device 40 (bus controller 37, main processor 38) equipped with an I/O adapter 34.
, main memory 39) are connected to the system bus 41 to exchange data.

This local memory 3l can be accessed in word size from both the main processor 38 and the local processor 36, and the transmission/reception control # section 32 transmits and receives communication data between the main processor 38 and the local processor 36.

Further, the information register 33 has swap information of the upper byte and lower byte of data (word size) transferred via the main processor 38 and the system bus 4l.

The data swap control unit 35 also controls the information register 33
Data through control or data swap control is performed on communication data based on the swab information stored in the .

Further, the local processor 36 is a pick-endian or a true-endian processor, and is a different endian bus setter from the main processor 38.

The bus controller 37 also controls a system bus 4l that connects the I/O adapter 34 and the system device 40.

Further, the main processor 38 is a processor on the system side and has a different endian from the local processor 36.

Further, the main memory 39 is a memory of the system main body that stores communication data from the I/O adapter 34.

Further, the system bus 4l connects the local processor 36 and the main processor 38.

Next, the configuration and functions of the data swap control section 35 will be described.

4 is a logical configuration diagram of the data swap control section of FIG. 3, and FIG. 5 is an explanatory diagram of the logical configuration of the data swap control section of FIG. 3.

In Fig. 4, 42 to 45 are selector sections (SEL);
46 is a latch section, and 47 is a bus control signal control section.

This bus control signal q-ffIlm section 47 is
It has a control signal indicating whether the communication data from the system side to the I/O adapter 34 is a parameter or data, and based on that information, the communication data can be data swapped or data through, so that normal communication data can be transmitted between processors of different endianness. It is possible to send and receive.

The functions of the data swap system IX) 835 are shown in FIG. That is, when the communication data is data, data swap control is performed to reverse the upper byte and lower byte of the word-sized data, as shown by the solid line. Furthermore, if the communication data is a parameter, data through control is performed and the upper and lower bytes are left unchanged.

Next, the main processor 38 and the local processor 36
This section describes the transmission and reception of communication data between the two.

FIG. 1 is a flowchart showing an endian conversion method in an embodiment of the present invention, and FIG. 6 is an explanatory diagram of endian conversion in an embodiment of the present invention.

In this embodiment, when communication data is transmitted from the system side to the I/O adapter 34, the communication data passes through the transmission/reception control section 32 and is stored in the information register 33. that time,
The I/O adapter 34 receives the communication data from the system side, and also receives information indicating whether the communication data is data or parameters.

The information is sent to the data swap control unit 35 through the transmission/reception control unit 32, stored in the information register 33, and
It is checked whether it is data or a parameter (101).

If the result is data, the swap control unit 35 controls the data swap and sets a parameter instructing endian conversion in the information register 33 (1 0 2
). That is, when data is transferred between the local memory 31 and the main memory 39 as shown in FIG. 6(a), mutually accurate data can be obtained by reversing the upper and lower bytes.

If it is a parameter, data through control is performed and the parameter to suppress endian conversion is stored in the information register 3.
Set to 3 (+03). The processing in this case is shown in FIG. 6(b).

As a result, the communication data is normally stored in the local memory 31 (104), and then the communication data is stored in the local memory 3! From there, the data is withdrawn (105), and the process moves to sending/receiving or one-to-one operations (+06).

〔Effect of the invention〕

According to the present invention, normal data exchange between processors of different endianness can be performed via a co-tracing memory, such as a local memory, that can be accessed by both processors.

[Brief explanation of the drawing]

FIG. 1 is a flowchart showing an endian conversion method in an embodiment of the present invention, FIG. 2 is an explanatory diagram showing a conventional data exchange method, and FIG. 3 is a configuration diagram of a data processing system in an embodiment of the present invention. 4 is a logical configuration diagram of the data swap control section in FIG. 3, FIG. 5 is an explanatory diagram of the logical configuration of the data swap control section in FIG. 3, and FIG. 6 is an illustration of endian conversion in an embodiment of the present invention. It is an explanatory diagram. 2l: System bus, 22.23: Processing module, 2
4, 25: Processor, 26. 27: Local memory,
28: common memory, 31: local memory, 32: transmission/reception control section, 33: information register, 34: I/O adapter, 35: data swap control section, 36: local processor, 37: bus controller, 38: main processor, 39: Main memory. 40: System installation L4 1
: System bus, 42 to 45: Selector section (SEL),
46: latch section, 47: path control signal control section. Figure l Figure 5 Figure 35 Figure 6 (Part 1) (a) Local memory Main memory Figure 6 (Part 2) (b) Local memory Main memory

Claims (1)

[Claims] 1. A common memory including a local processor and a transmission/reception buffer for storing operation regulation parameters indicating control information of the local processor and transmission/reception data, and accessible in word size from both the local processor and the main processor of the system device. An I/O adapter, a main processor having a different endian from the local processor, a main memory, and a bus controller; In a data processing system equipped with a system bus to be connected, the I/O adapter includes a transmission/reception control unit that transmits and receives communication data with other systems under the control of the local processor, and a transmission/reception control unit that transmits and receives communication data to and from other systems via the main processor and the system bus. an information register that stores swap information for the upper byte and lower byte of word-sized data to be transferred, and a data swap control unit that is controlled by the stored value of the information register, Information indicating whether communication data between the processor and the main processor is data is sent to the data swap control unit via the transmission/reception control unit, and the I/O adapter side stores the information in the information register. An endian conversion method characterized in that, when the communication data is data, the data swap control unit swaps the upper byte and lower byte of the communication data and stores the swapped data in the common memory.