JPH04205047A - Data processor - Google Patents

Abstract

PURPOSE:To make it possible to control operation of main and sub control sections by connecting the main control section to the sub-control section via a coupling means of substituting part of memory space of the main control section for a program space of the subcontrol section to load the main control section with internal software from an external memory. CONSTITUTION:CPU 34 reads a base program for CPU 35 from external memory 42, and writes the base program and an interrupt vector area in a dual port RAM 43. The CPU 34 releases CPU 35 from reset to operate the CPU 35 from the base program, writes an internal software request command in RAM 43, generates an interrupt in CPU 34, and waits for termination of loading of internal software. CPU 34 reads a command area to release the interrupt, reads internal software from CPU 35 and writes it in RAM 43, and further writes a command indicating termination of loading in RAM 43 to terminate interrupt processing by CPU 34. In CPU 35, a command area of RAM 43 is read to release interrupt, reads a data area, and writes internal software in the program area of CPU 35.

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention has a plurality of control units (hereinafter referred to as CPUs), and is capable of transmitting and receiving data between the plurality of CPUs or with other peripheral devices. The present invention relates to a data processing device that performs.

[Conventional technology]

2. Description of the Related Art Conventionally, data processing apparatuses shown in FIGS. 6 and 7 are known as data processing apparatuses that transmit and receive data using a plurality of CPLIs.

The data processing device shown in FIG. [Data is exchanged between J and the peripheral device of the other CPU. Furthermore, a ROM 5 that stores the internal software of the CPU 1 and a RAM 6 for temporarily storing various data are connected to the path line of the CPLI 1, and the internal software of the CPtJ 2 is also stored in the CPU 2. ROM 7 and R for temporarily storing various data
AM 8 is connected.

Further, the data processing device shown in FIG. 7 is a CPLI 11
, the CPLI 12 and the external memory 13 are connected to the mother bus 17 via interfaces 14.15 and 16, respectively, for data transfer between the CPU 1.12 or other peripheral devices. ,CPU
Connected to each path line of l1.12 are a ROM 18.19 that stores the internal software of each CPtJ, a RAM 20.21 that temporarily stores various data, and an I10 port 22.23 that exchanges data. There is.

[Invention or problem to be solved]

In the conventional data processing device described above, each C
A dedicated system ROM is used for each PU. Therefore, when changing the content of data processing, it is necessary to replace the system ROM of each CPU, or to provide a changing means for each CPU so that the processing content can be changed in advance.

However, data processing differs in content and processing method depending on the user or the data to be processed.
If a dedicated system ROM is used for each U, it may not be possible to handle changes in processing contents. For example, when adding new hardware to improve processing capabilities, it may be possible to connect the hardware without any problems, or it may be difficult to change the software that controls it.

The present invention was made in view of these conventional problems, and an object of the present invention is to provide a data processing device that is appropriately configured so that software changes can be easily made and data processing can be performed efficiently. do.

[Means and operations for solving the problem] In order to achieve the above object, the present invention includes a main control section that loads and operates internal software and application software from an external memory, and at least a main control section that does not have dedicated internal software in advance. one sub-control unit, and a coupling means connected between the main control unit and the sub-control unit and using a part of the memory space of the main control unit as a program space of the sub-control unit; Internal software and application software are loaded from the external memory to the coupling means to control the operations of the main control section and the sub-control section.

〔Example〕

FIG. 1 shows an embodiment of the present invention.

This embodiment shows an image processing device, in which an analog image signal from a TV left camera 1 is converted into a digital signal by an A/D converter 32 and stored in an image memory 33. CPU 34 for image data
The CPU 35 then performs necessary image processing, and the image-processed data is converted into an analog image signal by a D/A converter 36 and displayed on a CRT 37.

The CPU 34 is connected to the image memory 33 via a pass line, and a ROM 38 and a RAM 39 are connected on the pass line. The CPU 35 also has a RAM 40 and various I10 ports 4 on its pass line.
Connect 1.

In this embodiment, an external memory 42 such as an IC card, floppy disk, or hard disk is connected to the pass line of the CPU 34, and a dual port RAM 43 is connected between the pass line of the CPU 34 and the pass line of the CPtJ 35. . As shown in FIG.
4. Command area 45 of CPtJ 35, subcommand area 46, interrupt vector area 47 of CPLI 35,
As a memory configuration having a base program area 48 and a data area 49 for the CPU 35, this dual-baud RAM 43 has a part of the memory space of the CPU 34 and a part of the memory space of the CPU 34.
35 memory spaces.

In this way, data is read from the external memory 42 and stored in the dual port RAM 43, and based on this, the data is sent to the CPU 34, 35 through the dual port RAM 43.
The image data stored in the image memory 33 is processed by transferring data between the two. Note that the memory capacity of the dual port RAM 43 is preferably set to be equal to or more than one line of the image in order to perform image processing efficiently. Also,
When the CPU 35 turns on the device, the CPU 3
It is reset by the reset signal from 4.

The operation of this embodiment will be explained below with reference to the flowcharts shown in FIGS. 3 to 5.

When the device is powered on, CPU 35
The CPU 34 enters a reset state in response to a reset signal from 4, and during this period the CPU 34 operates according to the flowchart shown in FIG. That is, first, the CPtJ 34 reads the base program of the CPIJ 35 from an external memory such as an IC card. This base program is based on CP [
This is for reading a program as data from the J35 or dual port RAM 43 and writing it into the memory space of the CPU 35.

Next, the CPU 35 writes the base program for the CPU 35 read from the external memory 42 into the base program area 48 according to the memory map of the dual port RAM 43 shown in FIG.
35 interrupt vector area 47 is written. Thereafter, the reset of the CPU 35 is canceled by the CPU 34, and the CPU 35 starts operating from the base program.

When the CPU 35 starts its operation, it first writes an internal software request command to the command area 44 of the CPU 34 of the dual port RAM 43 shown in FIG. 2 to generate an interrupt to the CPU 34, and then,
Wait for the internal software to load or finish before managing the device.

On the other hand, when an interrupt occurs, the CPU '34 releases the command area 44 of the CPLI 34 of the dual port RAM 43 to release the interrupt, and also performs interrupt processing according to the flowchart shown in FIG. 4 according to the contents of the command. In other words, in this case, since it is an internal software load command, first load the CP from the external memory.
Read the internal software of U 35 as data, dual port)! 'Write to data area 49 of lAM43. Next, a command indicating the end of loading is written to the command area 45 of the CPU 35, and thereby the CPU 35
Generates an interrupt to CPIJ 34 and ends the interrupt processing.

When the CPU 35 generates this interrupt, the command area 4 of the CPU 35 in the dual port RAM 43 is
5 to cancel the interrupt, and according to the contents of the command, interrupt processing is performed according to the flowchart shown in FIG. That is, in this case, first, it recognizes that it is a command or an internal memory load end command, reads the data area 49 of the dual port RAM 43, and transfers the read internal software to the program area (memory space inside).

Next, the CPU 34 determines whether all internal software has been loaded into the program area of the CPLI 35 and whether it is necessary to continue loading the internal software.
If it is unnecessary, set the load end flag and end the interrupt processing. Based on this load completion flag, the CPU 35 recognizes that the internal software has been loaded and starts executing the internal software.

In addition, in this embodiment, the dual port RAM 43 has C.
Since the interrupt vector area 47 for the PU 35 is provided, the C
It becomes possible to rewrite the CPU 34 or its interrupt vector in response to an interrupt from the PU 35. Therefore, even if the CPU 35 receives an interrupt based on the same interrupt condition, the operation can be changed depending on the CPU 34 condition.

In this way, according to this embodiment, the internal software can be transferred to the CPU 35 without providing a system ROM.
34, the operations of the CPUs 34 and 35 can be easily changed by changing the external memory 42.

Note that the present invention is not limited to the above-described image processing apparatus, but can be effectively applied to other data processing apparatuses. Also,
In the embodiment described above, one sub CPU 35 is connected to the main CPU 34, but the main CPU 34 is connected to the sub CPU 35.
Even when connecting multiple sub CPUs to a PU, each sub CPU
The invention can be effectively applied by connecting the PUs through similar dual-port hRAMs.

〔Effect of the invention〕

As described above, according to the present invention, the main control section and the sub-screening section are connected via the coupling means that uses a part of the memory space of the main control section as the program space of the sub-screening section. Since the main control section loads the internal software from the external memory and controls the operations of the main control section and the sub-control section, it is easy to change the software by changing the external memory. Data processing can be performed efficiently.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing the memory configuration of the dual-port RAM shown in FIG. 1, and FIGS. Flowcharts for explaining the operation of the embodiment shown in FIGS. 6 and 7.
The figure is a diagram for explaining a conventional technique. 31...TV camera 32...A/D converter 33...Image memory 34.35...CP
tJ36...D/A converter 37...CRT
38...ROM 39.40...R
AM41...I10 port 42...External memory 43
...Dual port RAM Figure 1 Figure 2 Figure 3 CPLJ34 I shell

Claims (1)

[Claims] 1. A main control unit that loads and operates internal software and application software from an external memory, at least one sub-control unit that does not have dedicated internal software in advance, and is connected between the main control unit and the sub-control unit, a coupling means that uses a part of the memory space of the main control section as a program space of the sub-control section; the main control section loads internal software and application software from the external memory to the coupling means; A data processing device configured to control operations of a main control section and the sub-control section.